A new analytical model for optimizing SOI LDMOS with step doped drift region

In this paper, a new theoretical breakdown model of SOI RESURF LDMOS with step drift doping profile is proposed. According to this model, the 2-D electric field distributions of drift regions are investigated for both the incompletely and completely depleted cases. The doping profile and step number are optimized to improve the breakdown voltage and reduce fabrication cost. Finally, SOI LDMOS with various step numbers have been made using a 3 μm-thick top silicon layer and a 1.5 μm-thick buried oxide layer. The experiment results indicate that two-step drift doping can enable increase in the breakdown voltage by as much as 40% and decrease in the on-resistance by as much as 16% in comparison to the conventional LDMOS with uniformly doped drift region.     

An analytical model for snapback in n-channel SOI MOSFET's

An analytical snapback model for n-channel silicon-on-insulator (SOI) transistors with body either tied to the source or floating is been presented. The snapback is modeled as a nonlinear feedback system leading to negative transconductances from which the jump in current can occur at the point of instability. The crux of this model is based on the strong dependence of the transistor threshold voltage on the body potential when the body potential is above the transistor surface potential at strong inversion. No parasitic bipolar action is invoked to account for the snapback phenomena. The model correctly predicts the occurrence of hysteresis/latch phenomena and the conditions under which the current jump occurs despite some gross approximations in the electric field and the injection level. Results obtained from this model show good agreement with experimental data measured from SIMOX devices fabricated on 0.3-μm epi film     

An analytical back-gate bias effect model for ultrathin SOI CMOSdevices

An analytical back-gate bias effect model for ultrathin SOI CMOS devices is presented. As verified by PISCES results, the analytical SOI CMOS back-gate bias effect model provides a much better accuracy in the integral potential distribution and the threshold voltage as the back-gate bias is changed     

Design guideline for minimum channel length in silicon-on-insulator (SOI) MOSFET

This brief proposes a preliminary design guideline for the minimum channel length in silicon-on-insulator (SOI) MOSFETs that is based on simulations of device characteristics. The simulations examine a wide variation in many device parameters to comprehensively evaluate device characteristics. A characteristic parameter that can successfully describe the minimum channel length is found. It is suggested that a sub-20-nm-channel single-gate SOI MOSFET with suppressed short-channel effects can be stably realized by optimizing its device parameters.     

A one-dimensional analytical model for the dual-gate-controlledthin-film SOI MOSFET

A one-dimensional analytical model for dual-gate-controlled SOI MOSFETs is presented and applied to a stacked p-channel MOSFET fabricated by epitaxial lateral overgrowth (ELO). The authors found and modeled a nonlinear dependence of front-gate threshold voltage on back-gate voltage if threshold is defined by a constant current instead of a constant silicon-surface potential. It is demonstrated by comparison of subthreshold slopes that surface potentials are not pinned to the onset of strong inversion or accumulation. Accurate one-dimensional modeling is a necessity for device characterization and a precondition for general SOI models for circuit simulation     

A novel SOI lateral-power MOSFET with a self-aligned drift region

In this letter, a novel drift-region self-aligned SOI lateral-power MOSFET using a partial exposure technique is proposed and demonstrated for RF power amplifier applications. The drift self-aligned structure was achieved using a simple process and without the need of an additional mask. Furthermore, the drift length can be controlled conveniently using different layout designs. The fabricated SOI power device has a breakdown voltage of over 20 V. Using a 0.7-/spl mu/m nonsilicide technology, the cutoff frequency (f/sub t/) and maximum oscillation frequency (f/sub max/) of the device are 10.1 and 13.7 GHz, respectively.     

An analytical model for fully depleted single gate SOI MOS transistors including lattice temperature effects

An analytical model for fully depleted SOI MOSFETs is presented. Major small geometry effects such as carrier velocity saturation, mobility degradation, channel length modulation, and drain induced barrier lowering are included. Device self heating due to low thermal conductivity of a buried oxide layer is included in carrier mobility modelling. Thermal effects are also included in threshold voltage expression. Source, drain, and channel resistance effects are also included. Modelled results are then compared to available measured data and are shown to be in very good agreement.     

700V折叠漂移区高压器件新结构

A new high-voltage LDMOS with folded drift region(FDR LDMOS) is proposed. The drift region is folded by introducing the interdigital oxide layer in the Si active layer, the result of which is that the effective length of the drift region is increased significantly. The breakdown characteristic has been improved by the shielding effect of the electric field from the holes accumulated in the surface of the device and the buried oxide layer. The numerical results indicate that the breakdown voltage of 700 V is obtained in the proposed device in comparison to 300 V of conventional LDMOS, while maintaining low on-resistance.     

An analytical back gate bias dependent threshold voltage model forSiGe-channel ultrathin SOI PMOS devices

An analytical threshold voltage model for SiGe-channel ultrathin SOI PMOS devices is presented. As confirmed by the PISCES simulation results, the analytical model provides a good prediction on the threshold voltage. According to the analytical-formula, depending on the back gate bias, the SiGe-channel SOI PMOS device may have a conduction channel at the top or the bottom of the SiGe channel or at the top of the field oxide     

An analytic model for thin SOI transistors

A simple charge sheet model is shown to provide a surprisingly accurate approximation to the behavior of a long-channel FET fabricated in a silicon-on-insulator (SOI) structure with a very thin silicon film. Using this charge sheet model, an accurate calculation of the I-V characteristics of transistors fabricated in these thin films is derived. Included in the results is an expression for the threshold voltage which shows, among other things, that the threshold voltage of suitably designed transistors is only logarithmically dependent on the thickness of the silicon film     

An analytical fully-depleted SOI MOSFET model considering theeffects of self-heating and source/drain resistance

In this paper, we present a new and analytical drain current model for submicrometer SOI MOSFET's applicable for circuit simulation. The model was developed by using a two-dimensional (2-D) Poisson equation, and considering the source/drain resistance and the self-heating effect. Using the present model, we can clearly see that the reduction of drain current with the parasitic series resistance and self-heating effect for typical SOI devices. We also can evaluate the impact of series resistance and self-heating effects. The accuracy of the presented model has been verified with the experimental data of SOI MOS devices with various geometries     

A modified two dimensional analytical model for short-channel fully depleted SOI MESFET's

Analytical modeling of channel potential of SOI MESFET can be obtained by solving Poisson's equation to derive an expression for channel potential. Superposition method is an accurate technique for solving Poisson's equation, in which the solution of the 2-D Poisson's equation is represented as the sum of the 1-D Poisson's equation and a 2-D Laplace's equation solutions. In the existing models applying this method, the authors tried to solve 2-D Laplace's equation by using approximations [1] or modifying the boundary conditions [2] producing inaccurate results. In this report, a new methodology is applied to develop a modified analytical model for the channel potential of fully depleted SOI MESFET's, in which the drawbacks of the previous models are significantly eliminated. Using this model, the subthreshold performance of the device including channel potential, threshold voltage, drain current, and subthreshold swing under various conditions have been studied, plotted, and compared with TCAD simulation and experimental results. It is concluded the proposed model has been improved in term of accuracy compared to other existing models.     

一种VOD系统的分析模型

对全连网络的分布式视频点播系统进行了性能分析，提出了一种VOD系统的分析模型，可以利用这一模型计算视频请球发生拥塞的概率以及网络的带宽要求，同时还可以得到在通信和存储费用两者之间的一个折衷方案。     

An analytical model for the determination of optimal outputreflectivity and fiber length in erbium-doped fiber lasers

An analysis relating the output power of erbium-doped fiber lasers to the output mirror reflectivity r_out is performed, and a closed-form expression valid for r_out<0.95 is obtained. It shows that the laser output power is nearly independent of the output reflectivity when 0.5<r_out<0.95. The closed-form expression is used to study the dependence of the output power with laser wavelength and confirms the large tuning range (60 nm) already reported. However, it is shown that the tuning range is greatly increased (up to more than 100 nm) if r_out is chosen near 0.9. Finally, an approximate expression for the optimal fiber length needed to achieve maximum laser output is derived     

An analytic model for estimating the length of the velocitysaturated region in GaAs MESFETs

An analytical model is presented for estimating the length of the portion of an FET channel with velocity saturated carriers. The model is based on previous work proposed by Pucel et al. [1974, 1975], and has been adapted to remove discontinuities between extreme bias conditions. The need for complicated numerical solutions has also been removed making the model suitable for use with circuit simulators. Results obtained from the model agree well with previously proposed models over a wide range of bias conditions where velocity saturation can be either dominant or negligible, depending on the overall channel length and bias conditions     

A new double gate SOI LDMOS with a step doping profile in the drift region

uences of device parameters on BV and Ron, sp are investigated by simulation. The results indicate that BV is increased by 35.2% and Ron, sp is decreased by 35.1% compared to a conventional SOILDMOS.     

漂移区阶梯掺杂的双栅SOI LDMOS研究

A new double gate SOI LDMOS with a step doping profile in the drift region is proposed. The structure is characterized by one surface gate and another embedded gate under the P-body region. The broadened current flow path and the majority carrier accumulation layer on the side wall of the embedded gate reduce the specific on-resistance （Ron, sp）. The electric field distribution is improved due to the embedded gate and step doping profile, resulting in a high breakdown voltage （BV） and low Ron, sp. The influences of device parameters on BV and Ron, sp are investigated by simulation. The results indicate that BV is increased by 35.2% and Ron, sp is decreased by 35.1% compared to a conventional SOI LDMOS.     

An analytical two-dimensional model for silicon MESFETs

A model that predicts small-geometry effects in Si MESFETs has been developed. It is based on a two-dimensional (2-D) analytical solution of Poisson's equation in the subthreshold regime that applies to the junction-isolated structure typical of silicon devices. The model is in excellent agreement with numerical simulations from the PISCES 2-D device analysis program. The analytical model provides the physical basis for a subthreshold current model for small-geometry MESFETs. A scaling scheme for MESFETs, derived from the analytical model, that predicts a minimum-acceptable gate length of 0.15 μm for these devices is proposed     

An analytical breakdown model for short-channel MOSFET's

Avalanche-induced breakdown mechanisms for short-channel MOSFET's are discussed. A simple analytical model that combines the effects due to the ohmic drop caused by the substrate current and the positive feedback effect of the substrate lateral bipolar transistor is proposed. It is shown that two conditions must be satisfied before breakdown will occur. One is the emission of minority carriers into the substrate from the source junction, the other is sufficient avalanche multiplication to cause significant positive feedback. Analytical theory has been developed with the use of a published model for short-channel MOSFET's. The calculated breakdown characteristics agree well with experiments for a wide range of processing parameters and geometries.     

An analytical model for adaptive routing networks

Real-time network routing (RTNR) is a new adaptive routing method. With RTNR, switches have a simple way of exchanging link status bit map information, thereby determining the availability and load conditions of the direct and all two-link paths to the destination. Link busy-idle status is exchanged between the network nodes using a bit map data exchange through the common channel signaling (CCS) network, and calls are set up where there is the most available capacity in the network. To date the analysis of RTNR networks has been limited to simulation models. The present authors develop an analytical model for the AT&T network under RTNR, which is shown to provide good agreement with simulation models. The analytical model for RTNR networks uses an Erlang fixed point method to solve the nonlinear equations describing dynamical network behavior. The equations include the link state probability, network flows, link arrival rates, adaptive trunk reservation level, and adaptive path selection depth. The link state model provides the aggregate link state probabilities through solution of the birth-death equations, and models the adaptive nature of trunk reservation. The network flow model provides a method to calculate the traffic flow using the least busy concept employed in RTNR, and also models the adaptive nature of the path selection depth. The analytical model addresses asymmetrical networks, and computational examples show the differences from the simulation model to be small. The authors also use the analytical model to examine key RTNR parameters over a range of values