The Effect of Ionic Contaminants on Silicon Transistor Stability

The development of the beam-lead sealed-junction (BLSJ) technology (beam-lead contact metals-silicon nitride passivation) included many experiments to study the effects of various ionic contaminants on silicon transistor stability. Stress aging was performed on standard n-p-n silicon transistors (aluminum contacts and silicon dioxide protection) under various conditions of temperature, bias, contamination, and ambient. These experiments showed the following results. 1) Alkali ions and copper in a reducing ambient are detrimental to the devices. 2) A hydrogen ambient accelerates the effect of alkali ions on the transistor degradation. 3) The degradation is approximately a linear function of the reverse bias and the contamination level from 4 to 400 ? of sodium chloride. 4) Anions have only a secondary effect on the migration of alkali ions in the oxide. The BLSJ technology was developed to protect unencapsulated silicon devices from the degradation seen on standard transistors during the preceding experiments. Results have shown that the median time to failure of sodium-contaminated BLSJ transistors aged in air at 300°C is higher than that for standard silicon transistors aged under identical conditions.     

Stable gallium arsenide MIS capacitors and MIS field effecttransistors by (NH4)2Sx treatment andhydrogenation using plasma deposited silicon nitride gate insulator

The beneficial effects of sulfur passivation of gallium arsenide (GaAs) surface by (NH₄)₂S_x chemical treatment and by hydrogenation of the insulator-GaAs interface using the plasma-enhanced chemical vapor-deposited (PECVD) silicon nitride gate dielectric film as the source of hydrogen are illustrated by fabricating Al/PECVD silicon nitride/n-GaAs MIS capacitors and metal insulator semiconductor field effect transistors (MISFET). Post metallization annealing (PMA) at temperatures in the range 450-550°C is shown to be the key process for achieving midgap interface state density below 10 ¹¹/cm²/eV and maximum incremental transconductance, which is about 75% of the theoretical maximum limit. MIS capacitors are fabricated on (NH₄)₂S_x treated GaAs substrate using gate dielectrics such as PECVD SiO ₂ and silicon oxynitride to demonstrate that the PMA is less effective with these dielectrics because of their lower hydrogen content. The small signal AC transconductance, g_ms measurements on MISFETs fabricated using silicon nitride, have shown that the low-frequency degradation of g_ms is almost absent in the devices fabricated on (NH₄)₂S_x-treated GaAs substrates and subjected to PMA. The drain current stability in these devices is demonstrated to be excellent, with an initial drift of only 2% of the starting value. The dual role of silicon nitride layer, namely, protection against loss of sulfur and an excellent source of hydrogen for additional surface passivation along with sulfur is demonstrated by comparing the transconductance of MISFETs fabricated on GaAs substrates annealed without the nitride cap after the (NH₄)₂S _x treatment     

GaAs metal insulator field effect transistors with excellentintrinsic transconductance and stable drain currents using (NH4)2Sx chemical treatment

Metal insulator semiconductor field effect transistors (MISFETs) and MIS capacitors are fabricated using Al metal-gate and PECVD silicon nitride (Si₃N₄) gate-insulator on commercial GaAs epitaxial wafers after treating the channel regions with (NH₄)₂S_x. It is shown that the post metallization annealing (PMA) of these devices improves the transconductance and reduces the interface state density (D_it) considerably. This is attributed to the additional passivation effect of hydrogen diffusing to the interface from the Si ₃N₄ during the PMA. An intrinsic transconductance of 30.7 mS/mm which is 75% of the theoretical maximum limit of 40.5 mS/mm has been achieved using silicon nitride gate insulator thickness of 1100 Å. Stability of the drain currents in these devices is demonstrated to be excellent     

Medium power high-speed germanium alloy transistors

A complementary pair of medium-power high-speed switching transistors was required to satisfy the needs of an electronic switching system. Units have been designed and produced which exhibit a median cutoff frequency of 7 mc and a punch-through voltage of 70 volts. High yields have been achieved on established production lines by very close manufacturing controls of the critical alloying variables, namely, germanium wafer thickness, alloyed junction area, concentricity, mass of alloying material, alloying temperature, and special material properties such as orientation and etch-pit density. A vacuum-tight transistor structure has been designed to permit the dissipation of one-half watt of power at 25°C in free air. The structure embodies an all-copper cold-welded encapsulation for efficient heat removal. Important techniques concerning the cold-welding process will be discussed, and the particular die contour used will be illustrated in some detail. Additional cleanliness advantages are obtained by use of the cold welded seal.     

Heterostructure devices using self-aligned p-type diffused ohmiccontacts

Describes the use of a p-type refractory ohmic contact in ohmic self-aligned devices. The contacts are based on self-aligned diffusion of zinc-doped tungsten film. The diffusion is nearly isotropic in the vicinity of silicon nitride sidewalls, allowing self-alignment of ohmic contacts with emitters and gates. Low-resistance contacts (<10^-6 Ω·cm²) are formed both to GaAs and GaAlAs, and the lifetime of the diffused region is superior to that obtained from implantation. Heterostructure bipolar transistors (HBTs) showing high current gains (⩾50 at 2×10³ A·cm^-2 and ⩾200 at 1×10⁵ A·cm^-2 with micrometer-sized emitter widths) and p-channel GaAs gate heterostructure field-effect transistors (HFETs) showing high transconductances (78 mS/mm at 2.2-μm gate length) have been fabricated using this contact     

High efficiency inversion layer solar cells on polycrystalline silicon by the application of silicon nitride

Plasma enhanced CVD silicon nitride is introduced for the fabrication of inversion layer solar cells on p-type polycrystalline silicon. The same high interface quality as obtained for Si-nitride on monocrystalline silicon could also be achieved for polycrystalline silicon. This includes high interface charge densities up to 6.6 × 10¹²cm^-2and high UV sensitivity of the cells. For 4-cm²polycrystalline metal-insulator-semiconductor inversion layer (MIS/IL) solar cells active area efficiencies up to 13.4 percent (12.3-percent total area efficiency) under AM1 illumination could be reached, the highest values yet reported for polycrystalline silicon inversion layer solar cells on a total area basis. For the coprocessed MIS/IL cells on monocrystalline 0.7-ω. cm p-Si     

Amorphous-silicon thin-film transistor with liquid phase depositionof silicon dioxide gate insulator

The liquid phase deposition of silicon dioxide (LPD-SiO₂) at 50°C has been successfully applied as the gate insulator for inverted, staggered amorphous silicon thin-film transistors (TFTs). The maximum field-effect mobility of the TFTs, estimated from the saturation region, was 0.53 cm²/V-s, comparable to that obtained for conventional, silicon nitride (SiN_x ) gate transistors. The threshold voltage and subthreshold swing were 6.2 V and 0.76 V/decade, respectively. Interface and bulk characteristics are as good as those obtained for silicon nitride (SiN _x) films deposited by plasma enhanced chemical vapor deposition     

Thermal nitridation of Si and SiO2for VLSI

This paper presents an extensive review of our work on thermal nitridation of Si and SiO2. High-quality ultrathin films of silicon nitride and nitrided-oxide (nitroxide) have been thermally grown in ammonia atmosphere in a cold-wall RF-heated reactor and in a lamp-heated system. The growth kinetics and their dependence on processing time and temperature have been studied from very short to long nitridation times. The kinetics of thermal nitridation of SiO2in ammonia ambient have also been studied. In nitroxide, nitrogen-rich layers are formed at the surface and interface at a very early stage of the nitridation. Then the nitridation reaction mainly goes on in the bulk region with the surface and near interface nitrogen content remaining fairly constant. Our results also indicate the formation of an oxygen-rich layer at the interface underneath the nitrogen-rich layer whose thickness increases slowly with nitridation time. The nitride and nitroxide films were analyzed using Auger electron spectroscopy, grazing angle Rutherford backscattering, and etch rate measurements. MIS devices were fabricated using these films as gate insulators and were electrically characterized usingI - V, C - V, time-dependent breakdown, trapping, and dielectric breakdown techniques. Breakdown, conduction, andC-Vmeasurements on metal-insulator semiconductor (MIS) structures fabricated with these films show that very thin thermal silicon nitride and nitroxide films can be used as gate dielectrics for future highly scaled-down VLSI devices. The electrical characterization results also indicate extremely low trapping in the nitride films. The reliability of ultrathin nitride was observed to be far superior to SiO2and nitroxide due to its much less trapping. Studies show that the interface transition from nitride to silicon is almost abrupt and the morphology and roughness of the interface are comparable to the SiO2-Si interfaces.     

Recent progress in MIS solar cells

Metal–insulator–semiconductor (MIS)-type solar cells have an inherent cost advantage compared to p-n junction solar cells. First-generation MIS–inversion layer (MIS–IL) solar cells, already successfully produced in an industrial pilot line, are restricted to efficiencies of 15–16%. With the second-generation MIS–IL silicon solar cells, based on drastically improved surface passivation by plasma-enhanced chemical vapour-deposited silicon nitride, simple technology can be combined with very high efficiencies. The novel inversion layer emitters have the potential to outperform conventional phosphorus-diffused emitters of Si solar cells. A 17.1% efficiency could already be achieved with the novel point-contacted ‘truncated pyramid’ MIS–IL cell. A new surface-grooved line-contact MIS–IL device presently under development using unconventional processing steps applicable for large-scale fabrication is discussed. By the mechanical grooving technique, contact widths down to 2 μm can be achieved homogeneously over large wafer areas. Bifacial sensitivity is included in most of the MIS-type solar cells. For a bifacial 98 cm² Czochralski (Cz) Si MIS-contacted p-n junction solar cell with a random pyramid surface texture and Al as grid metal, efficiencies of 16.5% for front and 13.8% for rear side illumination are reported. A 19.5% efficiency has been obtained with a mechanically grooved MIS n⁺p solar cell. The MIS-type silicon solar cells are able to significantly lower the costs for solar electricity due to the simple technology and the potential for efficiencies well above 20%.©1997 John Wiley & Sons, Ltd.     

Current gain recovery in silicon nitride passivated planar transistors by hydrogen implantation

During deposition of silicon nitride, the low-current hFEof silicon planar transistors decreases. When the nitride layer completely seals the oxide from the ambient, the initial value of hFEcannot be restored by annealing at 500°C in forming gas. To eliminate this difficulty, hydrogen ions have been implanted at an energy of 70 keV and at doses varying from 1.10¹³to 1.10¹⁶cm^-2through the nitride into the oxide. Optimum hFErecovery has been obtained with implantation at a dose of 3.10¹⁵cm^-2followed by a radiation damage annealing at 400-500°C in dry nitrogen.     

Dual-metal gate CMOS technology with ultrathin silicon nitride gatedielectric

We report the first demonstration of a dual-metal gate complementary metal oxide semiconductor (CMOS) technology using titanium (Ti) and molybdenum (Mo) as the gate electrodes for the N-metal oxide semiconductor field effect transistors (N-MOSFETs) and P-metal oxide semiconductor field effect transistors (P-MOSFETs), respectively. The gate dielectric stack consists of a silicon oxy-nitride interfacial layer and a silicon nitride (Si₃N₄) dielectric layer formed by a rapid-thermal chemical vapor deposition (RTCVD) process. C-V characteristics show negligible gate depletion. Carrier mobilities comparable to that predicted by the universal mobility model for silicon dioxide (SiO₂) are observed     

Emitter and base transit time of polycrystalline silicon emittercontact bipolar transistors

The author formulates transit time in the neutral emitter region, τ_E, and in the neutral base region τ_B, of polycrystalline silicon emitter contact bipolar transistors. An analytical theory derived for τ_E of polysilicon emitter contact bipolar transistors and its dependence on the emitter junction depth, the polysilicon thickness, and the base width are presented. The influence of bandgap narrowing on τ_E and τ_B is analyzed. Bandgap narrowing increases τ_E , but τ_B is insensitive to it. τ_E is proportional to base width W_B and τ_B to W²_B. τ_E is not negligible compared to τ_B when W_B is less than 100 nm. Reducing emitter junction depth and polysilicon thickness is indispensable to developing shallow base bipolar transistors     

A lateral metal—insulator—p-Si tunnel transistor

We report the fabrication of a lateral MIS tunnel transistor whose emitter and collector are Al/SiO2/p-Si tunnel junctions. All processing is carried out at room temperature except for the growth of the passivating field oxide. The small signal common emitter current gain is 20. Two coupled gain mechanisms exist for such a lateral MIS tunnel transistor. The first mechanism relies on a high minority-carrier injection ratio of the emitter junction. Second, the minority carriers injected into the reverse-biased collector junction may produce additional gain through multiplication of majority-carrier current. Lateral MIS tunnel transistors on n-Si make use of the second mechanism. Our device takes advantage of the high minority-carrier injection ratio achievable with Al/SiO2/p-Si tunnel junctions.     

Silicon nitride thin-film deposition by LPCVD with in situ HF vaporcleaning and its application to stacked DRAM capacitor fabrication

Silicon nitride film deposited by LPCVD with newly developed in situ HF vapor cleaning has been studied and applied to fabricate dielectric films for stacked DRAM capacitors. Using this method, an oxide-free surface of underlaid poly-Si can be obtained. Silicon nitride film deposited on this surface has been verified by FTIR measurement to have the stoichiometrically proper composition of Si₃N₄ . However, the film was found to be selectively deposited on poly-Si electrodes. This selective deposition degrades the reliability of the stacked capacitor, because the silicon nitride can not completely cover the periphery of poly-Si electrodes on SiO₂. We propose a simple process that avoids the problem making it possible to apply silicon nitride film to stacked-capacitor fabrication. Stacked capacitors fabricated by this process exhibit very low leakage current and high electrical reliability even for ultra-thin silicon nitride films less than 5 nm thick     

Amorphous silicon buried-channel thin-film transistors

We demonstrate a buried-channel thin-film field effect transistor (TFT) based on deposited silicon nitride and hydrogenated amorphous silicon with the conducting channel recessed approximately 50 Å from the interface. We fabricate transistors and capacitors by DC reactive magnetron sputtering of a silicon target in a plasma of (Ar+H ₂+N₂) or (Ar+H₂) for the nitride and silicon layers, respectively. To create a step in the conduction band, and thus a buried-channel, we vary the hydrogen partial pressure which varies the hydrogen content and the bandgap of amorphous silicon. Capacitance-voltage and current-voltage measurements on these devices present strong evidence for the existence of the buried-channel. We achieve a record field effect mobility in saturation of 1.68 cm² /V-s with amorphous silicon deposited at 230°C, and an acceptable mobility of 0.44 cm²/V-s with amorphous silicon deposited at 125°C     

Fabrication and characterization of high performance AlGaN/GaN HEMTs on sapphire with silicon nitride passivation

AlGaN/GaN high electron mobility transistors(HEMTs)with high performance were fabricated and characterized.A variety of techniques were used to improve device performance,such as AlN interlayer,silicon nitride passivation,high aspect ratio T-shaped gate,low resistance ohmic contact and short drain-source distance. DC and RF performances of as-fabricated HEMTs were characterized by utilizing a semiconductor characterization system and a vector network analyzer,respectively.As-fabricated devices exhibited a maximum drain current density of 1.41 A/mm and a maximum peak extrinsic transconductance of 317 mS/mm.The obtained current density is larger than those reported in the literature to date,implemented with a domestic wafer and processes.Furthermore, a unity current gain cut-off frequency of 74.3 GHz and a maximum oscillation frequency of 112.4 GHz were obtained on a device with an 80 nm gate length.     

Low-temperature gate dielectrics formed by plasma anodisation ofsilicon nitride

Silicon nitrides, deposited on silicon by PECVD using an SiH₄ /NH₃ plasma at 300°C, were anodised in an oxygen plasma at 500°C. The resulting dielectric appears to have lower fixed charge, leakage current and interface trap density than the original PECVD nitride, and to have the potential of use as a gate dielectric for MIS devices in VLSI circuits     

Insulator investigation on SiC for improved reliability

Significant improved high-temperature reliability of SiC metal-insulator-semiconductor (MIS) devices has been achieved with both thermally grown oxides and by using a stacked dielectric consisting of silicon oxide-nitride-oxide (ONO). Capacitors of p-type 6H-SiC, n-type 6H-SiC and n-type 4H-SiC were fabricated with a variety of insulators. The best performance was accomplished only with insulators incorporating silicon dioxide. A new thermal oxidation process of growing a dry oxide then following with a wet re-oxidation anneal produces an oxide with the dielectric strength of a dry oxide and the high-quality interface of a wet oxide. MIS field effect transistors (MISFETs) with an ONO gate insulator had surface channel mobilities similar to MISFETs with thermal gate oxides, and demonstrated a lifetime of 10 days at 335°C and 15 V bias. The lifetime of the ONO MISFET was a factor of 100 higher than for devices fabricated with deposited oxides, which had been the prior state of the art for high-temperature MISFETs on SiC     

Reliability of MINP compared to MIS, SIS, and N/P silicon solar cells under 1.0-MeV electron and environmental effects

The effects of 1.0-MeV electron radiation are compared for MIS, SIS, N/P, and MINP silicon solar cells. MIS, SIS, and N/P silicon solar cells are comparable in performance except that SIS cells degraded faster due to use of n-type Si substrates. MINP cells exhibited superior performance in that efficiency degraded 9 percent at a fluence of 1 × 10¹⁵e^-/cm²and 32 percent at a fluence of 1 × 10¹⁶e^-/cm²compared to 29 percent and 49 percent, respectively, for N/P cells. MINP cells utilize an SiO2insulator layer over a thin N-region, and a low work function metal contact. This design gives a high ultraviolet response and low surface recombination velocity which maintains high efficiency since most of the radiation loss occurs in the infrared region due to bulk damage effects.     

Analyses for stoichiometry and for Hydrogen and Oxygen in silicon nitride films

Optical, ion, and electron probe techniques can be effectively applied to analyze for H, O, and the Si/N ratio in thin films of silicon nitride. The films studied were formed by chemical-vapor deposition or plasma deposition for application as a gate dielectric in semiconductor memory devices and for circuit encapsulation. The H concentration is measured by the multiple internal reflection technique which detects NH and SiH vibrational modes. A decrease in SiH bonding with an increase in deposition temperature is shown for chemical-vapor-deposited silicon nitride, and a very high concentration of SiH bonds is observed in plasma-deposited silicon nitride. Ion back-scattering analysis is a direct method for measuring the Si/N ratio and a related nuclear reaction analysis technique is a direct method for measuring and profiling the O content. Backscattering analysis shows a significantly larger Si/N ratio for plasma than for chemical-vapor-deposited silicon nitride. The O profile obtained by reaction analysis for a nitride/oxide/Si structure is compared to that obtained by sputter Auger electron spectroscopy, and the results show that O concentrations down to ∼0.5 at % can be measured by either technique. Auger analysis gives better depth resolution than reaction analysis but it requires a calibration standard. Auger results also show N penetration of interfacial SiO2and accumulation of N at the Si-SiO2interface.