Flip chip attachment on flexible LCP substrate using an ACF

In this study the reliability of a flip chip bonding process using anisotropic conductive adhesives (ACA) was evaluated. The flexible substrates used were made of liquid crystal polymer (LCP), which is an interesting new material having excellent properties for flexible printed circuit boards. The test samples were prepared using two different anisotropic conductive films (ACF) having the same fast-cure resin matrix, but different conductive particles. The reliability of the test samples was studied by accelerated environmental tests. In the constant humidity test the temperature was 85 °C and the relative humidity was 85%. The temperature cycling test was carried out between temperatures of −40 °C and 85 °C. To determine the exact time of a failure the resistance of each test sample was measured using continuous real-time measurement. A clear difference between the behaviour of the conductive particles was seen in the test. While the adhesive having polymer particles had only one failure during testing, the adhesive having nickel particles had a considerable number of failures in both tests. Cross sections of the samples were made to analyze the failure mechanisms.     

Comparison of different flex materials in high density flip chip on flex applications

This paper presents the results from the evaluation of different types of flexible substrates for high-density flip chip application. In this work four different flexible substrates were used. The flex substrates were Espanex, Upilex and epoxy glass with 80 μm pitch and Upilex with 54 μm pitch. Two different test IC’s were used for both pitches. In test IC1 (80 μm pitch) and IC3 (54 μm pitch) the bumps were in one row and test IC2 (80 μm pitch) and IC4 (54 μm pitch) in two rows. The total amount of contacts in test IC1 was 190, in test IC2 173, in test IC3 293 and in test IC4 270. The anisotropically conductive adhesive that was used in the tests was epoxy based thermosetting adhesive film with conductive particles. The conductive particles in the adhesives were isolated soft metal-coated polymer particles. The contact resistance was measured using Kelvin four-point method and the continuity and series resistance using daisy chain structure. The reliability of the flip chip interconnections was tested in temperature cycling test and environmental test. Cross section samples were made to analyse the possible reason for failures. The results presented in this paper are from FLEXIL development project that is part of European Union IST research program.     

Effect of microwave preheating on the bonding performance of flip chip on flex joint

A microwave (MW) preheating mechanism of anisotropic conductive adhesive film (ACF) has been introduced in order to reduce the bonding temperature for flip chip technology. Thermal curing of epoxy shows a very sluggish and non-uniform curing kinetics at the beginning of the curing reaction, but the rate increases with time and hence requires higher temperature. On the other hand MW radiation has the advantage of uniform heating rate during the cycle. In view of this, MW preheating (for 2/3 s) of ACF prior to final bonding has been applied to examine the electrical and mechanical performance of the bond. Low MW power has been used (80 and 240 W) to study the effect of the MW preheating. It has been found that 170 °C can be used for flip chip bonding instead of 180 °C (standard temperature for flip chip bonding) for MW preheating time and power used in this study. The contact resistance (0.015–0.025 Ω) is low in these samples where the standard resistance is 0.017 Ω (bonded at 180 °C without prior MW preheating). The shear forces at breakage were satisfactory (152–176 N) for the samples bonded at 170 °C with MW preheating, which is very close and even higher than the standard sample (173.3 N). For MW preheating time of 2 s, final bonding at 160 °C can also be used because of its low contact resistance (0.022–0.032 Ω), but the bond strength (137.3–145 N) is somewhat inferior to the standard one.     

Anisotropic conductive film flip chip joining using thin chips

In this study, flip chip interconnections were made on very flexible polyethylene naphthalate substrates using anisotropic conductive film. Two kinds of chips were used: chips of normal thickness and thin chips. The thin chips were very thin, only 50 μm thick. Due to the thinness of the chips they were flexible and the entire joint was bendable. The reliability properties of the interconnections established with these two different kinds of chips were compared. In addition, the effect of bending of the chip and joint area on the joint reliability was studied. Furthermore, part of the substrates was dried before bonding and the effect of that on the joint performance was investigated.The pitch of the test vehicles was 250 μm and the chips had 25 μm high gold bumps. For resistance analysis there were two four-point measuring positions in each test vehicle. For finding the optimal bonding conditions for the test vehicles, the bonding was done using two different bonding pressures, of which the better one was chosen for the final tests.Furthermore, the test vehicles were subjected to thermal cycling tests between −40 and +125 °C (half-an-hour cycle) and to a humidity test (85%/85 °C). Part of the test vehicles were bent during the tests. Finally, the structures of the joints were studied using scanning electron microscopy.     

Effects of bonding temperature on the properties and reliabilities of anisotropic conductive films (ACFs) for flip chip on organic substrate application

The effects of bonding temperatures on the composite properties and reliability performances of anisotropic conductive films (ACFs) for flip chip on organic substrates assemblies were studied. As the bonding temperature decreased, the composite properties of ACF, such as water absorption, glass transition temperature (T_g), elastic modulus (E′) and coefficient of thermal expansion (α), were improved. These results were due to the difference in network structures of cured ACFs which were fully cured at different temperatures. From small angle X-ray scattering (SAXS) test result, ACFs cured at lower temperature, had denser network structures. The reliability performances of flip chip on organic substrate assemblies using ACFs were also investigated as a function of bonding temperatures. The results in thermal cycling test (−55 °C/+150 °C, 1000 cycles) and PCT (121 °C, 100% RH, 96 h) showed that the lower bonding temperature resulted in better reliability of the flip chip interconnects using ACFs. Therefore, the composite properties of cured ACF and reliability of flip chip on organic substrate assemblies using ACFs were strongly affected by the bonding temperature.     

Effects of different bonding parameters on the electrical performance and peeling strengths of ACF interconnection

The effects of different bonding parameters, such as temperature, pressure, curing time, bonding temperature ramp and post-processing, on the electrical performance and the adhesive strengths of anisotropic conductive film (ACF) interconnection are investigated. The test results show that the contact resistances change slightly, but the adhesive strengths increase with the bonding temperature increased. The curing time has great influence on the adhesive strength of ACF joints. The contact resistance and adhesive strength both are improved with the bonding pressure increased, but the adhesive strengths decrease if the bonding pressure is over 0.25 MPa. The optimum temperature, pressure, and curing time ranges for ACF bonding are concluded to be at 180–200 °C, 0.15–0.2 MPa, and 18–25 s, respectively. The effects of different Teflon thickness and post-processing on the contact resistance and adhesive strength of anisotropic conductive film (ACF) joints are studied. It is shown that the contact resistance and the adhesive strength both become deteriorated with the Teflon thickness increased. The tests of different post-processing conditions show that the specimens kept in 120 °C chamber for 30 min present the best performance of the ACF joints. The thermal cycling (−40 to 125 °C) and the high temperature/humidity (85 °C, 85% RH) aging test are conducted to evaluate the reliability of the specimens with different bonding parameters. It is shown that the high temperature/humidity is the worst condition to the ACF interconnection.     

Long time reliability study of soldered flip chips on flexible substrates

Due to the requirements of new light, mobile, small and multifunctional electronic products the density of electronic packages continues to increase. Especially in medical electronics like pace makers the minimisation of the whole product size is an important factor. So flip chip technology becomes more and more attractive to reduce the height of an electronic package. At the same time the use of flexible and foldable substrates offers the possibility to create complex electronic devices with a very high density. In terms of human health the reliability of electronic products in medical applications has top priority.In this work flip chip interconnections to a flexible substrate are studied with regard to long time reliability. Test chips and substrates have been designed to give the possibility for electrical measurements. Solder was applied using conventional stencil printing method. The flip chip contacts on flexible substrates were created in a reflow process and underfilled subsequently.The assemblies have been tested according to JEDEC level 3. The focus in this paper is the long time reliability up to 10,000 h in thermal ageing at 125 °C and temperature/humidity testing at 85 °C/85% relative humidity as well as thermal cycling (0 °C/+100 °C) up to 5000 cycles. Daisy chain and four point Kelvin resistances have been measured to characterise the interconnections and monitor degradation effects.The failures have been analysed in terms of metallurgical investigations of formation and growing of intermetallic phases between underbump metallisation, solder bumps and conductor lines. CSAM was used to detect delaminations at the interfaces underfiller/chip and underfiller/substrate respectively.     

Chip on paper technology utilizing anisotropically conductive adhesive for smart label applications

Smart labels are a new generation of low cost transponders consisting of a transponder chip and a flexible type of antenna. Applying a flip chip assembly technology yields a new generation of low cost radio frequency identification (RFID) system that is a paper-thin smart label. Anisotropically conductive adhesive (ACA) is utilized to attach a flip chip onto a paper substrate to form the BiStatix RFID tag. Unlike bar codes, which are passive tags, smart labels can dynamically transmit and receive information to help identify, track and route packages remotely. The concept of flipping or inverting a silicon chip to be mounted on a paper substrate offers distinct advantages and enables achieving the cost and performance goals of this new product technology.Significant process development and reliability assessment was required to develop this smart label application. This paper discusses the process development and reliability assessment that was completed to achieve a low cost flip chip on paper assembly process. The various characteristics of ACA made it an enabling technology for this smart label application. A bare (unbumped) flip chip––without a dielectric layer and conductive polymer bumps––was aligned and placed on the paper substrate with compressive force. A thin layer of anisotropically conductive adhesive was used to attach the IC chip to the conductive ink antenna on the paper substrate. The conductive adhesive underfills and cures in only seconds. Advantages of this environmentally preferred process include the elimination of additional curing processes and reduced equipment requirements as well as the reduction of total IC packaging thickness.     

Effect of Gold Stud Bump Topology on Reliability of Flip Chip on Flex Interconnects

The flip chip technique using conductive adhesives have emerged as a good alternative to solder flip chip methods. Different approaches of the interconnection mechanism using conductive adhesives have been developed. In this paper, test chips with gold stud bumps are flip-chipped with conductive adhesives onto a flexible substrate. An experimental study to characterize the bonding process parameters is reported. Initial results from the environmental studies show that thermal shock test causes negligible failure. On the other hand, high humidity test causes considerable failure in flip chip on flex assemblies. Improvements in the reliability of the assembly are achieved by modifying the shape of the gold stud bumps.     

Plasma cleaning of the flex substrate for flip-chip bonding with anisotropic conductive adhesive film

Advanced integrated circuit packaging processes require good bondability and reliability between various mating surfaces. A key factor affecting this requirement is surface cleanliness. Plasma cleaning is the most suitable process for optimum surface cleanliness. An investigation of O₂, Ar, and O₂/SF₆ plasma cleaning was carried out on a flexible substrate to study the adhesion of anisotropic conductive adhesive film for flip chip bonding. Surface roughness was found to increase substantially after the plasma treatment. Adhesion strength was evaluated by 90° peeling tests both for untreated and plasma-treated flex. A higher adhesion strength of anisotropic conductive film (ACF) bond was observed after plasma cleaning. The surface morphology of plasma treated and untreated flex substrate before bonding, as well as the fracture surfaces after the peel test for both cases, was characterized by secondary electron image techniques of scanning electron microscopy (SEM). Based on the detailed SEM findings, extensive comparisons were made between the plasma treated and the untreated samples. Mechanical interlocking is found to be responsible for higher peel strength of the plasma treated flex bonding. It was also proposed to select the right flexible substrate for highly reliable, ACF bonded flip chip on flex substrate.     

Interconnect resistance characteristics of several flip-chip bumping and assembly techniques

Several flip-chip interconnection methods were compared by measuring interconnect resistance before and after exposure to environments including pre-conditioning, 85°C/85% RH exposure, 150°C storage, and 0–100°C temperature cycling. The goal was to determine an acceptable low-cost, reliable method for bumping and assembling chips to flexible or rigid substrates using flip-chip assembly techniques. Alternative flip-chip bumping methods are compared to a traditional wafer solder bumping method. Flip-chip interconnection methods evaluated included high lead content solder, silver filled conductive adhesive, and gold stud bumps. Under bump metallurgies evaluated included bare aluminum, evaporated Cr/Cr–Cu/Cu, and electroless nickel plating.     

Reliability study of underfill/chip interface under accelerated temperature cycling (ATC) loading

Interface reliability issue has become a major concern in developing flip chip assembly. The CTE mismatch between different material layers may induce severe interface delamination reliability problem. In this study, multifunctional micro-moiré interferometry (M³I) system was utilized to study the interfacial response of flip chip assembly under accelerated thermal cycling (ATC) in the temperature range of −40 °C to 125 °C. This in-situ measurement provided good interpretation of interfacial behavior of delaminated flip chip assembly. Finite element analysis (FEA) was carried out by introducing viscoelastic properties of underfill material. The simulation results were found to be in good agreement with the experimental results. Interfacial fracture mechanics was used to quantify interfacial fracture toughness and mode mixity of the underfill/chip interface under the ATC loading. It was found that the interfacial toughness is not only relative to CTE mismatch but also a function of stiffness mismatch between chip/underfill.     

Qualification approaches and thermal cycle test results for CSP/BGA/FCBGA

Qualification of newly developed multifunctional electronic packages, e.g. system in a package (SIP), are becoming complex at the package level and even more at the assembly and system levels. After many years of data collection, just recently industry agreed to release an industry-wide specification for single die area array package assembly qualification.Probability risk assessment, being implemented by NASA for space flight missions, may be narrowed at the element level for advanced electronic systems and SIP, and further narrowed at the electronic subsystem level. This paper will review the key elements of an industry-wide specification recently published by the IPC (association connecting electronics industries). It will report on a few other unique qualification approaches that are currently being either implemented or developed for risk reduction in high reliability applications. Risk level assessment based 2-P, 3-P, and LogNormal distributions will be compared for plastic ball grid array (PBGA) and flip chip BGA (FCBGA). For this case, risks are compared using cycles-to-failures (CTFs) test results for temperature ranges of −30 to 100 °C and 0 to 100 °C (two profiles).In addition, CTFs up to 1,500 cycles in the range of −55 to 125 °C for a 784 I/O FCBGA (flip chip BGA, a 175 I/O FPBGA (fine pitch BGA)), and a 313 I/O PBGA (plastic BGA) are compared. Inspection results along with scanning electron microscopy and optical cross-sectional photos revealing damage and failure mechanisms are also included.     

Role of bonding time and temperature on the physical properties of coupled anisotropic conductive-nonconductive adhesive film for flip chip on glass technology

Using thermosetting epoxy based conductive adhesive films for the flip chip interconnect possess a great deal of attractions to the electronics manufacturing industries due to the ever increasing demands for miniaturized electronic products. Adhesive manufacturers have taken many attempts over the last decade to produce a number of types of adhesives and the coupled anisotropic conductive-nonconductive adhesive film is one of them. The successful formation of the flip chip interconnection using this particular type of adhesive depends on, among factors, how the physical properties of the adhesive changes during the bonding process. Experimental measurements of the temperature in the adhesive have revealed that the temperature becomes very close to the required maximum bonding temperature within the first 1 s of the bonding time. The higher the bonding temperature the faster the ramp up of temperature is. A dynamic mechanical analysis (DMA) has been carried out to investigate the nature of the changes of the physical properties of the coupled anisotropic conductive-nonconductive adhesive film for a range of bonding parameters. Adhesive samples that are pre-cured at 170, 190 and 210 °C for 3, 5 and 10 s have been analyzed using a DMA instrument. The results have revealed that the glass transition temperature of this type of adhesive increases with the increase in the bonding time for the bonding temperatures that have been used in this work. For the curing time of 3 and 5 s, the maximum glass transition temperature increases with the increase in the bonding temperature, but for the curing time of 10 s the maximum glass transition temperature has been observed in the sample which is cured at 190 °C. Based on these results it has been concluded that the optimal bonding temperature and time for this kind of adhesive are 190 °C and 10 s, respectively.     

Studies on various chip-on-film (COF) packages using ultra fine pitch two-metal layer flexible printed circuits (two-metal layer FPCs)

Various fine pitch chip-on-film (COF) packages assembled by (1) anisotropic conductive film (ACF), (2) nonconductive film (NCF), and (3) AuSn metallurgical bonding methods using fine pitch flexible printed circuits (FPCs) with two-metal layers were investigated in terms of electrical characteristics, flip chip joint properties, peel adhesion strength, heat dissipation capability, and reliability. Two-metal layer FPCs and display driver IC (DDI) chips with 35 μm, 25 μm, and 20 μm pitch were prepared. All the COF packages using two-metal layer FPCs assembled by three bonding methods showed stable flip chip joint shapes, stable bump contact resistances below 5 mΩ, good adhesion strength of more than 600 gf/cm, and enhanced heat dissipation capability compared to a conventional COF package using one-metal layer FPCs. A high temperature/humidity test (85 °C/85% RH, 1000 h) and thermal cycling test (T/C test, ?40 °C to + 125 °C, 1000 cycles) were conducted to verify the reliability of the various COF packages using two-metal layer FPCs. All the COF packages showed excellent high temperature/humidity and T/C reliability, however, electrically shorted joints were observed during reliability tests only at the ACF joints with 20 μm pitch. Therefore, for less than 20 μm pitch COF packages, NCF adhesive bonding and AuSn metallurgical bonding methods are recommended, while all the ACF and NCF adhesives bonding and AuSn metallurgical bonding methods can be applied for over 25 μm pitch COF applications. Furthermore, we were also able to demonstrate double-side COF using two-metal layer FPCs.     

Board level reliability assessment of chip scale packages

A large program had been initiated to study the board level reliability of various types of chip scale package (CSP). The results on six different packages are reported here, which cover flex interposer CSP, rigid interposer CSP, wafer level assembly CSP, and lead frame CSP. The packages were assembled on FR4 PCBs of two different thicknesses. Temperature cycling tests from −40°C to +125°C with 15 min dwell time at the extremes were conducted to failure for all the package types. The failure criteria were established based on the pattern of electrical resistance change. The cycles to failure were analyzed using Weibull distribution function for each type of package. Selected packages were tested in the temperature/humidity chamber under 85°C/85%RH for 1000 h. Some assembled packages were tested in vibration condition as well. In all these tests, the electrical resistance of each package under testing was monitored continuously. Test samples were also cross-sectioned and analyzed under a Scanning Electronic Microscope (SEM). Different failure mechanisms were identified for various packages. It was noted that some packages failed at the solder joints while others failed inside the package, which was packaging design and process related.     

Particle on Bump (POB) technique for ultra-fine pitch chip on glass (COG) applications by conductive particles and adhesives

Chip on glass (COG) technology is widely used in liquid crystal display (LCD) modules for connecting driver ICs to the displays especially for middle and small size panels. The most common COG technology currently used in display applications is based on anisotropic conductive films (ACF). As the increasing demand in higher resolution and cost reduction, the bump pitch of the driver ICs becomes finer and finer. With the reduction of bump pitch, the current ACF based COG technology is confronted with two issues: one is the increase of the chances of open circuit; the other is the increase of the chances of forming shorts. A new approach for ultra-fine pitch chip on glass (COG) bonding, named ”Particle on Bump (POB)”, is proposed in this paper. In this technique, conductive particles are planted on the top surface of bumps of a driver IC through Au–Sn intermetallic connection. The driver IC is then assembled on the glass substrate of a LCD panel with an insulated adhesive by thermal press. The new method ensures that electrical connections are established only between bumps and corresponding pads. The Au–Sn reflow process for particle planting and corresponding COG bonding process were investigated in detail. The results showed that reliable connections were formed between particles and bumps through an Au–Sn intermetallic layer and final COG interconnections thus formed performed well in reliability tests. It is concluded that the POB technique overcomes the shortcomings of current ACF technique and has good potential to provide a viable ultra-fine pitch flip chip on glass solution for display applications.     

Study of adhesive flip chip bonding process and failure mechanisms of ACA joints

The flip chip bonding process using anisotropic conductive adhesives (ACA) and the consequent joint reliability were studied. The substrates used were rigid FR-4 boards, which are interesting due to their low cost and wide range of applications. The problems associated with the technique are discussed in this paper from the reliability point of view. Also, some aspects concerning production are introduced.The reliability of the joints was studied by accelerated environmental tests. A temperature cycling test was performed between temperatures −40 and +125 °C. Constant humidity testing was conducted at 85 °C and RH85%. In addition, reflow aging tests were performed using a conventional Sn/Pb reflow profile. For reducing the bonding cycle time, a two-stage curing process was used, which also utilizes the reflow process.The results show that the three bonding parameters, temperature, time, and pressure, all affect joint reliability. Most detrimental, however, seems to be reflow treatment performed after bonding. Most failures occurred only very briefly during the temperature cycling at the moment the temperature changed, while the joints were still conducting at both temperature extremes. However, a different failure mechanism caused a different kind of behavior during temperature cycling. The relationship between the failure modes and the failure mechanisms was studied using a scanning electron microscopy.     

A reliable and environmentally friendly packagingtechnology-flip-chip joining using anisotropically conductive adhesive

There is an increasing demand to move the radio base station closer to the antenna for future mobile telecommunication systems. This requires a significant reduction in weight and volume and increased environmental compatibility. This work provides an evaluation of environmental impact and reliability when using anisotropically conductive adhesives (ACA) for flip-chip joining in radio base station applications. Conventional FR-4 substrate has been used to assemble a digital ASIC chip using an anisotropically conductive adhesive and flip-chip technology. The chip has a minimum pitch of 128 μm with 7.8 mm in chip 8 and has in total 144 bumps with a bump size of 114×126 μm². Bumping was made using electroless nickel/gold technology. Bonding quality has been characterized by optical and scanning electron microscopy and substrate planarity measurement. The main parameters affecting quality are misalignment and softening of the FR-4 substrate during assembly, leading to high joint resistance. Reliability testing was conducted in the form of a temperature cycling test between -40 and ±125°C for 1000 cycles, a 125°C aging test for 100 h and a 85/85 humidity test for 500 h. The results show that relatively small resistance changes were observed after the reliability test. The environmental impact evaluation was done in the form of a material content declaration and a life cycle assessment (LCA). By using flip-chip ACA joining technology, the content of environmentally risky materials has been reduced more than ten times, and the use of precious metals has been reduced more than 30 times compared to conventional surface mount technology     

Effect of substrate flexibility on solder joint reliability. Part II: finite element modeling

Solder joint fatigue failure is a serious reliability concern in area array technologies, such as flip chip and ball grid array packages of integrated-circuit chips. The selection of different substrate materials could affect solder joint thermal fatigue life significantly. The mechanism of substrate flexibility on improving solder joint thermal fatigue was investigated by thermal mechanical analysis (TMA) technique and finite element modeling. The reliability of solder joints in real flip chip assembly with both rigid and compliant substrates was evaluated by accelerated temperature cycling test. Finite element simulations were conducted to study the reliability of solder joints in flip chip on flex assembly (FCOF) and flip chip on rigid board assembly (FCOB) applying Anand model. Based on the finite element analysis results, the fatigue lives of solder joints were obtained by Darveaux’s crack initiation and growth model. The thermal strain/stress in solder joints of flip chip assemblies with different substrates were compared. The results of finite element analysis showed a good agreement with the experimental results. It was found that the thermal fatigue lifetime of FCOF solder joints was much longer than that of FCOB solder joints. The thermal strain/stress in solder joints could be reduced by flex buckling or bending and flex substrates could dissipate energy that otherwise would be absorbed by solder joints. It was concluded that substrate flexibility has a great effect on solder joint reliability and the reliability improvement was attributed to flex buckling or bending during temperature cycling.