Multichip Module Diagnosis by Product-Code Signatures

A system diagnosis technique for multichip module (MCM) ispresented. The proposed technique uses built-in probes for monitoringinternal responses and, with a signature analysis scheme based onerror correcting codes, identifies the probes where erroneous test responses have been detected. Conceptsfrom system diagnosis is used in conjunction withsignature analysis in developing the proposed MCM diagnosistechnique, where the resulting patterns of the faulty probes are usedin the identification of the faulty submodules (dies). The proposedtechnique offers a diagnostic capability in system functional test.     

A Classical Parameter Identification Method and?a?Modern Test Generation Algorithm

Many methods have been presented for the testing and diagnosis of analog circuits. Each of these methods has its advantages and disadvantages. In this paper we propose a novel sensitivity analysis algorithm for the classical parameter identification method and a continuous fault model for the modern test generation algorithm, and we compare the characteristics of these methods. At present, parameter identification based on the component connection model (CCM) cannot ensure that the diagnostic equation is optimal. The sensitivity analysis algorithm proposed in this paper can choose the optimal set of trees to construct an optimal CCM diagnostic equation, and enhance the diagnostic precision. But nowadays increasing attention is being paid to test generation algorithms. Most test generation algorithms use a single value in the fault model. But the single values cannot substitute for the actual faults that may occur, because the possible faulty values vary over a continuous range. To solve this problem, this paper presents a continuous fault model for the test generation algorithm which has a continuous range of parameters. The test generation algorithm with this model can improve the treatment of the tolerance problem, including the tolerances of both normal and faulty parameters, and enhance the fault coverage rate. The two methods can be applied in different situations.     

Board-level built-in self-repair method of RAM

This paper describes the method of built-in self-repairing of RAM on board, designs hardware circuit, and logic for the RAM’s faults self-repairing system based on FPGA. The key technology is that it utilizes FPGA to test RAM according to some algorithm to find out failure memory units and replace the faulty units with FPGA. Then it can build a memory that has no fault concern to external controller, and realizes the logic binding between external controller and RAM. Micro Controller Unit (MCU) can operate external RAM correctly even if RAM has some fault address units. Conventional MCS-51 is used to simulate the operation of MCU operating external memory. Simulation shows FPGA can complete the faulty address units’ mapping and MCU can normally read and write external RAM. This design realizes the RAM’s built-in self-repairing on board.     

BIST-based test and diagnosis of FPGA logic blocks

We present a built-in self-test (BIST) approach able to detect and accurately diagnose all single and practically all multiple faulty programmable logic blocks (PLBs) in field programmable gate arrays (FPGAs) with maximum diagnostic resolution. Unlike conventional BIST, FPGA BIST does not involve any area overhead or performance degradation. We also identify and solve the problem of testing configuration multiplexers that was either ignored or incorrectly solved in most previous work. We introduce the first diagnosis method for multiple faulty PLBs; for any faulty PLB, we also identify its internal faulty modules or modes of operation. Our accurate diagnosis provides the basis for both failure analysis used for yield improvement and for any repair strategy used for fault-tolerance in reconfigurable systems. We present experimental results showing detection and identification of faulty PLBs in actual defective FPGAs. Our BIST architecture is easily scalable     

Fault Diagnosis of Nonlinear Analog Circuits Using Neural Networks with Wavelet and Fourier Transforms as Preprocessors

A neural-network based analog fault diagnostic system is developed for nonlinear circuits. This system uses wavelet and Fourier transforms, normalization and principal component analysis as preprocessors to extract an optimal number of features from the circuit node voltages. These features are then used to train a neural network to diagnose soft and hard faulty components in nonlinear circuits. Our neural network architecture has as many outputs as there are fault classes where these outputs estimate the probabilities that input features belong to different fault classes. Application of this system to two sample circuits using SPICE simulations shows its capability to correctly classify soft and hard faulty components in 95% of the test data. The accuracy of our proposed system on test data to diagnose a circuit as faulty or fault-free, without identifying the fault classes, is 99%. Because of poor diagnostic accuracy of backpropagation neural networks reported in the literature (Yu et al., Electron. Lett., Vol. 30, 1994), it has been suggested that such an architecture is not suitable for analog fault diagnosis (Yang et al., IEEE Trans. on CAD, Vol. 19, 2000). The results of the work presented here clearly do not support this claim and indicate this architecture can provide a robust fault diagnostic system.     

NASA ground terminal communication equipment: Automated fault isolation expert systems

This paper describes the prototype expert systems that diagnose the Distribution and Switching System I and II (DSS1 and DSS2), Statistical Multiplexers (SM), and Multiplexer and Demultiplexer systems (MDM) at the NASA Ground Terminal (NGT) located at White Sands, New Mexico. A system-level fault isolation expert system monitors the activities of a selected data stream, verifies that the fault exists in the NGT and identifies the faulty equipment. Equipment-level fault isolation expert systems will be invoked to isolate the fault to a Line Replaceable Unit (LRU) level. Input and sometimes output data stream activities for the equipment are available. The system-level fault isolation expert system will compare the equipment input and output status for a data stream and perform loopback tests (if necessary) to isolate the faulty equipment. The equipment-level fault isolation system utilizes the process of elimination and/or the maintenance personnel's fault isolation experience stored in its knowledge base. The DSS1, DSS2, and SM fault isolation systems, using the knowledge of the current equipment configuration and the equipment circuitry, will issue a set of test connections according to the predefined rules. The faulty component or board can be identified by the expert system by analyzing the test results. The MDM fault isolation system correlates the failure symptoms with the faulty component based on maintenance personnel experience. The faulty component can be determined by knowing the failure symptoms.

The NGT fault isolation prototype is implemented in Prolog, C, and VP-Expert, on an IBM AT compatible workstation. The DSS1, DSS2, SM, and MDM equipment simulators are implemented in PASCAL. The equipment simulator receives connection commands and responds with status for the expert system according to the assigned faulty component in the equipment. The DSS1 fault isolation expert system was converted to C language from VP-Expert and integrated into the NGT automation software for offline switch diagnoses.

Potentially, the NGT fault isolation algorithms can be used for the DSS1, SM, and MDM located at Goddard Space Flight Center (GSFC). The prototype could be a training tool for the NGT and NASA Communications (Nascom) Network maintenance personnel.     

Active-amplifier-array diagnostics using high-resolutionelectrooptic field mapping

Several Ka-band spatial-amplifier power combiners and their free-space feeds were characterized using a high-resolution extreme-near-field electrooptic measurement technique. The two-dimensional electric-field amplitude and phase maps obtained from several arrays are presented. The usefulness of the technique for diagnostic purposes during the design and prototyping stages of the active arrays is discussed. In particular, the electrooptic maps were shown to be valuable for making improvements in the bias line design in one case, and for isolating faulty unit cells in another case     

Fault Diagnosis of Analog Circuits Using Bayesian Neural Networks with Wavelet Transform as Preprocessor

We have developed an analog circuit fault diagnostic system based on Bayesian neural networks using wavelet transform, normalization and principal component analysis as preprocessors. Our proposed system uses these preprocessing techniques to extract optimal features from the output(s) of an analog circuit. These features are then used to train and test a neural network to identify faulty components using Bayesian learning of network weights. For sample circuits simulated using SPICE, our neural network can correctly classify faulty components with 96% accuracy.     

Online BIST and BIST-based diagnosis of FPGA logic blocks

We present the first online built-in self-test (BIST) and BIST-based diagnosis of programmable logic resources in field-programmable gate arrays (FPGAs). These techniques were implemented and used in a roving self-testing areas (STARs) approach to testing and reconfiguration of FPGAs for fault-tolerant applications. The BIST approach provides complete testing of the programmable logic blocks (PLBs) in the FPGA during normal system operation. The BIST-based diagnosis can identify any group of faulty PLBs, then applies additional diagnostic configurations to identify the faulty look-up table or flip-flop within a faulty PLB. The ability to locate defective modules inside a PLB enables a new form of fault-tolerance that reuses partially defective PLBs in their fault-free modes of operation.     

New defect detection approach using near electromagnetic field probing of high density PCBAs

With the density increase of today's printed circuit board assemblies (PCBA), the electronic fault detection methods reached their limits. In the same time the requirements of high reliability and robustness are greater. Industrials are obliged to find better-adapted test methods. Current test methods must be rethought to include a large panel of physical phenomena that can be used to detect electrical defects of components, absence, wrong value, and shorts at component level on the board under test (BUT).We will present the possibility of using electromagnetic signature to diagnose faulty components contactlessly. The technique consists in using magnetic field probes, which detect the field distribution over powered sensitive components. Reference EM signatures are extracted from a fault-free circuit, which will be compared to those extracted from a sample PCBA in which we introduced a component level defect by removing or changing the value of critical components to evaluate the relevance of the method.     

Distributed diagnosis for homogeneous systems

This article presents a distributed fault-diagnosis algorithm for identifying faulty and fault-free units (processors, PEs, cells) in homogeneous systems. It is based on local comparison among units in a system and dissemination of the test results. Each unit performs comparison with its neighbors by using its own comparator. Unlike other approaches, the algorithm does not assume that diagnostic circuits are fault free. The algorithm is simple enough to be realized with small circuit overhead. The results are especially useful in locating faulty units in processor arrays implemented on a single chip or wafer. Computer simulation has shown that even for low unit yields, extremely high performance (fault coverage) can be obtained by adjusting algorithm parameters.     

Effect of Ag doping on the electrical properties of thermally deposited CdS–La2O3 TFTs

This paper describes a new approach for repairing memories. Repair is implemented by deletion of either rows and/or columns on which faulty cells lie. These devices are commonly referred to as redundant memories, because redundant columns and rows are added. A new repair technique and an algorithm are proposed. The algorithm is based on a fault-counting technique and on a reduced-covering approach. The innovative feature is that reduced covering permits an heuristic, but efficient, criterion to be included in the selection of the rows and/or columns to be deleted. This retains independence of the repair process on the distribution of faulty cells in memory, while allowing a good repairability/ unrepairability detection. The main benefits that result by using the proposed repair algorithm are a reduction in execution time to determine the repair-solution for the device under test and its suitability for implementation in a defect analysis system. Illustrative examples and theoretical results are provided to substantiate the validity of the proposed repair technique     

基于红外温度序列的电路板故障诊断研究

电路板红外温度序列包含了丰富的故障类别信息,充分利用其局部与全局特征可以提高电路板故障诊断的准确率。为此,文中提出了一种由特征提取网络(Features Extraction Network,FEN)与关系学习网络(Relationship Learning Network,RLN)并行构成的可综合利用温度序列局部特征及特征间关系的电路板故障诊断模型。其中,FEN基于多尺度膨胀卷积(Multi-scale Dilated CNN,MDCNN)残差结构搭建,可在不增加训练参数的前提下构建多层次感受野,学习温度序列不同范围的空间特征;RLN基于嵌入长短期记忆网络的注意力机制(Long Short-Term Memory hybridized with Attention,LSTMwAtt)结构搭建,通过控制温度序列信息传递来学习特征重要性并分配权重,挖掘不同位置特征间的相关性。实验结果显示,所提模型在两个自建电路板温度序列测试数据集上的诊断性能优于同类型的FCN、MFCN、LSTM和LSTM-FCN,故障诊断准确率分别达到91.15%和96.27%,可实现对电路板故障的高准确率诊断。     

基于锁相环技术的过程辨识方法研究

针对广泛应用的继电反馈自整定控制器辨识方法的局限性,提出一种基于锁相环原理的过程非参数模型辨识方法。以NI公司的虚拟仪器软件LabVIEW为开发平台设计了锁相环过程辨识系统,包括被控过程仿真器、PCI-6024E数据采集卡和锁相环辨识软件设计三部分。实践证明,该系统具有操作简单,辨识精度较高的特点,具有良好的应用前景。     

Method for Analog Circuit Soft-Fault Diagnosis and Parameter Identification Based on Indictor of Phase Deviation and Spectral Radius

The soft fault induced by parameter variation is one of the most challenging problems in the domain of fault diagnosis for analog circuits. A new fault location and parameter prediction approach for soft-faults diagnosis in analog circuits is presented in this paper. The proposed method extracts the original signals from the output terminals of the circuits under test (CUT) by a data acquisition board. Firstly, the phase deviation value between fault-free and faulty conditions is obtained by fitting the sampling sequence with a sine curve. Secondly, the sampling sequence is organized into a square matrix and the spectral radius of this matrix is obtained. Thirdly, the smallest error of the spectral radius and the corresponding component value are obtained through comparing the spectral radius and phase deviation value with the trend curves of them, respectively, which are calculated from the simulation data. Finally, the fault location is completed by using the smallest error, and the corresponding component value is the parameter identification result. Both simulated and experimental results show the effectiveness of the proposed approach. It is particularly suitable for the fault location and parameter identification for analog integrated circuits.     

Switch fault detection and diagnosis in space vector modulated cascaded H-bridge multilevel inverter

This article investigates the development and online implementation of the power switch open-circuit fault detection and diagnosis in symmetric cascaded H-bridge multilevel inverter. A mathematical modelling technique is presented to understand the effect of the fault on the bridge voltages and output voltage. The modelled values of the output voltage, simulation results and experimental results indicate that the fault diagnostic methods based on the output voltage as the diagnostic feature have certain ambiguity in identifying the fault switch, since the output voltage waveform and its features remain the same for a group of switches under the fault condition. In order to overcome this, fault detection and diagnosis method based on the mean values of the bridge voltages is proposed in this article, which identifies the faulty switch pair and H-bridge in which the fault has occurred. Further, this method has been experimentally validated on a five-level space vector modulated symmetric cascaded H-bridge multilevel inverter.     

Fault Diagnosis in Mixed-Signal Low Testability System

This paper describes a new approach for fault diagnosis of analog multi-phenomenon systems with low testability. The developed algorithms include identification of ambiguity groups, fault diagnosis methodology and solving low testability equations. Our aim is to identify a minimum number of faulty parameters that satisfy the test equations called a minimum form solution. An algorithm to find a minimum form solution is presented, which is based on the solution invariant matrix and an identification of singular cofactors of this matrix. System simulation using a developed C++ and Matlab programs was performed to test different faulty circuits. Test examples are discussed and simulation results are presented.     

Diagnostic tolerance for missing sensor data

For practical automated diagnostic systems to continue functioning after failure, they must not only be able to diagnose sensor failures but also be able to tolerate the absence of data from the faulty sensors. We show that conventional (associational) diagnostic methods will have combinatoric problems when trying to isolate faulty sensors, even if they adequately diagnose other components. Moreover, attempts to extend the operation of diagnostic capability past sensor failure will necessarily compound those difficulties. By contrast, the algorithmic methods of model-based reasoning have no special problems diagnosing faulty sensors and can operate gracefully when sensor data is missing.     

Fault Identification in Electronic Circuits with the Aid of Bilinear Transformations

A method has been developed for applying bilinear transformations to the identification of faulty components in linear electronic circuits. Simple magnitude and phase measurements, at a number of test frequencies, are made and plotted on a set of predetermined loci in the complex transfer-function plane. The data for plotting the loci are determined either experimentally or by circuit analysis with a digital computer. The faulty component and the parameter value are then determined from the loci. The method has the advantage that it provides a graphical representation of the circuit behavior with a faulty component and also readily allows experimental error to be taken into account when plotting the measured data. The method is demonstrated with a practical transistor amplifier circuit.     

一种瓦片式T/R的关键工艺分析

该文介绍了一种Ku波段瓦片式发射/接收（T/R）组件的工艺设计技术。组件整体采用了低温共烧陶瓷（LTCC）高频基板、低频电源印制电路板（PCB）和控制PCB板,利用立体组装的方式实现产品的小型化。产品采用金锡焊接SMP接头实现气密性焊接,同时采用4种焊接材料实现了产品的温度梯度焊接,并对关键工艺进行了工艺鉴定分析,保证了产品的长期可靠性。