Charge trapping memory devices employing multi-layered Ge/Si nanocrystals for storage fabricated with ALD and PLD methods

The Ge/Si nanocrystals on ultra thin high-k tunnel oxide Al2O3 were fabricated to form the charge trapping memory prototype with asymmetric tunnel barriers through combining the advanced atomic layer deposition (ALD) and pulse laser deposition (PLD)techniques. Charge storage characteristics in such memory structure have been investigated using capacitance-voltage (C-V) and capacitance-time (C-t) measurements. The results prove that both the two-layered and three-layered memory structures behave relatively qualified for the multi-level cell storage. The results also demonstrate that compared to electrons, holes reach a longer retention time even with an ultra thin tunnel oxide owing to the high band offset at the valence band between Ge and Si.     

Impact of high-κ dielectric and metal nanoparticles in simultaneous enhancement of programming speed and retention time of nano-flash memory

A methodology to simulate memory structures with metal nanocrystal islands embedded as floating gate in a high-κ dielectric material for simultaneous enhancement of programming speed and retention time is presented. The computational concept is based on a model for charge transport in nano-scaled structures presented earlier, where quantum mechanical tunneling is defined through the wave impedance that is analogous to the transmission line theory. The effects of substrate-tunnel dielectric conduction band offset and metal work function on the tunneling current that determines the programming speed and retention time is demonstrated. Simulation results confirm that a high-κ dielectric material can increase programming current due to its lower conduction band offset with the substrate and also can be effectively integrated with suitable embedded metal nanocrystals having high work function for efficient data retention. A nano-memory cell designed with silver (Ag) nanocrystals embedded in Al₂O₃ has been compared with similar structure consisting of Si nanocrystals in SiO₂ to validate the concept.     

Novel Quantum Dot Gate FETs and Nonvolatile Memories Using Lattice-Matched II–VI Gate Insulators

This paper presents the successful use of ZnS/ZnMgS and other II–VI layers (lattice-matched or pseudomorphic) as high-k gate dielectrics in the fabrication of quantum dot (QD) gate Si field-effect transistors (FETs) and nonvolatile memory structures. Quantum dot gate FETs and nonvolatile memories have been fabricated in two basic configurations: (1) monodispersed cladded Ge nanocrystals (e.g., GeO _x -cladded-Ge quantum dots) site-specifically self-assembled over the lattice-matched ZnMgS gate insulator in the channel region, and (2) ZnTe-ZnMgTe quantum dots formed by self-organization, using metalorganic chemical vapor-phase deposition (MOCVD), on ZnS-ZnMgS gate insulator layers grown epitaxially on Si substrates. Self-assembled GeO _x -cladded Ge QD gate FETs, exhibiting three-state behavior, are also described. Preliminary results on InGaAs-on-InP FETs, using ZnMgSeTe/ZnSe gate insulator layers, are presented.     

Electrical characteristics of gold nanoparticle-embedded MIS capacitors with parylene gate dielectric

Memory characteristics of gold nanoparticle-embedded metal–insulator–semiconductor (MIS) capacitors with polymer (parylene-C) gate insulating material are investigated in this study. The gold nanoparticles used in this work were synthesized by the colloidal method. Current density versus voltage curves obtained from the MIS capacitors exhibit better performance for the parylene-C gate insulator, compared with other gate insulating materials. Capacitance versus voltage (C–V) curves show a flat band voltage shift, which indicates the possibility of charge storage in the gold nanoparticles. In addition, the charge retention characteristic for the gold nanoparticle-embedded MIS capacitor is described in this paper.     

KFM detection of charges injected by AFM into a thin SiO2 layer containing Si nanocrystals

Charge retention of Si nanocrystals elaborated by ultra-low energy ion implantation and thermal annealings into a thin SiO₂ layer is characterized by atomic force microscopy (AFM) and Kelvin force microscopy (KFM). Electrons and holes are injected under ambient conditions by applying different bias to a conductive AFM tip in contact with the grounded sample. A surface potential mapping of the sample by KFM is continuously carried out after charge injection. The temporal decay of injected charges and their corresponding lateral spreading are quantified. The results show that the presence of Si nanocrystals leads to a strong charge confinement.     

纳米晶浮栅存储器的模拟、制备和电学特性

介绍了在纳米晶浮栅存储器数据保持特性方面的研究工作,重点介绍了纳米晶材料的选择与制备和遂穿介质层工程。研究证明,金属纳米晶浮栅存储器比半导体纳米晶浮栅存储器具有更好的电荷保持特性。并且金属纳米晶制备方法简单,通过电子束蒸发热退火的方法就能够得到质量较好的金属纳米晶,密度约4×1011cm-2,纳米晶尺寸约6～7nm。实验证明,高介电常数隧穿介质能够明显改善浮栅存储器的电荷保持特性,所以在引入金属纳米晶和高介电常数遂穿介质之后,纳米晶浮栅存储器可能成为下一代非挥发性存储器的候选者。     

Flexible and transparent nanocrystal floating gate memory devices using silk protein

The charge storage behavior of a floating gate memory device using carbon nanotube-CdS nanostructures embedded in Bombyx mori silk protein matrix has been demonstrated. The capacitance – voltage characteristics in ITO/CNT–CdS-silk composite/Al device exhibits a clockwise hysteresis behavior due to the injection and storage of holes in the quantized valence band energy levels of CdS nanocrystals. The enhanced charge injection resulting in increase in memory window is observed at higher sweeping voltages. Nearly frequency independent hysteresis width over a wide range of 100 kHz–2.0 MHz, indicates its origin due to the charge storage in nanocrystals. The memory behavior of carbon nanotube–CdS nanostructures/silk nanocomposite devices has also been demonstrated on polyethylene terephthalate substrates, which may provide the way for flexible, transparent and printable electronic devices.     

氮气或氧气气氛退火的氧化铪材料电荷泄漏情况研究

本文中, 使用开尔文探针显微镜,研究了不同退火气氛(氧气或氮气)情况下氧化铪材料的电子和空穴的电荷保持特性。与氮气退火器件相比,氧气退火可以使保持性能变好。横向扩散和纵向泄露在电荷泄露机制中都起了重要的作用。 并且,保持性能的改善与陷阱能级深度有关。氮气和氧气退火情况下,氧化铪存储结构的的电子分别为0.44 eV, 0.49 eV,空穴能级分别为0.34 eV, 0.36 eV。 最后得到,不同退火气氛存储器件的电学性能也与KFM结果一致。对于氧化铪作为存储层的存储器件而言,对存储特性的定性和定量分析,陷阱能级,还有泄漏机制研究是十分有意义的。     

Asymmetric electric field enhancement in nanocrystal memories

The electrostatic model for nanocrystal memories is used to illustrate the fundamental difference of the metal nanocrystal memory in low-voltage program/erase (P/E) operations in comparison with semiconductor nanocrystal and trap-based memories. Due to repulsion of potential contours inside conductors, the metal nanocrystals will significantly enhance the electric field between the nanocrystal and the sensing channel set up by the control gate bias and, hence, can achieve much higher efficiency in low-voltage P/E. On the other hand, the electric field originated from the stored charge will only be slightly different for metal and semiconductor nanocrystal cases. We presented the electrostatic models by both approximate analytical formulation and three-dimensional numerical simulation in a nanocrystal array. Operations of P/E and read disturbance were analyzed for the cases of homogeneous charge distribution, silicon, and metal nanocrystals. In the P/E condition of +5/-5 V, the metal nanocrystal memory offers around 1.6 times higher peak fields than Si counterparts and almost three times higher than that from the one-dimensional model for homogeneous charge distribution. The field enhancement factor suggests the design criteria of oxide thickness, nanocrystal size, and spacing. The advantage of asymmetric field enhancement of metal nanocrystals will be even more prominent when high-K gate dielectrics are employed.     

Performance improvement of flash memory using AlN as charge-trapping Layer

Potential of high-k dielectric films for future scaled charge storage non-volatile memory (NVM) device applications is discussed. To overcome the problems of charge loss encountered in conventional flash memories with silicon-nitride (Si₃N₄) films and polysilicon-oxide-nitride-oxide-silicon (SONOS) and nonuniformity issues in nanocrystal memories (NC), such as Si, Ge and metal, it is shown that the use of high-k dielectrics allows more aggressive scaling of the tunnel dielectric, smaller operating voltage, better endurance, and faster program/erase speeds. Charge-trapping characteristics of high-k AlN films with SiO₂ as a blocking oxide in p-Si/SiO₂/AlN/SiO₂/poly-silicon (SOHOS) memory structures have been investigated in detail. The experimental results of program/erase characteristics obtained as the functions of gate bias voltage and pulse width are presented.     

Multilevel charge storage in Si nanocrystals arranged in double-dot-layers within SiO2

We investigated charging/discharging characteristics of a MOS structure with two layers of Si-nanocrystals (NCs) embedded in the SiO₂ dielectric. The two-dimensional (2D) arrays of nanocrystals, of sizes 3 and 5 nm in the lower and upper NCs layer, respectively, were fabricated by low pressure chemical vapor deposition (LPCVD) of amorphous Si (a-Si), followed by oxidation/annealing. The tunnel oxide was 3.5 nm thick. Successive charging of the NCs layers by both electrons and holes injected from the substrate was clearly demonstrated by the observed steps in the flatband voltage shift (ΔV_FB) as a function of the applied positive (electrons) or negative (holes) pulses on the gate, thus opening the potential for multiple bit operation of the memory. Discharging of the structure by pulses of opposite sign was consistently obtained. The current-voltage (I-V) curves exhibited two transient peaks at voltages corresponding to the two steps in ΔV_FB vs. V_gate that were attributed to a displacement current from the substrate to the nanocrystal layers. Clear improvement of charge retention in the double-nanocrystal layer structure compared to the single one was obtained, opening the possibility for lowering the gate oxide thickness of the NC memory without compromising device reliability.     

Nonvolatile memory with a metal nanocrystal/nitride heterogeneous floating-gate

Heterogeneous floating-gates consisting of metal nanocrystals and silicon nitride (Si/sub 3/N/sub 4/) for nonvolatile memory applications have been fabricated and characterized. By combining the self-assembled Au nanocrystals and plasma-enhanced chemical vapor deposition (PECVD) nitride layer, the heterogeneous-stack devices can achieve enhanced retention, endurance, and low-voltage program/erase characteristics over single-layer nanocrystals or nitride floating-gate memories. The metal nanocrystals at the lower stack enable the direct tunneling mechanism during program/erase to achieve low-voltage operation and good endurance, while the nitride layer at the upper stack works as an additional charge trap layer to enlarge the memory window and significantly improve the retention time. The write/erase time of the heterogeneous stack is almost the same as that of the single-layer metal nanocrystals. In addition, we could further enhance the memory window by stacking more nanocrystal/nitride heterogeneous layers, as long as the effective oxide thickness from the control gate is still within reasonable ranges to control the short channel effects.     

Characteristics of p-channel Si nano-crystal memory

In this work, the feasibility of p-channel nano-crystal memory with thin oxide in direct tunneling regime is demonstrated. By comparing the programming characteristics of devices with nano-crystals and devices without nano-crystals, the role of dots as storage node is presented. The programming and erasing mechanisms of p-channel nano-crystal memory were investigated by charge separation technique. For small gate programming voltage, hole tunneling component from inversion layer is dominant. However, valence band electron tunneling component from the valence band in the nano-crystal becomes dominant for large gate voltage. In case of erasing, the electron tunneling occurs from either the conduction band or the valence band. Finally, the comparison of retention between programmed holes and electrons shows that holes have longer retention time     

Ge-related impurities in high-k oxides: Carrier traps and interaction with native defects

Volatilization of a Ge substrate may generate a large number of impurities inside the gate dielectric of a Ge-based device. Here we use density-functional theory calculations to probe the stability of Ge atoms and GeO molecules inside Al₂O₃ and Y₂O₃ high-k oxides. We identify the most stable impurity configurations and we show that both types of extrinsic species generate levels inside the energy band gap of the host systems. We also find that Ge and GeO impurities get trapped at O vacancies and replace the vacancy-related carrier traps with different types of levels in the gap. The results identify atomic-scale mechanisms that underlie gate leakage and charge trapping in Ge-based electronic systems.     

Properties of Ge nanocrystals formed by implantation of Ge<Superscript>+</Superscript> ions into SiO<Subscript>2</Subscript> films with subsequent annealing under hydrostatic pressure

The influence of hydrostatic compression on the implantation-induced synthesis of Ge nanocrystals in SiO₂ host was studied. It is found that high-temperature annealing under pressure leads to retardation of Ge diffusion in SiO₂. It is shown that unstressed Ge nanocrystals are formed as a result of conventional annealing (under atmospheric pressure). Annealing under pressure is accompanied by formation of hydrostatically stressed Ge nanocrystals. The stress in Ge nanocrystals was determined from optical-phonon frequencies in the Raman spectra. The shift of Raman resonance energy (E₁, E₁ + Δ₁) corresponds to the quantization of the ground-state energy for a two-dimensional exciton at the critical point M₁ of germanium. It is ascertained that a photoluminescence band peaked at 520 nm is observed only in the spectra of the films which contain stressed Ge nanocrystals.     

Self-assembled metallic nanocrystal structures for advanced non-volatile memory applications

Nanocrystal (NC) based non-volatile memories are a leading candidate to replace conventional floating gate memory. Substituting the poly-silicon gate with a layer of discrete nanocrystals or nanodots provides increased immunity to charge loss. Metallic nanocrystals have been found to be advantageous over Si- or Ge-based approaches due to good controllability of the size distribution and the achievable NC densities as well as increased charge storage capacity of metallic nanocrystals. Sufficiently high NC densities have been achieved to demonstrate feasibility for sub-32 nm node non-volatile memory devices.     

Leakage paths identification in NVM using biased data retention

In this paper we propose a way to study leakage paths for electrons during data retention in floating gate non-volatile memories and especially in EEPROM memory cells. We investigate the main leakage paths, through tunnel oxide as well as through the tri-layer stack oxide “oxide/nitride/oxide” (ONO). We used a TCAD simulation of the full EEPROM cell to precisely determine the control gate bias voiding the electric field through ONO or tunnel oxide. Data retention measurements are then performed with simulated bias. We highlight the fact that leakage paths during data retention are different for extrinsic and intrinsic cells. Indeed, extrinsic behavior disappears when voiding electric field across tunnel oxide, showing these cells leak through tunnel oxide, whereas intrinsic behavior is the same whatever the electric field across tunnel oxide, showing charge loss in intrinsic cells is due to another path.     

Improvement of the P/E window in nanocrystal memories by the use of high-k materials in the control dielectric

In this paper nanocrystals memories program curves are shown and their saturation points (steady state condition) can be observed. We present a model that relates the voltage shift at the steady state (ΔV_Tss) to the gate program voltage (V_G). Starting from a good agreement between experimental data and simulations for nanocrystals memory cells with a conventional dielectric structure (SiO₂), we present the estimated values of the ΔV_Tss vs V_G for different control stacks. Our investigation shows an improvement if a material with a high dielectric constant and a small conduction band-offset with respect to the SiO₂, is placed between two SiO₂ layers when the first of them is very thin.     

Program efficiency and high temperature retention of SiN/high-K based memories

This paper presents an experimental and simulation study of the program efficiency and retention of SANOS memory cells. We analyzed the experimental curves of the available cells by a physics based model that includes drift-diffusion transport of carriers in the nitride conduction band. We evidenced how the gate stack dimensions impact the program efficiency; in particular, thicker Si₃N₄ layers allow for faster programming. However, the Si₃N₄ thickness hardly influence the high temperature retention, since charge loss due to thermal emission dominates. Good agreement of the model with a wide set of experiments makes us confident on the validity of the interpretation of data which is suggested by the modeling results.     

Electron states at the (1 0 0)Ge/HfO2 Interface

The energy distribution of extended and localized electron states at the Ge/HfO₂ interface is determined by combining the internal photoemission of electrons and holes from Ge into the Hf oxide and AC capacitance/conductance measurements. The inferred offsets of the conduction and valence band at the interface, i.e., 2.0 ± 0.1 and 3.0 ± 0.1 eV, respectively, suggest the possibility to apply the deposited HfO₂ layer as a suitable insulator on Ge. The post-deposition annealing of the Ge/HfO₂ structures in oxygen results in 1 eV reduction of the valence band offset, which is attributed to the growth of a GeO₂ interlayer. However, this treatment enables one to substantially reduce the density of Ge/HfO₂ interface traps, approaching ≈1×10¹² cm⁻² eV⁻¹ near the Ge midgap.