Investigation of n-ohmic contact of vertical GaN-based light-emitting diodes on graphite substrate with Ag-In bonding

Vertical light-emitting diodes (VLEDs) were successfully transferred from a GaN-based sapphire substrate to a graphite substrate by using low-temperature and cost-effective Ag-In bonding, followed by the removal of the sapphire substrate using a laser lift-off (LLO) technique. One reason for the high thermal stability of the AgIn bonding compounds is that both the bonding metals and Cr/Au n-ohmic contact metal are capable of surviving annealing temperatures in excess of 600 °C. Therefore, the annealing of n-ohmic contact was performed at temperatures of 400 °C and 500 °C for 1 min in ambient air by using the rapid thermal annealing (RTA) process. The performance of the n-ohmic contact metal in VLEDs on a graphite substrate was investigated in this study. As a result, the final fabricated VLEDs (chip size: 1000 µm×1000 µm) demonstrated excellent performance with an average output power of 538.64 mW and a low operating voltage of 3.21 V at 350 mA, which corresponds to an enhancement of 9.3% in the light output power and a reduction of 1.8% in the forward voltage compared to that without any n-ohmic contact treatment. This points to a high level of thermal stability and cost-effective Ag-In bonding, which is promising for application to VLED fabrication.     

Improvement of GaN-based light-emitting diode by indium-tin-oxide transparent electrode and vertical electrode

A sapphire-etched vertical-electrode nitride semiconductor (SEVENS) light-emitting diode (LED) is fabricated by means of a selective chemical wet-etching technique. The SEVENS-LED formed on sapphire substrate exhibits excellent device performance compared to a conventional NiAu lateral-electrode (LE) GaN-based LED formed on the same sapphire substrate. The integral light-output power of SEVENS-LED is /spl sim/7 mW, which is 1.75 times stronger than that of the conventional NiAu LE-LED (/spl sim/4 mW). The external quantum efficiency of SEVENS-LED is estimated to be approximately 13%.     

Optimizing n-type contact design and chip size for high-performance indium gallium nitride/gallium nitride-based thin-film vertical light-emitting diode

The effects of the n-contact design and chip size on the electrical, optical and thermal characteristics of thin-film vertical light-emitting diodes (VLEDs) were investigated to optimize GaN-based LED performance for solid-state lighting applications. For the small (chip size: 1000×1000 µm²) and large (1450×1450 µm²) VLEDs, the forward bias voltages are decreased from 3.22 to 3.12 V at 350 mA and from 3.44 to 3.16 V at 700  mA, respectively, as the number of n-contact via holes is increased. The small LEDs give maximum output powers of 651.0–675.4 mW at a drive current of 350 mA, while the large VLEDs show the light output powers in the range 1356.7–1380.2 mW, 700 mA, With increasing drive current, the small chips go through more severe degradation in the wall-plug efficiency than the large chips. The small chips give the junction temperatures in the range 51.1–57.2 °C at 350  mA, while the large chips show the junction temperatures of 83.1–93.0 °C at 700  mA, The small LED chips exhibit lower junction temperatures when equipped with more n-contact via holes.     

Optimization and validation of thermal management for a RF front-end SiP based on rigid-flex substrate

This paper mainly presents a new 3D stacking RF System-in-Package (SiP) structure based on rigid-flex substrate for a micro base station, with 33 active chips integrated in a small package of 5cm × 5.5cm × 0.8cm. Total power consumption adds up to 20.1 Watt. To address thermal management and testability difficulties of this RF SiP, a thermal test package is designed with the same package structure and assembly flow, only replacing active chips with thermal test dies (TTDs). Optimization and validation of thermal management for the thermal test package is conducted. Effects of the structure, chip power distribution, and ambient temperature aspects on the thermal performance are studied. Thermal vias designed in the organic substrate provide a direct heat dissipation path from TTDs to the top heatsink, which minimizes junction temperature gap of the top substrate from 31.2 °C to 5.3 °C, and enables junction temperatures of all the chips on the face to face structure to be well below 82 °C. Chip power distribution optimization indicates placing high power RF parts on the top rigid substrate is a reasonable choice. The ambient temperature optimizes with forced air convection and cold-plate cooling method, both of which are effective methods to improve thermal performances especially for this micro base station application where environment temperature may reach more than 75 °C. The thermal management validation is performed with a thermal test vehicle. Junction temperatures are compared between finite-volume-method (FVM) simulation and thermal measurement under the natural convection condition. The accordance of simulation and measurement validates this thermal test method. Junction temperatures of typical RF chips are all below 80 °C, which shows the effectiveness of thermal management of this RF SiP.     

Germanium on sapphire by wafer bonding

This paper describes the creation of a germanium on sapphire platform, via wafer bonding technology, for system-on-a-chip applications. Similar thermal coefficients of expansion between germanium (5.8 × 10^?6 K^?1) and sapphire (5 × 10^?6 K^?1) make the bonding of germanium to sapphire a reality. Germanium directly bonded to sapphire results in microvoid generation during post bond annealing. Inclusion of an interface layer such as silicon dioxide layer by plasma enhanced chemical vapour deposition, prior to bonding, results in a microvoid free bond interface after annealing. Grinding and polishing of the subsequent germanium layer has been achieved leaving a thick germanium on sapphire (GeOS) substrate. Submicron GeOS layers have also been achieved with hydrogen/helium co-implantation and layer transfer. Circular geometry transistors exhibiting a field effect mobility of 890 cm²/V s have been fabricated onto the thick germanium on sapphire layer.     

Improving the light output power of GaN-based light-emitting diodes through the use of SiO2 cones

We introduced a simple wet-etching process to form SiO₂ cones and investigated the effect of the size and coverage of the SiO₂ cones on the output power of GaN-based light-emitting diodes (LEDs). The diameter of the cones varies from 2.8 to 17.1 μm and the height from 0.6 to 2.0 μm. It is shown that regardless of the sizes of the cones, all of the LEDs exhibit a same forward-bias voltage of 3.31 V at an injection current of 20 mA. As the size of the cones increases, the light output increases, reaches maximum at cone #3 (12.4 μm in diameter and 2.0 μm in height), and then decrease slightly. For example, the LEDs fabricated with different SiO₂ cones exhibit 11.4–35.9% higher light output power (at 20 mA) than do the LEDs without the cones. The electroluminescence (EL) intensity (at 20 mA) also exhibits cone size dependence similar to that of light output power. For example, the LEDs fabricated with different cones exhibit 7.7–36.3% higher EL intensity than the LEDs without the cones.     

Improving performance of high-power indium gallium nitride/gallium nitride-based vertical light-emitting diodes by employing simple n-type electrode pattern

In this work, simple n-type electrode structures were used to enhance the electrical and optical performances of fully packaged commercially mass-produced vertical-geometry light-emitting diodes (VLEDs). The forward bias voltage of the VLED with a Y-pattern electrode increased less rapidly than that of VLEDs with a reference electrode. The VLEDs with the reference and Y-pattern electrodes exhibited forward voltages of 2.93±0.015 and 2.89±0.015 V at 350 mA and 3.77±0.015 and 3.53±0.015 V at 2000 mA, respectively. The VLEDs with the Y-pattern electrode resulted in a higher light output than the VLEDs with the reference electrode with increase in the drive current to 2000 mA. The emission images showed that the VLEDs with the Y-pattern electrode exhibited better current spreading behavior and lower junction temperatures than the VLEDs with the reference electrode. With increase in the current from 350 to 2000 mA, the VLEDs with the Y-pattern electrode experienced a 39.4% reduction in the wall plug efficiency, whereas the VLEDs with the reference electrode suffered from a 43.3% reduction.     

New hole blocking material for green-emitting phosphorescent organic electroluminescent devices

The new amorphous molecular material, 2,5-bis(4-triphenylsilanyl-phenyl)-[1,3,4]oxadiazole, that functions as good hole blocker as well as electron transporting layer in the phosphorescent devices. The obtained material forms homogeneous and stable amorphous film. The new synthesized showed the reversible cathodic reduction for hole blocking material and the low reduction potential for electron transporting material in organic electroluminescent (EL) devices. The fabricated devices exhibited high performance with high current efficiency and power efficiency of 45 cd/A and 17.7 lm/W in 10 mA/cm², which is superior to the result of the device using BAlq (current efficiency: 31.5 cd/A and power efficiency: 13.5 lm/W in 10 mA/cm²) as well-known hole blocker. The ITO/DNTPD/α-NPD/6% Ir(ppy)₃ doped CBP/2,5-bis(4-triphenylsilanyl-phenyl)-[1,3,4]oxadiazole as both hole blocking and electron transporting layer/Al device showed efficiency of 45 cd/A and maximum brightness of 3000 cd/m² in 10 mA/cm².     

Photosintering and electrical performance of CuO nanoparticle inks

A copper oxide (CuO) nanoparticle ink was inkjet printed and photosintered in order to optimize electrical performance as a function of pattern dimension. For a given photosintering condition, electrical conductance varied strongly with line widths, ranging from 100 to 300 μm, illustrating the implications of printing and sintering complex circuit designs with varying feature sizes. By tuning the time delay between printing and sintering, exposure wavelength, radiant energy, pulse width and the distance between the light-source and substrate, photosintering conditions were optimized so that variations in sheet resistance for different line widths were minimized. Using optimized photosintering conditions, a sheet resistance value as low as 150 mΩ/□ (resistivity of 9 μΩ cm) and current carrying capacity of 280 mA for a 300 μm wide trace was achieved.     

K Band SiGe HBT single ended active inductors

The study of monolithic integration of active inductors (AI) on a 0.25 μm SiGe BiCMOS technology with 4 metal layers and HBTs with f_T=120 GHz is presented. Two topologies are presented and their performance discussed. Q values higher than 30 were obtained on a 3.4 GHz bandwidth at 28 GHz and maximum values as high as 100. Active inductors can be biased with low power, such as 2 V with a nominal DC current of 0.6 mA. The inductance value is controlled by external bias voltages and adjustments up to 40% were measured. Simple gyrators topologies with only 2 transistors are used for low power consumption and good performance at K Band is proved. The internal parameters of small signal model of HBT were studied and the crucial parameter to enhance the negative resistance and so the Q of the AI was identified.     

A 1-V, 1.2-mA fully integrated SoC for digital hearing aids

Both power and size are very important design issues for hearing aids. This paper proposes a fully integrated low-power SoC for today׳s digital hearing aids. The SoC integrates all the audio processing elements on single chip, including the analog front-end, digital signal processing (DSP) platform and class-D amplifier. Also, the low-dropout voltage regulators and internal clock generator are both integrated to minimize the system overall size. The 24-bit DSP platform comprises an application-specific instruction-set processor and several dedicated accelerators to achieve a trade-off between flexibility and power efficiency. Three critical hearing-aid algorithms (wide dynamic range compression, noise reduction and feedback cancellation) are performed by the low-power accelerators. The proposed SoC has been fabricated in SMIC 130 nm CMOS technology. The measurement results show that the analog front-end has up to 88 dB signal-to-noise ratio. And the DSP platform consumes about 0.86 mA current at 8 MHz clock frequency when executing the three algorithms. The total current consumption of SoC is only 1.2 mA at 1 V supply. In addition, the acoustic test results indicate that the SoC is one promising candidate for hearing-aid manufacturers.     

Common-base multi-finger submicron InGaAs/InP double heterojunction bipolar transistor with fmax of 305 GHz

A layout of a common-base four-finger InGaAs/InP double heterostructure bipolar transistor (DHBT) has been designed and the corresponding DHBT has been fabricated successfully by using planarization technology. The area of each emitter finger was 1 × 15 μm². The breakdown voltage was more than 7 V, the current could be more than 100 mA. The maximum output power can be more than 80 mW derived from the DC characteristics. The maximum oscillation frequency was as high as 305 GHz at I_C = 50 mA and V_CB = 1.5 V. The DHBT is thus promising for the medium power amplifier and voltage controlled oscillator (VCO) applications at W band and higher frequencies.     

Determination of the average channel temperature of GaN MOSHFETs under continuous wave and periodic-pulsed RF operational conditions

We present a method to determine the average device channel temperature of AlGaN/GaN metal–oxide–semiconductor heterostructure field effect transistors (MOSHFETs) in the time domain under continuous wave (CW) and periodic-pulsed RF (radiation frequency) operational conditions. The temporal profiles of microwave output power densities of GaN MOSHFETs were measured at 2 GHz under such conditions and used for determination of the average channel temperature. The measurement technique in this work is also being utilized to determine the thermal time constant of the devices. Analytical temporal solutions of temperature profile in MOSHFETs are provided to support the method. The analytical solutions can also apply to generic field effect transistors (FETs) with an arbitrary form of time-dependent heat input at the top surface of the wafer. It is found that the average channel temperature of GaN MOSHFETs on a 300 μm sapphire substrate with the output power of 10 W/mm can be over 400 °C in the CW mode while the average channel temperature of GaN MOSHFETs on a SiC substrate with the same thickness only reaches 50 °C under the same condition. The highest average channel temperature in a pulsed RF mode will vary with respect to the duty cycle of the pulse and type of the substrate.     

A novel low voltage very low power CMOS class AB current output stage with ultra high output current drive capability

In this paper a novel low voltage (LV) very low power (VLP) class AB current output stage (COS) with extremely high linearity and high output impedance is presented. A novel current splitting method is used to minimize the transistors gate–source voltages providing LV operation and ultra high current drive capability. High linearity and very high output impedance are achieved employing a novel resistor based current mirror avoiding conventional cascode structures to be used. The operation of the proposed COS has been verified through HSPICE simulations based on TSMC 0.18 μm CMOS technology parameters. Under supply voltage of ±0.7 V and bias current of 5 μA, it can deliver output currents as high as 14 mA with THD better than ?53 dB and extremely high output impedance of 320 MΩ while consuming only 29 μW. This makes the proposed COS to have ultra large current drive ratio (I_outmax/I_bias or the ratio of peak output current to the bias current of output branch transistors) of 2800. By increasing supply voltage to ±0.9 V, it can deliver extremely large output current of ±24 mA corresponding to 3200 current drive ratio while consuming only 42.9 μW and exhibiting high output impedance of 350 MΩ. Interestingly, the proposed COS is the first yet reported one with such extremely high output current and a THD even less than ?45 dB. Such ultra high current drive capability, high linearity and high output impedance make the proposed COS an outstanding choice for LV, VLP and high drive current mode circuits. The superiority of the proposed COS gets more significance by showing in this work that conventional COS can deliver only ±3.29 mA in equal condition. The proposed COS also exhibits high positive and negative power supply rejection ratio (PSRR+/PSRR?) of 125 dB and 130 dB, respectively. That makes it very suitable for LV, VLP mixed mode applications. The Monte Carlo simulation results are provided, which prove the outstanding robust performance of the proposed block versus process tolerances. Favorably the proposed COS resolves the major limitation of current output stages that so far has prevented designing high drive current mode circuits under low supply voltages. In brief, the deliberate combination of so many effective novel methods presents a wonderful phenomenal COS block to the world of science and engineering.     

A high Schottky barrier between Ni and S-passivated n-type Si(1 0 0) surface

By minimizing surface states with sulfur passivation, a record-high Schottky barrier is achieved with nickel on n-type Si(1 0 0) surface. Capacitance–voltage measurements yield a flat-band barrier height of 0.97 eV. Activation-energy and current–voltage measurements indicate ～0.2-eV lower barriers for the Ni/Si(1 0 0) junction. These results accompany a previously-reported record-high Schottky barrier of 1.1 eV between aluminum and S-passivated p-type Si(1 0 0) surface. The operation of these metal/Si(1 0 0) junctions changes from majority-carrier conduction, i.e., a Schottky junction, to minority-carrier conduction, i.e., a p–n junction, with the increase in barrier height from 0.97 eV to 1.1 eV. Temperature-dependent current–voltage measurements reveal that the Ni/S-passivated n-type Si(1 0 0) junction is stable up to 110 °C.     

A low-voltage low-power CMOS transmitter front-end using current mode approach for 2.4 GHz wireless communications

This paper presents a low-voltage low-power transmitter front-end using current mode approach for 2.4 GHz wireless communication applications, which is fabricated in a chartered 0.18 μm CMOS technology. The direct up-conversion is implemented with a current mode mixer employing a novel input driver stage, which can significantly improve the linearity and consume a small amount of DC current. The driver amplifier utilizes a transimpedance amplifier as the first stage and employs an inter-stage capacitive cross-coupling technique, which enhances the power conversion gain as well as high linearity. The measured results show that at 2.4 GHz, the transmitter front-end provides 15.5 dB of power conversion gain, output P?1 dB of 3 dBm, and the output-referred third-order intercept point (OIP3) of 13.8 dBm, while drawing only 6 mA from the transmitter front-end under a supply voltage of 1.2 V. The chip area including the testing pads is only 0.9 mm×1.1 mm.     

An investigation on capacitance-trigger ESD protection devices for high voltage integrated circuits

A novel cascaded complementary dual-directional silicon controlled rectifier (CCDSCR) structure has been proposed and implemented in a 0.5 μm 20 V Bipolar/CMOS/DMOS process as an ESD (electrostatic discharge) protection device. The ESD characteristics of the capacitance-trigger CCDSCR has been investigated by transmission line pulse (TLP) testing. Compared with the substrate-trigger insulated gate bipolar transistor with the enhanced substrate parasitic capacitance, the gate-driven trigger insulated gate bipolar transistor with the gate coupling capacitance and the normal dual-directional silicon controlled rectifier, the CCDSCR has the highest holding voltage of about 25.4 V and the best current conduction uniformity. In addition, it has the best figure of merit (FOM) with the value of about 0.64 mA/μm². The good current conduction uniformity in CCDSCR due to the enhanced substrate parasitic capacitance-trigger effect is finally confirmed by Sentaurus simulations.     

Formation of low-resistance and transparent indium tin oxide ohmic contact for high-brightness GaN-based light-emitting diodes using a Sn–Ag interlayer

We report on the formation of low-resistance and highly transparent indium tin oxide (ITO) ohmic contacts to p-GaN using a Sn–Ag alloy interlayer. Although the as-deposited Sn–Ag(6 nm)/ITO(200 nm) contacts show non-ohmic behaviors, the scheme becomes ohmic with specific contact resistance of 4.72×10⁻⁴ Ω cm² and produce transmittance of ∼91% at wavelength of 460 nm when annealed at 530 °C. Blue light-emitting diodes (LEDs) fabricated with the Sn–Ag/ITO contacts give forward-bias voltage of 3.31 V at injection current of 20 mA. LEDs with the Sn–Ag/ITO contacts show the improvement of the output power by 62% (at 20 mA) compared with LEDs with Ni/Au contacts.     

Vertically aligned ZnO nanowires prepared by thermal oxidation of RF magnetron sputtered metallic zinc films

ZnO nanowires have been successfully grown by thermal oxidation of metallic zinc films at 430 °C. Polycrystalline zinc films were deposited on Si (100) substrates by RF magnetron sputtering utilizing discharge power from 70 to 180 W. Experimental results show that 70 W discharge power results in the formation of porous zinc nanoparticles that prevent zinc atom from diffusion and thus does not result in the formation of ZnO nanowires by subsequent thermal oxidation. By increasing discharge power to 120 W the zinc film transforms to Zone II with a columnar structure, while further increase in discharge power to 180 W results in re-crystallization and formation of micron-sized hexagonal structures on the surface. Vertically aligned ZnO nanowires can only be obtained by thermal oxidation of columnar zinc films that exhibit a field emission threshold of 5.3 V/μm (at a current density of 10 μA/cm²) with a field enhancement factor of 1834. A target current density of 0.75 mA/cm² is achieved with a bias field less than 10 V/μm.     

Growth enhancement and field emission characteristics of one-dimensional 3,4,9,10-perylenetetracarboxylic dianhydride nanostructures on pillared titanium substrate

We have utilized the π–π interactions between 3,4,9,10-perylenetetracarboxylic dianhydride (PTCDA) molecules and temperature-induced morphology changes to synthesize one-dimensional (1D) nanostructures of PTCDA on a heated (ca. 100 °C) titanium substrate through vacuum sublimation. Because of the pillared Ti structures and the presence of reactive Ti–Cl sites, the titanium substrate played a crucial role in assisting the PTCDA molecules to form 1D nanostructures. The average diameter of the nanofibers deposited on the Ti-CVD substrate, a Ti substrate formed by chemical vapor deposition (CVD), at 100 °C was ca. 84 nm, with lengths ranging from 100 nm to 3 μm. When the PTCDA nanofibers were biased under vacuum, the emission current remained stable. The turn-on electric field for producing a current density of 10 μA/cm² was 8 V/μm. The maximum emission current density was 1.3 mA/cm², measured at 1100 V (E = 11 V/μm). From the slope of the straight line obtained after plotting ln(J/E²) versus 1/E, we calculated the field enhancement factor β to be ca. 989. These results demonstrate the PTCDA nanofibers have great potential for applicability in organic electron-emitting devices.