Quantitative evaluation of proximity effect in raster-scan exposure system for electron-beam lithography

The proximity effect in a raster-scan for electron-beam lithography system was evaluated by Monte Carlo calculation and verified by experiments. It was revealed that the reduction in the beam diameter below the scanning pitch, which links into the shortening of drawing time, is more effective in decreasing the proximity effect than the reduction in the resist thickness. From the calculated results, it was found that the error in linewidth definition due to the proximity effect was less than 10 percent at a linewidth of 1.5 µm with scanning pitch of 0.5 µm, beam diameter of 0.2 µm, and PMMA resist of 1.0-µm thickness.     

电子束光刻中邻近效应校正的几种方法

本文简要介绍了限制电子束光刻分辨率的主要因素之一-邻近效应的产生机制,列举了校正邻近效应的GHOST法、图形区密集度分布法和掩模图形形状改变法,介绍了每种方法的原理、步骤和效果,比较了它们各自的优缺点.     

Line width control in electron-beam lithography

A method for predicting line widths in electron beam lithography is described. Computer predictions of line dimension as a function of dose, and profile as a function of proximity to another line are compared with experimental results on 0.35?m thick PMMA at a beam energy of 15 keV.     

图形改正方法在邻近效应修正中的应用

本文利用双高斯形式的邻近函数来表达电子束在抗蚀剂中能量的分布,并以邻近函数为基础计算一些简单图形在曝光时所需的尺寸改变量.通过与实验的比较来说明该方法的可靠性,并对所得结果进行讨论和分析.     

Fabrication of curved structures by electron-beam lithography

The suitability of electron-beam lithography for the fabrication of curved structures, of interest for integrated optical devices, can be limited by the available pattern data formats. Extensions to the input format of a Cambridge Instruments electron-beam microfabricator are reported, which have allowed complex patterns to be easily specified for both mask making and direct writing.     

New method of registration for electron-beam lithography

A method of pattern registration for use in electron-beam lithography is described in the letter. The beam energy is reduced by a retarding field during the location of a pattern position, and the resist is unexposed. Patterns may be joined without any registration marks.     

Simulation of proximity and contact lithography

A simulation method based on scalar diffraction analysis of proximity and contact lithography is presented and compared with rigorous electromagnetic calculations in terms of accuracy and computation cost. It is shown that the error of the diffraction method is tolerable for standard lithography processes. Several examples demonstrate the integration of the new method in a typical lithographic process flow.     

Proximity-effect correction for VLSI patterns in electron-beam lithography

A proximity-effect correction method for VLSI patterns has been developed. In this method, a dose ratio has been introduced as a control parameter for the negative- resist thickness after development, in addition to the proximity parameters.A new technique has been used to obtain the proximity parameters. By using the dose ratio and the proximity parameters, both the exposure dose and the size of the irradiated shape are easily determined.A pattern accuracy of ±0.1 μm and a uniform resist of the desired thickness were obtained. The computation time is proportional to 1.2 power of pattern density, and is 100 seconds on a 1.5-MIPS computer when correcting for 10⁴ shapes in a pattern whose pattern density is 10⁴.     

Analysis of pattern-dependent image placement of single-membrane stencil masks for electron-beam lithography

Large single-membrane stencil masks have been developed for electron-beam lithography. Since a large membrane induces large image placement (IP) error, which is pattern dependent, a method of correcting EB data has been studied to compensate the membrane distortion. In this study, firstly, the effect of crystal anisotropy of a Si membrane to the distortion is examined by making masks from blanks with different orientations. The influence of the anisotropy is found to be small and simulation based on isotropic modeling should be applicable. Secondly, a finite element method (FEM) called ANSYS and Pseudo-FEM are used to predict distortions for three masks with 8 mm-, 12 mm-, or 18 mm-square die of an opening ratio of 0.2 on a 24 mm-square membrane. The simulation results are compared with the results obtained in the experiment on anisotropy and a previous experiment. Qualitative agreement is observed between simulation and experiment but quantitative agreement is obtained only after introduction of adjustment factors. A suggestion is made to improve the IP correction scheme for EB data.     

Double-layer resist films for submicrometer electron-beam lithography

This paper describes a double-layer resist-film technique for submicrometer electron-beam lithography. The results of computer simulation and lithography experiments carried out on PMMA/MPR (LO/HI) and MPR/PMMA (HI/LO) double-layer films are reported in full detail. It is shown that an undercut profile suitable for the lift-off processing can be reproducibly obtained by the use of the LO/HI structure over a wide range of electron-beam exposure dose, while the HI/LO structure is of great advantage in the fabrication of lift-off metal gates with a mushroom-like cross section.     

Fabrication of ordered GaAs nanowhiskers using electron-beam lithography

The formation of ordered GaAs nanowhiskers obtained on GaAs (111)As substrates using electron-beam lithography and catalytic molecular-beam epitaxy (MBE) growth is studied experimentally. The main parameters of the e-beam lithographic process necessary for obtaining Au catalyst droplets 10–150 nm in size are determined. It is established that subsequent MBE growth proceeds predominantly by the diffusion mechanism. In the regions subjected to a repeated e-beam exposure after the lift-off process, suppression of nanowhisker growth can take place.     

Enhanced proximity-effect correction for VLSI patterns in electron-beam lithography

When applying a proximity-effect correction to VLSI patterning, the major challenge is to obtain a highly accurate pattern without excessive computation. A fast correction program that has two new techniques for the proximity effect has been developed for highly accurate VLSI patterning on a negative resist. The first technique is the effective definition of sample points where energy intensity is calculated to obtain a highly accurate pattern. The second is the use of the exposure-intensity reduction rate which corresponds to a change in the pattern dimensions to reduce the computation time. A pattern accuracy of ±0.1 µm and a uniform resist of the desired thickness were obtained. The computation time is proportional to the 1.2 power of pattern density.     

接近式光刻的计算机模拟研究

分析了菲涅耳近似模型在接近式光刻模拟中的应用和误差起源,并根据光的标量衍射理论,对菲涅耳近似模型进行了修正,得到了更加准确的类菲涅耳近似模型;并对这两种模型的模拟结果进行了比较。     

接近式光刻的计算机模拟研究

分析了菲涅耳近似模型在接近式光刻模拟中的应用和误差起源 ,并根据光的标量衍射理论 ,对菲涅耳近似模型进行了修正 ,得到了更加准确的类菲涅耳近似模型 ;并对这两种模型的模拟结果进行了比较     

MOS and bipolar VLSI technologies using electron-beam lithography

Key issues for micrometer and submicrometer MOS and bipolar device fabrication are discussed, including lithography, device and circuit scaling limitations, and process considerations. Lithographic requirements are presented in terms of an overall technology-machine, resist and pattern transfer methods-and an electron-beam alice writing technology is described which satisfies those needs. Viable micrometer and submicrometer MOS and bipolar process technologies are demonstrated by scaling complex LSI circuits to VLSI density using electron lithography. For the MOS case, scaling of static memories is discussed in detail, including fabrication of a 4K SRAM with 1.5-µm minimum feature sizes, 12-15-ns access times, and a chip size of only 6K mil². A discussion of bipolar device and process scaling issues is highlighted by the successful fabrication of a scaled 16-bit integrated injection logic (I²L) microprocessor with 1.25-µm minimum feature sizes and a clock frequency of 10 MHz with a chip current of only 250 mA.     

Lower submicron pattern definition by high-voltage electron-beam lithography

High-voltage electron-beam writing on polymethyl methacrylate (PMMA) at 50 kV with a dose of 50 ?C/cm2 has been found to give an outstanding result of the simultaneous formation of isolated and arrayed quarter-micron window patterns of the same size as the electron-beam diameter of a quarter micron.     

Masked ion beam lithography for proximity printing

Optical and X-Ray proximity printing systems are resolution limited by diffraction and beam dispersion. Parallel dispersion free ion beam systems are therefore ideal to transfer stencil mask patterns onto all sorts of nonideal substrates. A feasibility study was performed with the existing Alpha ion projector of the Society for the Advancements of Microelectronics in Austria operated in the MIBL (Masked Ion Beam Lithography) mode with ≈ 10×10 mm² exposure field. Structures as small as 0.2 μm in diameter could be transfered even with a gap of 1 mm between stencil mask and substrate. The widening of resist lines with 10% increase in dose was evaluated to be 14 nm for 2800 μm gap and 4 nm for 300 μm gap. This excellent exposure latitude favourably compares with synchrotron based X-ray lithography, where a widening of 20 nm with 10% overexposure has been reported for a 40 μm gap, and 10 nm for 10 μm gap. Promising applications of the MIBL technique include the fabrication of flat panel displays based on vacuum electronics (field emitter displays), surface acoustic wave and microoptic devices and - in combination with reactive ion etching - the fabrication of micro electro mechanical systems (MEMS). Prospects for MIBL steppers of printing fields > 100×100 mm² are discussed.     

Dose control circuit for digital electrostatic electron-beam array lithography

This paper demonstrates a technique for controlling the electron emission of an array of field emitting vertically aligned carbon nanofibers (VACNFs). An array of carbon nanofibers (CNF) is to be used as the source of electron beams for lithography purposes. This tool is intended to replace the mask in the conventional photolithography process by controlling their charge emission using the “Dose Control Circuitry” (DCC). The large variation in the charge emitted between CNFs grown in identical conditions forced the controller design to be based on fixed dose rather than on fixed time. Compact digital control logic has been designed for controlling the operation of DCC. This system has been implemented in a 0.5 μm CMOS process. Chandra Sekhar A. Durisety received his B.E. (Hons.) Instrumentation from Birla Institute of Technology and Sciences, Pilani, India in 1997 and his M.S in Electrical Engineering from University of Tennessee, Knoxville in 2002. Since 2003, he has been working towards his Ph.D degree also in Electrical Engineering at Integrated Circuits and Systems Lab (ICASL), University of Tennessee, Knoxville. He joined Wipro Infotech Ltd, Global R & D, Bangalore, India in 1997, where he designed FPGA based IPs for network routers. Since 1999, he was involved in the PCI bridge implementation at CMOS chips Inc, Santa Clara, CA, and the test bench development for Sony’s MP3 player, while at Toshiba America Electronic Components Inc., San Jose, CA. His research interests include multi-stage amplifiers, data converters, circuits in SOI and Floating Gate Devices. Rajagopal Vijayaraghavan received the B.E degree in electronics and communication engineering from Madras University in 1998 and the M.S degree in electrical engineering from the University of Texas, Dallas in 2001.He is currently working towards the Ph.D degree in electrical engineering at the University of Tennessee. His research interest is in the area of CMOS Analog and RF IC design. His current research focuses on LNAs and VCOs using SOI based MESFET devices. Lakshmipriya Seshan was born in Trivandrum, India on April 30, 1979. She received her B.tech in Electronincs & Communication Engg from Kerala University, India in June 2000 and M.S in Electrical Engg from University of Tennessee in 2004. In 2004, she joined Intel Corporation as an Analog Engineer, where she is engaged in the design of low power, high speed analog circuits for various I/O interface topologies. Syed K. Islam received his B.Sc. in Electrical and Electronic Engineering from Bangladesh University of Engineering and Technology (BUET) and M.S. and Ph.D. in Electrical and Systems Engineering from the University of Connecticut. He is presently an Associate Professor in the Department of Electrical and Computer Engineering at the University of Tennessee, Knoxville. Dr. Islam is leading the research efforts of the Analog VLSI and Devices Laboratory at the University of Tennessee. His research interests are design, modeling and fabrication of microelectronic/optoelectronic devices, molecular scale electronics and nanotechnology, biomicroelectronics and monolithic sensors. Dr. Islam has numerous publications in technical journals and conference proceedings in the areas of semiconductors devices and circuits. Benjamin J. Blalock received his B.S. degree in electrical engineering from The University of Tennessee, Knoxville, in 1991 and the M.S. and Ph.D. degrees, also in electrical engineering, from the Georgia Institute of Technology, Atlanta, in 1993 and 1996 respectively. He is currently an Assistant Professor in the Department of Electrical and Computer Engineering at The University of Tennessee where he directs the Integrated Circuits and Systems Laboratory (ICASL). His research focus there includes analog IC design for extreme environments (both wide temperature and radiation immune), multi-gate transistors and circuits on SOI, body-driven circuit techniques for ultra low-voltage analog, mixed-signal/mixed-voltage circuit design for systems-on-a-chip, and bio-microelectronics. Dr. Blalock has co-authored over 60 published refereed papers. He has also worked as an analog IC design consultant for Cypress Semiconductor Corp. and Concorde Microsystems Inc.     

Experiment-based estimation of point spread function in electron-beam lithography: Forward-scattering part

The point spread function (PSF) plays an important role in electron beam (e-beam) lithography, e.g., estimation of resist profile, proximity effect correction, etc. One of the essential tasks is how to estimate the PSF with accuracy and efficiency. Conventional approaches include estimation of PSF’s based on certain functions or through a Monte Carlo simulation. A new approach to estimating PSF’s based on experimental data is proposed to provide an alternative to the conventional approaches. It utilizes the relationship between a PSF and a line spread function (LSF), and that between a LSF and the remaining resist profile. Since effects of all phenomena and processes involved in the exposure step are reflected in experimental results, the proposed approach has a good potential to generate realistic PSF’s for any substrates and e-beam tools as long as experiments can be carried out. In this paper, the implementation of the new approach for estimation of the forward scattering part of PSF is described along with the simulation and experiment results.     

Impact of proximity correction on device yield in electron-beam definition of MSM-detectors

The influence of proximity correction on device yield and process latitude in electron-beam fabrication of short-period metal-semiconductor-metal (MSM) photodetectors is investigated. A modified Fourier-transform deconvolution method is used for proximity correction. Scattering data is obtained from Monte Carlo simulation, without the need for costly experimental parameter determination. Proximity correction leads to a significant improvement in device yield and process latitude. Figures of merit for latitude enhancement typically are in the range 2…10, depending on device geometry and process context. For a field-effect transistor compatible process technology, MSM devices with finger periods down to 200 nm can be realized using proximity corrected exposure.