Characterization of scaled MANOS nonvolatile semiconductor memory (NVSM) devices

We have modeled and characterized scaled Metal–Al₂O₃–Nitride–Oxide–Silicon (MANOS) nonvolatile semiconductor memory (NVSM) devices. The MANOS NVSM transistors are fabricated with a high-K (K_A = 9) blocking insulator of ALD deposited Al₂O₃ (8 nm), a LPCVD silicon nitride film (8 nm) for charge-storage, and a thermally grown tunneling oxide (2.2 nm). A low voltage program (+8 V, 30 μs) and erase (?8 V, 100 ms) provides an initial memory window of 2.7 V and a 1.4 V window at 10 years for an extracted nitride trap density of 6 × 10¹⁸ traps/cm³ eV. The devices show excellent endurance with no memory window degradation to 10⁶ write/erase cycles. We have developed a pulse response model of write/erase operations for SONOS-type NVSMs. In this model, we consider the major charge transport mechanisms are band-to-band tunneling and/or trap-assisted tunneling. Electron injection from the inversion layer is treated as the dominant carrier injection for the write operation, while hole injection from the substrate and electron injection from the gate electrode are employed in the erase operation. Meanwhile, electron back tunneling is needed to explain the erase slope of the MANOS devices at low erase voltage operation. Using a numerical method, the pulse response of the threshold voltages is simulated in good agreement with experimental data. In addition, we apply this model to advanced commercial TANOS devices.     

A nonvolatile semiconductor memory device in 6H-SiC for harsh environment applications

An electrically erasable programmable read-only memory (EEPROM) cell fabricated on a 6H-SiC substrate is reported. It is the first fully functional SiC EEPROM device. This device uses a generic double-polysilicon-gate configuration. It has been tested at both room temperature and elevated temperatures, up to 200/spl deg/C, to demonstrate full programmability. The threshold voltage shifts between programmed and erased states, at all tested temperatures, are larger than 4.5 V. In both states, the device functions satisfactorily as an n-type MOSFET. Charge retention time is more than 24 h at room temperature.     

低温工艺硅量子点多晶硅TFT非易失性存储器

This paper reports on a successful demonstration of poly-Si TFT nonvolatile memory with a much reduced thermal-budget.The TFT uses uniform Si quantum-dots(size ¹0 nm and density ¹0¹¹ cm^-2) as storage media,obtained via LPCVD by flashing SiH₄/H₂ at 580℃for 15 s on a Si₃N₄ surface.The poly-Si grain-enlargement step was shifted after source/drain formation.The NiSi_x-silicided source/drain enables a fast lateral-recrystallization,and thus grain-enlargement can be accomplished by a much reduced thermal-cycle（i.e., 550℃/4 h）.The excellent memory characteristics suggest that the proposed poly-Si TFT Si quantum-dot memory and associated processes are promising for use in wider TFT applications,such as system-on-glass.     

Electrically reprogrammable nonvolatile semiconductor memory

Electrically reprogrammable nonvolatile memories using avalanche injection of electrons and holes into a floating gate are described. The fabrication data and the results of measurement on fabricated devices are shown. Analyses of the operation of the memory cell are done using conventional MOS transistors. The injection of current into silicon dioxide, its ratio to avalanche current, the WRITE speed, the basic data for analog memory, and the drift of the characteristics are measured and discussed.     

A semiconductor nonvolatile electron beam accessed mass memory

BEAMOS-beam addressed metal-oxide-semiconductor is a new technology for fast auxiliary memories which is expected to find important applications in military and commercial data systems. The concept is based on electron beam accessing, using a matrix lens, of a simple MOS memory chip. It has performance features which include large bit capacity per module (> 30 × 10⁶bits), short access time ( 10 Mbit/s), and low cost. The BEAMOS module is all electronic, rugged, and relatively insensitive to variations in temperature, making it especially attractive for military computer applications. The operating principles of the BEAMOS memory and its present state of development are described.     

A nonvolatile charge-addressed memory (NOVCAM) cell

A nonvolatile charge-addressed memory (NOVCAM) cell is described in a 64-bit shift register configuration. The charge address is performed by a charge-coupled device (CCD) shift register and the information is stored in metal-nitride-oxide-silicon (MNOS) nonvolatile sites located in parallel with the CCD shift register. The tunneling electric field strength across the thin-oxide MNOS structure is controlled by the magnitude of the charge transferred from the CCD register. The write, erase, and read modes of operation are discussed with typical /spl plusmn/20 V 10 /spl mu/s write/erase, and 2 V 2 /spl mu/s read conditions. Readout is accomplished by parallel stabilized charge injection from a diffused p/n junction to minimize access time to the first bit.     

Electrically erasable nonvolatile optical MNOS memory device

A new type of nonvolatile optical memory device composed of a MNOS FET with a photosensitive region is proposed. Based upon charge transport induced by voltage change across a double insulator layer under illumination, the present device can be operated in a broad wavelength spectrum from the infrared to the visible region when provided with a d.c. bias voltage. It is found that the charge transport is a function of the exposure time as well as of the intensity of the incident light. An operation mechanism is proposed based upon the experimental results.     

DIFMOS—A floating-gate electrically erasable nonvolatile semiconductor memory technology

Electrically alterable read-only memories (EAROM's) or reprogrammable read-only memories (RPROM's) can be fabricated using a single-level metal-gate p-channel MOS technology with all conventional processing steps. Given the acronym DIFMOS for dual-injector floating-gate MOS, this technology utilizes the floating-gate technique for nonvolatile storage of data. Avalanche injection of hot electrons through gate oxide from a special injector diode in each bit is used to charge the floating gates. A second injector structure included in each bit permits discharge of the floating gate by avalanche injection of holes through gate oxide. The overall design of the DIFMOS bit is dictated by the physical considerations required for each of the avalanche injector types. The end result is a circuit technology which can provide fully decoded bit-erasable EAROM-type circuits using conventional manufacturing techniques.     

FCAT—A low-voltage high-speed alterable n-channel nonvolatile memory device

The structure and principles of a new nonvolatile charge storage device are described. The Floating Si-gate Channel Corner Avalanche Transition (FCAT) memory device is an n-channel MOS transistor with a floating gate. The p⁺regions are placed outside the channel area by aligning them with the floating gate and are adjacent to the diffused n⁺source and/or drain regions. This device can operate in the write/erase modes under low-voltage (12 V) and high-speed (< 1 ms) conditions using only a pair of positive pulses. This is achieved with a novel avalanche transition at the channel corner through a relatively thin (4-6 nm thick) oxide under the open-drain condition.     

A novel P-channel nitride-trapping nonvolatile memory device with excellent reliability properties

A novel P-channel nitride trapping nonvolatile memory device is studied. The device uses a P/sup +/-poly gate to reduce gate injection during channel erase, and a relatively thick tunnel oxide (>5 nm) to prevent charge loss. The programming is carried out by low-power band-to-band tunneling induced hot-electron (BTBTHE) injection. For the erase, self-convergent channel erase is used to expel the electrons out of nitride. Experimental results show that this p-channel device is immune to read disturb due to the large potential barrier for hole tunneling. Excellent P/E cycling endurance and retention properties are demonstrated. This p-channel device shows potential for high-density NAND-type array application with high-programming throughput (>10 Mb/sec).     

Reliability issues of double gate dielectric stacks based on hafnium dioxide (HfO2) layers for non-volatile semiconductor memory (NVSM) applications

In this study, we present selected reliability issues of double gate dielectric stacks for non-volatile semiconductor memory (NVSM) applications. Fabricated gate structures were consisted of PECVD silicon oxynitride layer (SiO_xN_y) as the pedestal layer and hafnium dioxide layer (HfO₂) as the top gate dielectric. In the course of this work, obtained MIS structures were investigated by means of current–voltage characteristics, as well as applying dc stresses in constant current (CCS) and voltage (CVS) mode. Presented results have shown that the application of ultra-thin PECVD silicon oxynitride layer results in significant increase of breakdown voltage value in comparison to MIS structure with only hafnia as the gate dielectric. Moreover, due to the high temperature annealing of deposited SiO_xN_y layers, MIS device demonstrates much lower leakage currents, as well as higher breakdown voltage values in comparison to device with ‘as-deposited’ SiO_xN_y bottom layer. The results also proved larger immunity to dc stresses and better retention characteristics of MIS devices with ‘annealed’ oxynitride, in comparison to ‘as-deposited’ pedestal layer.     

A nonvolatile memory circuit-a novel approach

A nonvolatile memory circuit using conventionally available components (transistors and magnetic switching cores) operates on the principle of the two distinct impedance levels of a switching core in the irreversible and reversible regions. It has the property of nondestructive read-out and requires no sensing amplifiers. It is believed that the circuit is useful for systems that require low memory capacity, such as from a few bits to a hundred of bits of information.     

Organic nonvolatile memory devices utilizing intrinsic charge-trapping phenomena in an n-type polymer semiconductor

Charge trapping is an undesirable phenomenon and a common challenge in the operation of n-channel organic field-effect transistors. Herein, we exploit charge trapping in an n-type semiconducting poly (naphthalene diimide-alt-biselenophene) (PNDIBS) as the key operational mechanism to develop high performance, nonvolatile, electronic memory devices. The PNDIBS-based field-effect transistor memory devices were programmed at 60 V and they showed excellent charge-trapping and de-trapping characteristics, which could be cycled more than 200 times with a current ratio of 10³ between the two binary states. Programmed data could be retained for 10³ s with a memory window of 28 V. This is a record performance for n-channel organic transistor with inherent charge-trapping capability without using external charge trapping agents. However, the memory device performance was greatly reduced, as expected, when the n-type polymer semiconductor was end-capped with phenyl groups to reduce the trap density. These results show that the trap density of n-type semiconducting polymers could be engineered to control the inherent charge-trapping capability and device performance for developing high-performance low-cost memory devices.     

High-k polymer dielectrics with different cross-linked networks for nonvolatile transistor memory device

Nonvolatile OFET memory devices using different pPFPA/bPEI cross-linked polymers as the dielectric layer are fabricated. The influence of bPEI content on the electrical property and memory performance of devices are systematically investigated. The results demonstrate that the introduction of bPEI into pPFPA can significantly enhance the capacitance and dielectric constant of the pPFPA/bPEI cross-linked polymer dielectrics, but it also causes a slight increase in the leakage current density. Besides, the excess bPEI induces more morphology defects of the semiconductor film, leading to an apparent decrement in charge mobility. Transistors with the 119:250 pPFPA/bPEI dielectric layer exhibit the highest on/off current ratio (~10⁷ at V_g = − 20V) and a relatively low hole mobility of 0.38 cm² V⁻¹s⁻¹. Moreover, the corresponding memory devices show good reliability in information record with a data retention time over 10⁵ s, indicating that an appropriate amount of bPEI is crucial for improving the stability of the memory devices.     

Operation model of floating-Si-gate channel-corner-avalanche-transition (FCAT) nonvolatile memory devices

A write/erase model is described for FCAT nonvolatile memory devices which perform write/erase operations with 10–20 V pulses of less than 100-1 μs duration. The amplitude of the threshold voltage shift is analyzed as a function of the source and gate pulse amplitudes using a sample equivalent source circuit. The high level saturated threshold voltage, V_TH, obtained by electron injection into the floating gate and the low level saturated threshold voltage, V_TL, due to hole injection are shown to be linear functions of V_G and V_S, and the analysis agrees well with experimental results. The influence of series resistance, including substrate resistance, in the source circuit is also discussed.     

A 16-kbit nonvolatile charge addressed memory

A 16-kbit nonvolatile charge addressed memory (NOVCAM) is described. A unique cell design allows a high-density memory array layout without reduced line widths or spacings. A cell size of 0.5 square mils is produced by a seven mask process with 6-/spl mu/m polysilicon gates, 10-/spl mu/m aluminum gates, and 10-/spl mu/m minimum spacing on all mask levels. Charge addressed write and read operations are implemented with a very simple interface between the memory array and a two-phase dynamic shift register. The memory is organized as 256 columns by 64 rows. Two 64-bit shift registers provide data access to the memory array via a 2:1 column decoder. With single polysilicon processing the memory array is 50/spl times/161 mils; the 16-kbit chip is 131/spl times/200 mils.     

A new phase in nonvolatile memory?

This paper describes recent advances in techniques to develop phase-change memories. These include a new way to facilitate low-voltage phase changes with the use of a tiny strip of amorphous semiconductor compound of germanium, antimony, and tellurium on a layer of silicon dioxide, which is connected to lateral contacts connected to current sources. This configuration allows better control of heat dissipation and use of smaller voltages to change phase. Another development is a device made with a phase-change material based on antimony-tellurium material doped with one or more of the elements of germanium, indium, silver or gallium. This doped material changes phase significantly faster than the germanium-antimony-tellurium compounds in other experiments. Efforts are also underway to create arrays containing memory cells.     

A novel high voltage lateral double diffused metal oxide semiconductor (LDMOS) device with a U-shaped buried oxide feature

A novel U-shape buried oxide lateral double diffused metal oxide semiconductor (LDMOS) is reported in this paper. The proposed structure features ionized charges in both sides of dielectric between source and gate region to enhance the breakdown voltage. The dielectric between drain and drift region affects on the breakdown voltage by adding a new peak in the electric field profile. Two dimensional simulation with a commercial software tool predicts significantly improved performance of the proposed device as compared to conventional LDMOS structures.     

Organic low voltage rewritable memory device based on PEDOT:PSS/f-MWCNTs thin film

We report on devices constructed using a small quantity (?0.01 wt.%) of functionalized multiwalled carbon nanotubes (f-MWCNTs) embedded in a conducting polymer (poly(3,4-ethylenedioxythiophene):poly(styrenesulfonate), PEDOT:PSS) matrix and aluminum top electrodes, prepared on indium-tin-oxide (ITO) substrates. Our ITO/(PEDOT:PSS + f-MWCNTs)/Al devices show current bistability. The low resistance ON-state, as well as the high resistance OFF state, retain the information for hours and are stable after hundreds of write–read–erase–read (WRER) cycles, being potentially interesting for erasable and rewritable volatile memory device applications. Moreover, the operation voltages used for performing these WRER cycles are very low. The threshold voltage for OFF to ON switching can be adjusted changing the f-MWCNTs concentration. Our results suggest that the nanotubes are necessary for the production of an inhomogeneous electric field playing a role in the electroforming (dielectric breakdown) of the aluminum oxide layer at the Al₂O₃/(PEDOT:PSS) interface.     

Platinum-induced hysteresis and nonvolatile memory properties in MOS systems (PLATMOS)

The effect of diffused platinum on MOS structures has been studied using high-frequency capacitance-voltage techniques. The materials used were and oriented p-type silicon substrates of 3-5-Ω.cm resistivity. All the platinum diffusions were performed at 1000°C in a dry nitrogen ambient for various times between 10 and 300 min. Experimental results are presented which show that platinum diffusion produces hysteresis effects in the MOS system which have not previously been observed. The hysteresis is found to be very strongly dependent on diffusion time and crystal orientation, being much more pronounced in wafers than . All the experimental observations point to this phenomenon being associated with some bias-dependent charge storage at the oxide-silicon interface or mobile platinum ions in the oxide. The precise nature of the charge-storage mechanism is not completely understood; however, the platinum-induced hysteresis raises the possibility of being used as a memory element due to its nonvolatile property.