High-performance InGaAs junction field-effect transistor with P/Beco-implanted gate

InGaAs junction field-effect transistors (JFETs) are fabricated in metalorganic chemical-vapor-deposition (MOCVD)-grown n-InGaAs and semi-insulating Fe:InP layers on n⁺-InP substrate with a P/Be co-implanted p⁺ self-aligned gate. The device exhibits a transconductance of 245 mS/mm (intrinsic transconductance of 275 mS/mm) at zero gate bias and good pinch-off behavior for a gate length of 0.5 μm. The effective electron velocity is deduced to be 2.8×10⁷ cm/s, equal to the theoretical prediction     

GaAs LSI-directed MESFET's with self-aligned implantation for n+-layer technology (SAINT)

Self-aligned implantation for n⁺-layer technology (SAINT) has been developed for improvement in normally-off GaAs MESFET's to be used in LSI's. This technology has made it possible to arbitrarily control the spacing between the n⁺-implanted layer and gate contact by a dielectric lift-off process utilizing a multilayer resist with an undercut wall shape. SAINT FET's with a 1-µm gate length have above 200 mS/ mm transconductance in the normally-off region. The K value along the square-lawI - Vfitting has been improved by a factor of 3.4, compared to conventional FET's without the n⁺-layer. Thermal emission for carriers from the source n⁺-layer in the subthreshold region has been experimentally formulated. Threshold-voltage shift due to gate shortening for [011] gate FET's is definitely smaller than that for [011] gate FET's. The threshold-voltage standard deviations for [011] gate FET's with 2- and 1-µm gate lengths, obtained from a 6-mm × 9-mm area, are 9 and 34 mV, respectively. An E/D direct-coupled FET logics (DCFL) 15-stage ring oscillator with a 1-µm gate length shows a high switching speed of 45 ps/gate at a low supply voltage of 0.91 V.     

Subquarter-micrometer gate-length p-channel and n-channel MOSFETswith extremely shallow source-drain junctions

The fabrication of p-channel and n-channel MOSFETs with sub-quarter-micrometer n⁺ polysilicon gates, have been fabricated using extremely shallow source-drain (S-D) junctions, is reported p⁺-n junctions as shallow as 80 nm have been fabricated using preamorphization low-energy BF₂ ion implantation and rapid thermal annealing, and 80-nm n⁺-p junctions have been fabricated using low-energy arsenic ion implantation and rapid thermal annealing. n-channel MOSFETs with 80-mm S-D junctions and 0.16-μm gate lengths have been fabricated, and a maximum transconductance of 400 mS/mm has been obtained. 51-stage n-channel enhancement-mode/enhancement-mode (E/E) ring oscillators and p-channel E/E ring oscillators with extremely shallow S-D junctions have also been obtained     

Self-aligned In0.53Ga0.47As/semi-insulating/n+InP junction field-effect transistors

Depletion-mode junction field-effect transistors (JFET's) with InGaAs p-n junctions grown on compensated Fe:InP or highly resistive In0.52Al0.48As isolation layers grown on n⁺-InP substrates have been fabricated using a combination of molecular-beam epitaxy and metalorganic chemical vapor deposition growth techniques. Using a self-aligned gate technology with a 1-µm gate length, devices with high transconductance (80 mS/mm), low leakage current (<100 nA), and a gate-to-source capacitance of 0.4 pF have been fabricated. This is apparently the first report where InP-based alloy FET's have been fabricated on an isolated n⁺-substrate. This structure has application to monolithically integrated photoreceivers.     

Reduction of the short-channel effects for GaAs MESFETs by doubleshallow n+-layers

In order to suppress the short-channel effects of subquarter-micrometer gate-length GaAs MESFETs, it is necessary to fabricate shallow n⁺ layers without any increase of parasitic resistance. To advance this line of research, a double shallow n⁺ -layer structure was investigated using a T-shaped resist mask and oblique ion implantation. Employing this shallow n⁺-layer structure, the threshold-voltage shift was suppressed and the subthreshold characteristics were improved for subquarter-micrometer gate-length FETs. A transconductance of 500 mS/mm for the 0.15-μm gate-length FET and a cutoff frequency of 33 GHz for the 0.35-μm gate-length FET were obtained     

Planar, fully ion-implanted InP junction FETs with anitride-registered gate metallization

A planar, fully ion-implanted indium phosphide (InP) junction FET (JFET) fabrication process is described, which utilizes n⁺ source-drain implantation, Be and Be/P p⁺ gate implantation, AuZn/Ni/TiW/Au nitride-registered gate metallization, and proximity rapid thermal annealing. Devices fabricated with this approach exhibited a maximum transconductance of 140 mS/mm, which is believed to be the highest reported for InP JFETs     

Selectively dry-etched n+-GaAs/N-InAlAs/InGaAs HEMTs forLSI

High-speed n-InAlAs/InGaAs HEMT large-scale integrated circuits must have uniform device parameters. A selectively dry-etched n⁺ -GaAs/N-InAlAs/InGaAs HEMT which has a very uniform threshold voltage is discussed. Despite the high dislocation density at the n⁺-GaAs layer, its performance is excellent. For a gate length of 0.92 μm, the maximum transconductance of the HEMT is 390 mS/mm. The measured current-gain cutoff frequency is 23.7 GHz, and the maximum frequency of oscillation is 75.0 GHz. The standard deviation of the threshold voltage across a 2-in wafer is as low as 13 mV     

High-performance In0.08Ga0.92As MESFETs onGaAs(100) substrates

In_0.08Ga_0.92As MESFETs were grown in GaAs (100) substrates by molecular beam epitaxy (MBE). The structure comprised an undoped compositionally graded In_xGa_1-x As buffer layer, an In_0.08Ga_0.92As active layer, and an n⁺-In_0.08Ga_0.92As cap layer. FETs with 50-μm width and 0.4-μm gate length were fabricated using the standard processing technique. The best device showed a maximum current density of 700 mA/mm and a transconductance of 400 mS/mm. The transconductance is extremely high for the doping level used and is comparable to that of a 0.25-μm gate GaAs MESFET with an active layer doped to 10¹⁸ cm^-3. The current-gain cutoff frequency was 36 GHz and the power-gain cutoff frequency was 65 GHz. The current gain cutoff frequency is comparable to that of a 0.25-μm gate GaAs MESFET     

Normally-off InGaAs junction field-effect transistor with InGaAs buffer layer

InGaAs junction field-effect transistors (JFET's) with 1-µm gate length were successfully fabricated with an n⁺-InGaAs active layer (8 × 10¹⁶cm^-3) and an undoped InGaAs buffer layer grown on semi-insulating InP:Fe substrate by liquid-phase epitaxy. The device showed good pinch-off behavior with a threshold voltage of 0.25 V, a low drain current of 1 µA at zero gate-source voltage, and a very high transconductance of 553 mS/mm at room temperature. This is one of the highest transconductance values ever reported for a 1-µm gate-length FET.     

A new p-channel MOSFET with large-tilt-angle implanted punchthroughstopper (LATIPS)

A buried-channel p-MOSFET with a large-tile-angle implanted punchthrough stopper (LATIPS) is described. In this device the n⁺ LATIPS region was successfully realized adjacent to the p⁺ source/drain, even without a sidewall spacer, by taking advantage of the n⁺ large-tilt-angle implant. In spite of the relatively deep p⁺ junction of 0.2-μm depth and the low n-well concentration of 1×10¹⁶ cm^-3, the 0.5-μm LATIPS device (with corresponding channel length of 0.3 μm) achieved high punchthrough resistance, e.g. a low subthreshold swing of 95 mV/decade with a high transconductance of 135 mS/mm     

An anisotype GaAs/InxGa1-xAs heterojunctionfield-effect transistor for digital logic applications

An anisotype heterojunction field-effect transistor (A-HJFET) for GaAs digital integrated circuit applications is proposed. A thin, highly doped, strained In_xGa_1-xAs (x⩽0.2) n-channel is employed for improved transconductance while a p⁺-GaAs cap is used to enhance the dynamic gate voltage range of the device. Prototype devices with 5-μm gate lengths show a maximum transconductance of 80 mS/mm at V_ds=2 V and a forward gate bias voltage of up to +2 V without significant leakage current     

0.3-μm gate length p-channel AlGaAs/InGaAs heterostructure fieldeffect transistors with high cut-off frequency

P-channel Heterostructure Field Effect Transistors (HFETs) with a 0.3-μm gate were fabricated by Mg ion implantation. The maximum transconductance was 68 mS/mm and there was no serious drain or gate leakage current, regardless of this short gate length. The gate turn on voltage (@I_gs=-1 μA/μm) was -2.1 V and its absolute value was large enough for use in complementary HFETs. S-parameters measurements showed a very high cut-off frequency of over 10 GHz. Results indicated the superiority of less-diffusive Mg ion implantation for forming p⁺-layer in p-channel HFETs     

Semiconductor-gated InGaAs/InAlAs heterostructure transistors (SISFET's)

We have successfully fabricated FET's with In0.53Ga0.47As channels, lattice-matched In0.52Al0.48As gate barriers, and n+ In0.53- Ga0.47As gates. For a barrier thickness of 600 Å and a gate length of 1.7 µm, the maximum transconductance is 250 mS/mm at T = 300 K. From gate capacitance measurements, the cutoff frequency is inferred to be ft= 15 GHz for this gate length. Self-aligned source and drain implants have been used to permit nonalloyed ohmic contacts with a characteristic resistance of 0.1 Ω.mm. The transconductance remains above 210 mS/mm for forward gate bias up to +1.0 V, confirming the usefulness of this gate structure for enhancement-mode devices.     

Model and analysis of a delta-doping field-effect transistors utilizing an InGaP/GaAs camel-gate structure

In this paper, the performances of a new δ-doping field-effect transistor utilizing an InGaP/GaAs camel-gate structure by theoretical and experimental analysis will be reported. An analytical model related to drain saturation current, transconductance, potential barrier height, gate-to-source depletion capacitance, and unit current gain frequency is developed to explain the device performances. The employments of n⁺-GaAs/p⁺-InGaP/n-GaAs heterostructure gate and the δ-doping channel with heavy-doping level were used to improve transconductance linearity and enhance current drivability. For a 1×100 μm² device, the experimental results show that a drain saturation current of 1120 mA/mm, a maximum transconductance of 240 mS/mm, and a large V_gs swing larger than 3.5 V with the transconductance higher than 200 mS/mm are obtained. In addition, the measured unit current gain frequency f_t is 22 GHz. These experimental results are consistent with theoretical analysis.     

A new self-aligned GaAs FET with a Mo/WSixT-gate

An n+-layer and ohmic electrode self-aligned (NOSA) GaAs FET is a new self-aligned GaAs FET in which n⁺-layers and ohmic contacts in the source and the drain regions are self-aligned to a T-shaped gate formed with Mo and WSix(≈0.6) double layers. Using the NOSA FET structure, the device area can be easily reduced because no alignment margin is needed. The fabricated FET's exhibit a transconductance gmof 170 mS/mm.     

An all-implanted, self-aligned, GaAs JFET with a nonalloyedW/p+-GaAs ohmic gate contact

We describe a self-aligned, refractory metal gate contact, enhancement mode, GaAs junction field effect transistor (JFET) where all impurity doping was done by ion implantation. Processing conditions are presented for realizing a high gate turn-on voltage (~1.0 V at 1 mA/mm of gate current) relative to GaAs MESFET's. The high gate turn-on voltage is the result of optimizing the p⁺-gate implant and anneal to achieve a nonalloyed ohmic contact between the implanted p⁺-GaAs and the sputter deposited tungsten gate contact. Initial nominally 1.0 μm×50 μm n-JFET's have a transconductance of 85 mS/mm and f_t of 11.4 GHz     

Submicrometer n+-Ge gate AlGaAs/GaAs MISFETs

Submicrometer n⁺-Ge gate AlGaAs/GaAs MISFETs have been developed by designing a fabrication process for the n⁺-implanted region. The short-channel effect was sufficiently suppressed by lowering the ion-implantation energy down to 50 keV to achieve a standard deviation of threshold voltage as small as 13 mV for 0.5-μm-gate FETs in a 2-in-diameter wafer. The source resistance was reduced by increasing the annealing temperature to 850°C to obtain a transconductance of 500 mS/mm for a 0.5-μm-gate FET. Even after annealing at such a high temperature, the quality of the channel layer was maintained at a sufficient level to realize a large cutoff frequency of 70 GHz for a 0.4-μm-gate FET. A divide-by-four static frequency divider was also fabricated using the above-mentioned fabrication technology. Successful operation at 16 GHz at 300 K was obtained with a divider using 0.9-μm-gate FETs at a low power dissipation of 36 mW per T-flip-flop     

Small-signal characteristics of InP Junction FET's

The small-signal scattering parameters and an equivalent circuit of InP junction field-effect transistors are presented. These transistors have a planar structure with the channel and gate regions formed by selective silicon and berylium implantation, respectively. The nominal channel thickness and doping are 0.2 µm and 10¹⁷cm^-3and the gate length is approximately 2 µm. Typical values of transconductance and IDSSare 50 mS/mm and 150 mA/mm. Scattering parameter measurements indicate an fTof 10 GHz and anf_{max}of 22 GHz. In-process microwave measurements are used to determine the device performance before final gate definition.     

Comparisons of microwave performance between single-gate anddual-gate MODFETs

Both a 1.2-μm and a 0.3-μm gate length, n⁺-GaAs/InGa/n⁺-AlGaAs double-heterojunction MODFET have been fabricated with single-gate and dual-gate control electrodes. Extrinsic DC transconductance of 500 mS/mm has been achieved from a 0.3-μm single-gate MODFET. The device also has a current gain cutoff frequency f_T of 43 GHz and 14-dB maximum stable gain at 26 GHz with the stability factor k as low as 0.6 from the microwave S-parameter measurements. At low-frequency dual-gate MODFETs demonstrate higher gain than the single-gate MODFETs. However, the k of dual-gate MODFETs approaches unity at a faster rate. Power gain roll-off slopes of 3-, 6-, and 12-dB/octave have been observed for the dual-gate MODFETs     

High-transconductance p-channel AlGaAs/GaAs HFETs with low-energyberyllium and fluorine co-implantation self-alignment

The fabrication and electrical characteristics of p-channel AlGaAs/GaAs heterostructure FETs with self-aligned p⁺ source-drain regions formed by low-energy co-implantation of Be and F are reported. The devices utilize a sidewall-assisted refractory gate process and are fabricated on an undoped AlGaAs/GaAs heterostructure grown by MOVPE. Compared with Be implantation alone, the co-implantation of F⁺ at 8 keV with 2×10¹⁴ ions/cm² results in a 3× increase in the post-anneal Be concentration near the surface for a Be⁺ implantation at 15 keV with 4×10¹⁴ ions/cm². Co-implantation permits a low source resistance to be obtained with shallow p⁺ source-drain regions. Although short-channel effects must be further reduced at small gate lengths, the electrical characteristics are otherwise excellent and show a 77-K transconductance as high as 207 mS/mm for a 0.5-μm gate length