TSOP封装脱模中硅片碎裂失效的有限元分析

针对TSOP封装在塑封工艺中脱模时可能发生的芯片碎裂,利用有限元法模拟封装脱模过程阐明了芯片碎裂失效的机制.研究表明,模具内表面有机物形成的局部沾污可能阻碍芯片的顺利脱模,导致硅片内产生较大的局部应力并碎裂失效.通过模拟在不同的沾污面积、形状和位置下的封装脱模,确认了最可能导致失效的条件.芯片碎裂失效可以通过使用高弹性模量的塑封料或减小硅片尺寸得以改善.     

虽有家财万贯 不如金卡傍身(四)——IC卡制造工艺、数据加密及其读写设备

<正> (续上篇)上篇介绍了IC卡芯片结构,本文继续对IC卡的制造工艺以及数据加密措施作一简要介绍,供读者参考。 IC卡芯片类型 IC卡芯片分为通用芯片和专用芯片两大类。通用芯片因其开发简单、价格便宜,比较适合对安全性要求不高的IC卡应用。而专用芯片是专为IC卡而设计、制造的芯片。这种芯片符合目前IC卡的ISO国际标准,具有较高的安全性。IC卡所使用的专用芯片,又分为存储器芯片和微处理器芯片两大类。存储卡使用存储器芯片作为卡芯;智能卡则使用微处理器芯片作为卡芯。IC卡经常使用的存储器芯片种类及特征见表1。     

评价IC芯片质量与可靠性的关键技术研究

对CPK、SPC和PPM三项评价IC芯片质量和可靠性的关键技术进行了研究.使用这三项技术,实际评价了芯片制造工艺中的氧化工艺.实践证明,这三项技术在工艺生产能力评估、工艺过程控制和失效分析等方面具有广阔的应用前景,特别是在工艺过程中对特殊工艺的评估.     

虽有家财万贯 不如金卡傍身(三)

<正> 上篇我们将卡大致分为磁卡、接触式IC卡和非接触式IC卡等几个大类,本篇重点介绍接触式智能IC卡基本的物理特性以及芯片性能。 基本特性 1.基本结构 接触式IC卡的基本构成是依照国际ISO7816提出的ID-1外形尺寸标准,在塑料片基上嵌入集成电路芯片而组成的卡片,示意图如图1所示。其中,电路芯片是IC卡的核心部分,一般采用0.35～0.8μm的CMOS或NMOS工艺制造的超大规模集成电路。芯片电路中,通常包括接口驱动、逻辑加密电控制、译码、存储器,甚至微处理器(CPU)等各种功能电路,示意图如图2所示,而芯片的体积控制在2mm×1mm×0.3mm以内。     

电池保护电路中MOSFET器件常见失效机理研究

受限于电子设备的内部空间,电池保护电路中MOSFET器件通常采用晶圆级芯片规模封装（WLCSP）。由于WLCSP的特点,电池保护电路中的MOSFET器件在生产、使用中会出现各种类型的失效模式和失效机理。介绍了采用WLCSP技术封装的MOSFET器件常用的分析方法与设备,结合相关的失效案例,论述了芯片开裂、芯片工艺缺陷、芯片腐蚀和过电应力这4种常见的失效机理,为MOSFET器件及其他电子元器件的失效分析和问题解决提供一定的参考。     

一种新的无触点IC卡的检测方法

无触点IC卡在制卡过程中需要经过绕线碰焊、INLAY层压、成品层压工艺,可能造成芯片EEPROM的损坏,而这种IC卡是不能读写个人化数据的.本文基于上述情况,提出了一种新的在传统的检测仪中通过增加写模块,并设计相应的检测程序来实现检测IC卡芯片存储单元的检测方法.同时该检测方式是集成在功能检测仪中,一次可检测24张标准卡片,大大提高检测效率,对提高IC卡制作质量和缩短制作周期将产生促进作用.     

由版图引起的CMOS ESD保护电路失效的分析

ESD保护电路已经成为CMOS集成电路不可或缺的组成部分,在当前CMOS IC特征尺寸进入深亚微米时代后,如何避免由ESD应力导致的保护电路的击穿已经成为CMOS IC设计过程中一个棘手的问题.光发射显微镜利用了IC芯片失效点所产生的显微红外发光现象可以对失效部位进行定位,结合版图分析以及微分析技术,如扫描电子显微镜SEM、聚焦离子束FIB等的应用可以揭示ESD保护电路的失效原因及其机理.通过对两个击穿失效的CMOS功率ICESD保护电路实际案例的分析和研究,提出了改进ESD保护电路版图设计的途径.     

芯片叠层封装的失效分析和热应力模拟

通过高温高湿加速实验对双芯片叠层封装器件的失效进行了研究,观察到存在塑封料与上层芯片、BT基板与塑封料或贴片胶的界面分层和下层芯片裂纹等失效模式.结合有限元分析对器件内热应力分布进行了计算模拟,分析了芯片裂纹的失效机理,并从材料性能和器件结构角度讨论了改善叠层封装器件可靠性的方法.     

IC卡电子锁芯片CIPH09特性及应用

1.芯片功能特性 CIPH09芯片是IC卡电子密码锁的核心,它具有密码设置、插卡检测、IC卡读写以及插卡开锁等功能.修改密码时,由键盘输入的用户密码不仅被写入密码控制器的24C01A EEPROM中,同时也写入用户手持IC卡中;开锁时,只要将手持IC卡插入IC卡座中即可将电控锁体开启,使用方便,开锁快捷,特别适合老人等记忆力差的人员使用.     

SiP组件中芯片失效机理与失效分析

由于分析手段与分析设备的限制,系统级封装（SiP）组件的芯片在失效分析的过程中带有一定的盲目性。结合故障树分析方法,以PM O S芯片失效为例,讨论了SiP组件常见的管芯失效机理：电应力失效、热应力失效、机械损伤和环境应力失效以及相应的失效现象;最后从设计和工艺角度提出了降低各种失效机理发生的改进措施。     

Mechanical and electrical properties of ultra-thin chips and flexible electronics assemblies during bending

Ultra-thin chips of less than 20 μm become flexible, allowing integration of silicon IC technology with highly flexible electronics such as food packaging sensor systems or healthcare and sport monitoring tags as wearable patches or even directly in clothing textile. The ultra-thin chips in these products will be bent to a very high curvature, which puts a large strain on the chips during use.In this paper a modified four-point bending method is presented, which is capable of measuring chip stress at high curvatures. The strength of several types of ultra-thin chips is evaluated, including standalone ultra-thin test chips and back-thinned 20 μm thick microcontrollers, as well as assemblies containing integrated ultra-thin microcontroller chips. The effect of chip thickness, bending direction and backside finish on strength and minimum bending radius is investigated using the modified four point bending method. The effect of bonding ultra-thin chips to flexible foils on the assembly strength and minimum bending radius is evaluated as well as the effect of bending on electrical properties of the bonded microcontroller dies.     

服务于IC产业的MEMS探卡

圆片级芯片测试在IC制造工艺中已经成为不可或缺的一部分,发挥着重要的作用,而测试探卡在圆片级芯片测试过程中起着关键的信号通路的作用。分析指出由于芯片管脚密度的不断增加以及在高频电路中应用的需要,传统的组装式探卡将不能适应未来的测试要求;和传统探卡的组装方法相比,MEMS技术显然更适应当今的IC技术。综述了针对MEMS探卡不同的应用前景所提出的多种技术方案,特别介绍了传感技术国家重点实验室为满足IC圆片级测试的要求,针对管脚线排布型待测器件的新型过孔互连式悬臂梁芯片和针对管脚面排布型待测器件的Ni探针阵列结构的设计和制造。     

Investigations of the influence of dicing techniques on the strength properties of thin silicon

Thin silicon offers a variety of new possibilities in microelectronical, solar and micromechanical industries, e.g. for 3D-integration (stacked dies), thin microelectromechanical packages or thin single crystalline solar cells. The wafers in this investigation were thinned back by grinding and subsequent spin etching steps for stress relief followed by separation into single test dies by sawing or etching. In order to characterize and optimize relevant process steps in terms of quality and fabrication yield, the mechanical properties were investigated considering the defect formation and strength. In this paper the influence of three different dicing technologies on the mechanical strength of thin silicon samples was investigated by 3-point bending tests. Sawing, Dicing-by-Thinning with sawn grooves and Dicing-by-Thinning with dry-etched trenches were used as dicing technologies. Analytical and numerical calculations were performed to calculate fracture stresses from fracture forces in 3-point bending tests taking into account the non-linear relationship of force and displacement during testing. Thus the fracture stress as a parameter of strength could be calculated for all tested samples. The results were statistically evaluated by the Weibull distribution based on the weakest link theory. This approach allows a more comprehensive understanding of the influence of the process on strength properties independently of geometric factors. Samples, being separated by “Dicing-by-Thinning”, have much higher strength than simply sawed samples. If trenches are fabricated by dry-etched process the strength can be increased tremendously.     

应用于柔性电子的超薄硅基芯片研究进展北大核心

柔性电子技术在近些年得到了快速发展，越来越多的柔性电子系统需要柔性、高性能的集成电路来实现数据处理和通信。通过减薄硅基芯片可以获得高性能的柔性集成电路，但是硅基芯片减薄之后的性能有可能发生变化，并且在制备、转移、封装的过程中极易产生缺陷或者破碎，导致芯片性能退化甚至失效。因此，超薄硅基芯片的制备工艺和柔性封装技术对于制备高可靠性的柔性硅基芯片十分关键。在此背景下，文章综述了柔性硅基芯片的力学和电学特性研究进展，介绍了几种超薄硅基芯片的减薄工艺和柔性封装前沿技术，并对超薄硅基芯片在柔性电子领域的应用和发展进行了总结和展望，为柔性硅基芯片技术的进一步研究提供参考。     

创新型超薄IC封装技术

圆片薄型化工艺技术的改进,以及对小型化、便携式产品的强烈的市场需求,共同推动了封装技术的创新。文中主要论述了与超薄型集成电路封装技术相关的薄型硅集成电路应用、超薄型圆片的制造、薄型化切割技术、同平面互连技术、倒装片装配及其可靠性问题。     

Fabrication of ultra-thin strained silicon on insulator

A bond and etch back technique for the fabrication of 13-nm-thick, strained silicon directly on insulator has been developed. The use of a double etch stop allows the transfer of a thin strained silicon layer with across-wafer thickness uniformity comparable to the as-grown epitaxial layers. Surface roughness of less than 1 nm was achieved. Raman analysis confirms strain remains in the thin silicon layers after the removal of the SiGe that induced the strain. Ultra-thin strained silicon-on-insulator (SSOI) substrates are promising for the fabrication of ultra-thin body and double-gate, strained Si metal-oxide semiconductor field-effect transistors (MOSFETs).     

Low-cost preparation method for exposing IC surfaces in stacked die packages by micro-abrasive blasting

An alternative method for exposing IC structures in stacked die packages is described in this paper. Conventional preparation of stacked die packages is complex and time-consuming, requiring costly equipment and experienced operators. This paper presents a method that uses the brittleness of silicon for controlled removal of silicon dies by micro-abrasive blasting. Micro-abrasive blasting affects only the top silicon die; lower dies are protected by the elastic adhesive or the die-attach tape. Dissolving the adhesive layers by chemical wet etching allows step-by-step removal of the stacked die layers. This method is fast and does not require expensive equipment.     

Dielectric integrity of thin thermal oxides on silicon

The role of silicon dioxide layers in microelectronics and the importance of their integrity are undisputable. From passivating coatings and masking layers for diffusion to ultra-thin tunneling films — all the silicon technology could not exist without silicon dioxide. This review deals with some aspects of the integrity of thin silicon dioxide films for VLSI applications. The problems of dielectric strength and wear-out are considered from the point of view of their mechanisms, models, oxide processing dependence, testing, and measuring. A brief presentation of statistical approaches commonly applied to reliability topics is also included.     

Failure analysis from the back side of a die

A back side failure analysis flow has been developed in order to enable failure analysis of flip-chip, lead-on-chip dies and within multi-metal-level dies. A combination with frontside failure analysis methods is possible too. The back side flow consists of stepwise bulk silicon removal, electrical and physical failure analysis methods. Four different methods for bulk silicon thinning in order to localize electrical defects using photoemission microscope (PEM) are compared. A method to remove the bulk silicon after PEM analysis to expose the gate oxide level of a die has been developed. Different back side applications like physical analysis of gate oxide defects, passive voltage contrast and microprobing with an atomic force microscope tip for detection of interrupts within interconnect lines are described.     

Optimization of series resistance in sub-0.2 μm SOI MOSFET's

The optimization of device series resistance in ultra-thin film SOI devices is studied through 2-D simulations and process experiments. The series resistance is dependent on the contact resistivity of the silicide to silicon and the silicide geometry. To achieve low series resistance, very thin silicides that do not fully consume the SOI film are needed. A novel cobalt salicidation technology using titanium/cobalt laminates is used to demonstrate sub-0.2 μm, thin-film SOI devices with excellent performance and very low device series resistance