一种基于路径分类的时序重构算法

讨论了FEAS算法的实现问题，对FEAS算法进行了改进，并提出一种能快速的完成同步时序电路的时序重构变换的方法。通过基于ISCAS89标准测试电路的试验数据，说明了这种算法能快速的完成同步时序电路的时序重构变换。     

基于重定时的时序逻辑优化策略

提出了一种去除同步时序电路中冗余逻辑的方法．针对时序冗余难于识别的问题,这种方法引入重定时技术,将电路中的时序冗余转换为冗余的组合逻辑,然后利用已有的比较成熟的组合逻辑优化工具将具去除．这样避免了提取电路的状态表及电路状态空间的遍历,从而能够大大降低时序电路冗余识别和支除的复杂度．将相关算法应用于ＩＳＡＳ’８９基准电路集,结果验证了其有效性。     

同步时序电路优化中的时序重构技术

本文论述了自８０年代初以来，同步时序电路优化方法中出现的时序重构技术的基本理论、方法和应用，并指出了此技术进一步实用化的几种方法。     

时序逻辑电路设计的Petri网方法

1 引言 Petri网是一种系统模拟和分析的工具,它可以揭示出被模拟系统在结构和动态行为方面信息,利用这些信息可以对被模拟系统进行性能评估并提出改进系统的建议,从而设计出一个高质量的实际应用系统。文[1,2]利用Petri网的特性分别给出了组合逻辑电路和时序电路的Petri网分析方法,其基本思想是将已设计好的逻辑电路转化成Petri网,利用Petri网的各种分析方法(可达树、状态矩阵)进行分析。时序电路的设计是分析方法的逆过程,是根据给定的状态图或通过对设计要求的分析得到的状态图,设计出时序电路的过程;时序逻辑电路可分为同步和异步,然而采用传统的时序电路的设计方法时,即使是同步时序电路的设计也需要     

时序逻辑电路的分析

在历年数字电子技术考研题目中,时序逻辑电路的分析是要求重点掌握的也是必考的,时序逻辑电路的分析分同步和异步时序电路,因此,本文就同步和异步时序电路分析的题型,列举几个例题,描述出一个完整的解题思路,帮助读者提高对数字电路的解题能力时序逻辑电路的分析步骤一般有如下几步:1.看清电路根据给定的电路,首先明确电路的各个组成部分及输入、输出信号,再确定电路类型是同步时序电路还是异步时序电路,是Moore型电路还是Mealy型电路。2.写出方程⑴由电路中组合逻辑电路部分的逻辑关系,列出每个驱动方程。它反映了各触发器输入信号的组合…     

同步时取电路优化中的时序重构技术

本文论述了８０年代初以来，同步时序电路优化方法中出现的时序重构技术的基本理论、方法和应用，并指出了此技术进一步实用化的几种方法．     

未知时序电路状态图生成算法及状态间路径的递归导出

运用数字系统自动化设计的基本理论和技术，可采用逻辑反向设计法分析未知逻辑电路．本文为分析未知时序逻辑提出一种适合多状态、复杂同步时序电路的数据采集方法，并引入状态网络和基于状态网络的路径导出算法，使时序机数据采集有较理想的时空开销．     

改进的时间帧展开的时序电路等价验证算法

提出一种改进的基于时间帧展开的时序电路等价验证算法,其来源于模型检查中的基于数学归纳的验证算法,在使用并简化了SAT问题中不可满足子集提取过程后,将基本条件检查和归纳检查合并处理．为了能在时间帧展开过程中减少状态搜索空间,利用结构不动点技术并提出了准动态唯一状态约束等改进的方法．实验表明,随着时间帧的不断展开,文中算法运行时间的增长速度明显慢于基于数学归纳法的验证算法,其适合验证经过时序优化后的电路．     

时序逻辑电路的分析

在历年数字电子技术考研题目中,时序逻辑电路的分析是要求重点掌握的也是必考的,时序逻辑电路的分析分同步和异步时序电路,因此,本文就同步和异步时序电路分析的题型,列举几个例题,描述出一个完整的解题思路,帮助读者提高对数字电路的解题能力 时序逻辑电路的分析步骤一般有如下几步:     

未知时序电路状态图生成算法及状态间路径的递…

运用数字系统自动化设计的基本理论和技术，可采用逻辑反向设计法分析未各逻辑电路，本文为分析未知时序逻辑提出一个适合多状态，复杂同步时序电路的数据采集方法，并引入状态网络和基于状态网络的路径导出算法，使时序时机数据采集有较理想的时空开销。     

Theoretical comparison between sequential redundancy addition and removal and retiming optimization techniques

This paper attempts to determine the capabilities of existing redundancy addition and removal (SRAR) techniques for logic optimization of sequential circuits. To this purpose, we compare this method with the retiming and resynthesis (RaR) techniques. For the RaR case the set of possible transformations has been established by relating them to STG transformations by other authors. Following these works, we first formally demonstrate that logic transformations provided by RaR are covered by SRAR as well. Then we also show that SRAR is able to identify transformations that cannot be found by RaR. This way we prove that the sequential redundancy addition and removal technique provides more possibilities for logic optimization.     

Variables Bounding Based Retiming Algorithm

Retiming is a technique for optimizing sequential circuits.In this paper,we discuss this problem and propose an improved retiming algorithm based on varialbes bounding.Through the computation of the lower and upper bounds on variables,the algorithm can significantly reduce the number of constratints and speed up the execution of retiming.Furthermore,the elements of matrixes D and W are computed in a demand-driven way,which can reduce the capacity of memory,It is shown through the experimental results on ISCAS89 benchmarks that our algorithm is very effective for large-scale seuqential circuits.     

基于扫描D触发器的可逆电路测试综合方法

为了实现可逆逻辑电路的可测性设计,充分利用可逆逻辑电路中存在的输出引脚,提出一种可逆逻辑电路测试综合方法.通过定义可逆逻辑门的可观性值和可控性值的计算方法,对可逆逻辑电路的可测性进行建模;通过插入观察点,制定了可逆组合逻辑电路可测性实现方案;通过对现有的D触发器进行改造并构建全新的扫描D触发器,制定了可逆时序电路的可测性逻辑实现方案;最后分析了扫描D触发器的工作特点,规范了测试步骤,建立一种可逆逻辑电路的测试综合方法.实验结果表明,与现有方法相比,文中方法插入观察点代价平均增加不到1%,但电路的可观性平均能得到24%的改善.     

基于BDD的组合电路等价性检验

本文分析了基于BDD的组合电路等价性检验；讨论了构造输出函数的二叉判定图BDD的不同方法，并分析了BDD间布尔操作的不同的算法的异同；然后给出了一种基于BDD的组合电路等价性检验方法。     

下三角矩阵神经网络逻辑电路的设计

由于人工神经网络的卓越优点，为制造超高速，高可靠和可编程的数字集成电路提供了新途径，具有下三角形连接矩阵的Ｈｏｐｆｉｅｌｄ模型在同一输入下仅有唯一的平衡点。本文将讨论基于这种网络模型的组合逻辑电路的逻辑设计方法，以最小化神经元个数为目标的启发式优化算法及权电阻网络参数的计算方法。     

Design for Testability for Complete Test Coverage

Some design-for-testability techniques, such as level-sensitive scan design, scan path, and scan/set, reduce test pattern generation of sequential circuits to that of combinational circuits by enhancing the controllability and/or observability of all the memory elements. However, even for combinational circuits, 100 percent test coverage of large-scale circuits is generally very difficult to achieve. This article presents DFT methods aimed at achieving total coverage. Two methods are compared: One, based on testability analysis, involves the addition of test points to improve testability before test pattern generation. The other method employs a test pattern generation algorithm (the FAN algorithm). Results show that 100 percent coverage within the allowed limits is difficult with the former approach. The latter, however, enables us to generate a test pattern for any detectable fault within the allowed time limits, and 100 percent test coverage is possible.     

Hitest: A Knowledge-Based Test Generation System

Efforts to develop computer-based automatic test generation for digital circuits have been generally unsuccessful, except in the case of combinational circuitry. Current ATPG methods for sequential circuits often require a considerable amount of computer time and generate unstructured test waveforms of limited value. Experienced human test programmers, on the other hand, appear to have little difficulty in generating high-quality tests for complex sequential circuits when they have a good understanding of how the circuit operates. This article considers the causes of failure in automatic test generation algorithms and describes a new system called Hitest. This system lets the computer use human understanding of circuit operations to generate more effective tests.     

General decomposition of incompletely specified sequential machines with multi-state behavior realization

This paper is devoted to decomposition of sequential machines, discrete functions and relations. Sequential machine decomposition consists in representation of a given machine as a network of collaborating partial machines that together realize behavior of the given machine. A good understanding of possible decomposition structures and of conditions under which the corresponding structures exist is a prerequisite for any adequate circuit or system synthesis. The paper discusses the theory of general decomposition of incompletely specified sequential machines with multi-state behavior realization. The central point of this theory is a constructive theorem on the existence of the general decomposition structures and conditions under which the corresponding structures exist. The theory of general decomposition presented in this paper is the most general known theory of the binary, multi-valued and symbolic sequential and combinational discrete network structures. The correct circuit generator defined by the general decomposition theorem covers all other known structural models of sequential and combinational circuits as its special cases. Using this theory, in recent years we developed a number of effective and efficient methods and EDA tools for sequential and combinational circuit synthesis that consistently construct much better circuits than other academic and commercial state-of-the-art synthesis tools. This demonstrates the practical soundness of our theory. This theory can be applied to any sort of binary, multi-valued and symbolic systems expressed as networks of relations, functions or sequential machines, and can be very useful in such fields as circuit and architecture synthesis of VLSI systems, knowledge engineering, machine learning, neural network training, pattern analysis, etc.