Microsystems the Microprocessor in the Biological Laboratory

The use of microprocessors in the biological laboratory is a logical result of the evolution of computer use in the biomedical sciences. In 1963, H. K. Hartline and Floyd Ratliff, working at Rockefeller University in New York City, hooked up a CDC 160A computer as a generalpurpose laboratory instrument for data acquisition during their experiments on vision.¹For stimulus control, they used a digital programmer constructed from commercially available discrete transistor logic circuits.²The work in the Hartline-Ratliff laboratory was a continuation of earlier work done by Hartline on inhibitory interaction in the horseshoe crab's eye, for which Hartline shared the Nobel Prize for Physiology and Medicine in 1966, with Wald and Granit.³     

Alternatives for Data Network Architectures

The increasing use of computer data communications over the past several years has spawned a variety of network architectures to support requirements for distributed processing. Developed by various R&D groups,^1-3by the common carriers,^4-4by minicomputer and mainframe manufacturers,^7,8and by the vendors of traditional communications hardware,^9,10these new architectures represent alternative means to similar ends. This article provides a framework for understanding existing and forthcoming systems, focusing particular attention on the impact of evolving requirements and technologies.     

Distributed memory systems for simulating artificial neural networks

In executing tasks involving intelligent information processing, the human brain performs better than the digital computer. The human brain derives its power from a large number [O(10¹¹)] of neurons which are interconnected by a dense interconnection network [O(10⁵) connections per neuron]. Artificial neural network (ANN) paradigms adopt the structure of the brain to try to emulate the intelligent information processing methods of the brain. ANN techniques are being employed to solve problems in areas such as pattern recognition, and robotic processing. Simulation of ANNs involves implementation of large number of neurons and a massive interconnection network. In this paper, we discuss various simulation models of ANNs and their implementation on distributed memory systems. Our investigations reveal that communication-efficient networks of distributed memory systems perform better than other topologies in implementing ANNs.     

Cost, Performance, and Size Tradeoffs for Different Levels in a Memory Hierarchy*

Until recently, electronically addressable devices such as ferrite core, plated wire, semiconductor memories, and electromechanically addressable devices such as magnetic tapes, disks, and drums were the few technologies from which a computer system designer could build a memory system. A number of different new technologies and devices have been developed that close the "access gap"¹⁴between the two dissimilar technologies mentioned above. These include charge-coupled devices (CCD's),²bubble memories,⁴electron beam addressed memories (EBAM),¹⁷and domain tip propagation (DOT).¹⁶Other technologies like CMOS¹and integrated injection logic (I²L),⁹compete directly with the existing technologies. Table 1 (see p. 46) shows the possibility of a six-level hierarchy and some cost and performance projections for these technologies.     

Static and Dynamic Characteristics of XPL Programs

One use of performance measurement techniques is in the study of operational characteristics of programs written in high-level programming languages. Information derived from such studies can be used to construct benchmark programs and synthetic workloads,^1,2detect inefficiencies in programming language implementation, and suggest possible improvements in the design of computers.^3,9,10Our main interest is in the latter area: the discovery of primitive operations, implied by the semantics of a programming language, that can be added to the firmware or hardware of a computer to improve overall system performance. These computer architecture optimization techniques have been applied in several studies^3,9and have been used commercially to design efficient pseudo machines for the Burroughs B1700.^10,12     

A computer model to calculate flow resistance in open channels with movable boundaries

A computer package is developed to calculate the flow resistance in an alluvial channel based on the approaches of Einstein,³, Shen,⁶ Simons & Richardson,⁷ and Senturk.⁵ The model can classify the bedform, calculate the flow resistance and design the channel section based on each approach. The results of the different approaches are compared to one set of the field measurements to validate the model. The model can run on main frame computers or personal computers; it will aid hydraulic engineers to choose the optimum channel sections in a fast, efficient and reliable way without human error interpretations.     

A modified GERT network for automatic acquisition of temporal knowledge

This paper describes a technique which has been developed for automatically acquiring temporal knowledge for use in an Intelligent Simulation Training System (ISTS)^*. The objective of the ISTS is to train students in monitoring and controlling physical objects in time and space. The ISTS consists of a graphic computer simulation, an expert system, and a user interface. The graphic computer simulation represents the system to be monitored. The trainee responds to routine and/or critical situations as depicted in the simulation by typing in commands to simulation objects.

ISTS domain knowledge is automatically acquired by a subsystem known as ELICIT: Expertise Learner and Intelligent Causal Inference Tool. ELICIT incorporates a modified GERT network for representing knowledge concerning dependencies among temporal events. The network is used as a basis for prompting the domain expert for knowledge. In addition, ELICIT draws upon knowledge contained in the network for the development of contingency plans concerning timing of events. This implementation is coded in Common LISP and Joshua (a knowledge representation language developed by Symbolics, Inc.) on a Symbolics 3630 LISP machine.     

An engineering economy expression analyzer

Students and practitioners of engineering economy are faced with the unenviable task of evaluating engineering economy expressions. If the example expression: 1000 ^* (P/F,10,5) − 500 ^* (P/F,6,20) + 100 ^* (P/A,8,20) were solved manually, it would require three table look-ups to determine the values of the cash flow factors.

This paper discusses the automation of engineering economy expression analysis. A public domain program has been developed that solves engineering economy expressions. The above expression can be entered into the program exactly as written, and the computer will respond with the evaluated result. The program also has an integral editor and the ability to solve for unknowns such as interest rates.     

Operating Systems for Computer Networks

The last decade has seen the rapid evolution of computer communication networks from research curiosities to operational utilities. The Arpanet,¹for example, currently supports communication among more than 100 computer systems and is used daily by hundreds of users. Commercial networks, such as Telenet²in the United States and Datapac³in Canada, have very bright futures. One attraction of these networks is their ability to provide access to a wide variety of resources distributed among the connected computers.     

Special Feature Report on Intermag '77 Current Developments in Magnetic Bubble Technology

Last November we reported that magnetic bubble memory devices would be available this year, permitting designers to find out about them first hand.¹The most important development since then for the computer industry was Texas Instruments' March announcement of the first commercially available bubble device–a 92K chip–for about $200 each in sample quantities. Of importance as an indication of what the next two years could bring to the market was Rockwell International's announcement on June 7 at the International Magnetics Conference in Los Angeles of the successful development of a one-million-bit bubble device in its Electronic Research Division.²     

A sparse matrix algorithm on the Boolean vector machine

The Boolean Vector Machine (BVM) is a large network of extremely small processors with very small memories operating in SIMD mode using bit serial arithmetic. Individual processors communicate via a hardware implementation of the Cube Connected Cycles (CCC) network. A prototype BVM with 2048 processing elements, each with 200 binary bits of memory, is currently being built using VLSI technology.

The BVM's bit-serial arithmetic and the small memories of individual processors are apparently a drawback to its effectiveness when applied to large numerical problems. In this paper we analyze an implementation of a basic matrix-vector iteration algorithm for sparse matrices on the BVM. We show that a 2²⁰ Pe BVM can deliver over 1 billion (10⁹) useful floating-point operations per second for this problem. The algorithm is expressed in a new language (BVL) which has been defined for programming the BVM.     

Circuit Switching

Currently there is a considerable interest in the development of digital communication techniques. This interest is due to the development of distributed processing concepts,^1,2,3to changing regulatory policies of the US Government (the Carterfone decision and subsequent FCC rulings), and to the development of large networks.4 One widely used communication technique that has tremendous growth potential is circuit switching. There are two primary reasons for computer-oriented people to be interested in circuit switching. First, the computer plays a major role in the control and implementation of a circuit switch.5 Second, circuit switches have been used as the interconnection structure for systems containing (or hypothesized to contain) a multiplicity of processing elements.^2,5,6     

Information Processing with an Associative Parallel Processor

Research into new computer structures, which would be better suited to non-numerical information processing tasks, has been in progress for some years.^1,2,3The problem has been to design a computing system with high hardware efficiency and low software complexity over a wide range of these applications. Recent research^4,5,6has indicated that these apparently conflicting requirements could possibly be achieved by a parallel processing system containing content-addressable storage. Hence there is a revival of interest in associative memories and associative processors.     

The Many Faces of Simulation

The meaning of computer simulation, like beauty, rests in the eyes of the beholder. To the practitioner of econometrics, a model may be a complex algorithm, and he will simulate the prosperity (or poverty) of municipalities, states, and nations on the basis of the different values of the variables. Others have defined simulation as "the development and use of models to aid in the evaluation of ideas and the study of dynamic systems or situations."¹The first paper in this issue will provide another definition. Obviously, more definitions could be quoted, but of one thing we can be certain: simulation provides a laboratory in which we can test proposals without subjecting ourselves to the penalties of trial in the real world. These penalties, in cost and time, have provided the motivation for developing the art of simulation.     

Special Feature A Survey of Methods of Achieving Reliable Software

As organizations become more dependent on computers, they become more sensitive to computer system failures. The importance of computer reliability in realtime control systems (e.g., communications systems^8,15and traffic control systems) has been recognized for some time. Many computer users are now becoming aware that they accomplish more on systems which seldom crash because of malfunctions than on systems which run very rapidly (and correctly) between frequent crashes. Consequently, increasing emphasis is being placed by users and vendors on the reliability of the total system, and particularly the system software. A notable example of this is the emphasis placed by IBM on reliability concerns in the design and implementation of OS/VS2 Release 2.^35,36     

PRINCE密码算法的差分-线性分析

PRINCE是一个低时延轻量级分组密码算法,广泛应用于各种资源受限设备.PRINCE使用FX结构,其核心部件是PRINCEcore.差分-线性分析是一种经典分析方法,它将差分分析和线性分析结合起来,使用短的高概率差分特征和线性特征来攻击密码算法.研究了 PRINCEcore的差分-线性分析,使用2轮差分-线性区分器攻击...     

基于.NET的《英语口译》计算机辅助教学系统

英语口译教学必须加强实践性，强调口译技能技巧训练，传统的语言实验室已经很难达到这些要求。《英语口译》计算机辅助教学系统是基于.NET技术、采用C/S结构的计算机网络教学系统，它把《英语口译》中的各种训练方式在计算机局域网上实现，与传统的语言实验室相比，它具有很强的优越性。     

A strain-rate-dependent concrete material model for ADINA

The analysis, design and/or evaluation of protective structures and facilities for military use demands the accurate determination of material and structural response to high-intensity, short-duration impulse loadings. There currently exists a preponderance of data supporting increased strength characteristics in concrete, the primary construction material for protective facilities, at high strain rates. This paper summarizes the modification of the nonlinear concrete material model currently employed in the ADINA finite-element computer programs to account for high strain rate effects. The resultant strain-rate-dependent concrete material model encompasses the strain-rate range from 10⁻⁷s⁻¹ (quasi-static) to 10³s⁻¹, in both compression and tension.     

Modelling of the influence of HTdR on cell kinetics in mouse epidermis

Fluctuations occur in the labeling index (LI) of mouse epidermis over the first two days after application of tritiated thymidine (³HTdR) for which there has in the past been no explanation. Similarly, there has been no adequate explanation for the fluctuations in the percent labelled mitoses (PLM) data seen immediately after the first peak. Here we propose a model which provides an explanation for both these features. The hypothesis suggested is that some cells are killed by the ³HTdR either immediately when they are still in the S phase or later when they have reached G₁. In both cases the labelled precursor is released from the cell and may be incorporated into other S phase cells after an appropriate delay. The model has been formulated into a computer programme which can derive the appropriate LI or PLM curves and fit curves to the relevant data. The resulting curves fit the data well suggesting that such cytotoxic and reutilization processes may in fact occur.