高线性度CMOS射频AB类功率放大器设计

CMOS射频AB类功率放大器广泛应用于单片集成无线芯片内.采用恒定最大电流的方法对其效率进行分析,采用归一化输入电压的方法对其线性度进行分析.利用AB类功率放大器系统增益的非线性与CMOS跨导非线性相互补偿,提高了CMOS射频AB类放大器的线性度.基于TSMC 0.18μm CMOS混合信号工艺,设计了一款两级射频AB类功率放大器.该射频功率放大器差动输入,单端输出,工作频段为804~940MHz,工作电压为3V.仿真指标为:增益为11dB,输出1dB压缩点为17.2dBm,OIP3为18.2dBm,附加效率为37%.     

一种用于便携式射频识别阅读器的CMOS功率放大器

针对一种特定的射频识别技术的通讯协议(ISO1800-6B),提出了一种应用于射频识别读写器中的发射机前端结构,以实现发射信号的OOK调制.采用0.18μm CMOS工艺实现的这种高效率、高度集成的无线发射机前端由射频信号调制器、E类功率放大器以及相应的逻辑控制单元组成,其中的功率放大器的小信号增益约为23dB,其1dB压缩点输出功率为17.6dBm,最大输出功率为19.0dBm,而最大功率增加效率为35.4%.整个发射机的输出信号满足相应协议的特定要求,可以实现不同调制深度(18%和100%)的射频信号输出.     

一种用于便携式射频识别阅读器的CMOS功率放大器

针对一种特定的射频识别技术的通讯协议(ISO1800-6B),提出了一种应用于射频识别读写器中的发射机前端结构,以实现发射信号的OOK调制.采用0.18μm CMOS工艺实现的这种高效率、高度集成的无线发射机前端由射频信号调制器、E类功率放大器以及相应的逻辑控制单元组成,其中的功率放大器的小信号增益约为23dB,其1dB压缩点输出功率为17.6dBm,最大输出功率为19.0dBm,而最大功率增加效率为35.4%.整个发射机的输出信号满足相应协议的特定要求,可以实现不同调制深度(18%和100%)的射频信号输出.     

CMOS射频集成电路的研究进展

近年来，射频集成电路(RFIC)的应用和研究得到了飞速的发展，CMOS射频IC的研究更是成为该领域的研究重点和热点。文章对CMOS技术在射频和微波领域的应用进行了详细的探讨，着重介绍了当前射频通讯中常用的收发机结构及其存在的问题和解决方案；分析了射频收发机前端关键电路模块低噪声放大器(LNA)、混频器(Mixer)、压控振荡器(VCO)、功率放大器(PA)和射频关键无源元件的最新研究进展；展望了CMOS技术在射频领域的发展前景。     

3G CMOS功率放大器提升移动设备可靠性和数据传输率

Black Sand是业内第一家做3G CMOS射频功率放大器(PA)的公司,前不久,该公司推出了两条新的3G CMOS射频功率放大器(PA)产品线(BST34和BST35系列),它们可显著提升各种手机、平板电脑和数据卡的可靠性和数据传输量并降低成本。该产品系列包括6     

CMOS工艺射频功率放大器的实现与验证

射频功率放大器是无线设备的关键器件,GaAs工艺被广泛使用在射频功放的设计制造上。而CMOS工艺在生产成熟度和成本上有很大优势,主要关注用CMOS工艺来做射频功放的问题,介绍世界上第一颗量产的CMOS功放及其所使用的特殊技术。利用一款成熟的手机产品,替换这颗功放及外围器件,最后与原产品进行对比测试。     

基于有源匹配转换器的全集成双频带射频CMOS功率放大器的设计

设计了基于有源转换器的双频带射频CMOS功率放大器,该放大器可以应用于移动WiMAX系统. 设计采用了0.13μm CMOS 工艺并且所有的匹配完全集成在芯片内. 转换器可以通过有源匹配而在双频带工作,在2.5和3.5GHz,转换器的效率为78.2%和70.4%,功率放大器的增益分别为26.5和24.8dB,功率增加效率为20%和28%,在平均功率25dBm处,三阶交调系数均低于-30dBc.     

基于包络检测的射频功率放大器平均效率提高技术

提出了一种基于包络检测的射频功率放大器平均效率提高技术。该技术通过片上集成的包络检测器检测输入信号强度,通过动态配置功率放大管的尺寸,并调节输出阻抗匹配网络优化负载阻抗,提高功率放大器在低输出功率下的效率,达到提高功率放大器平均效率的目的。电路采用0.18 μm CMOS工艺实现,后仿真结果表明,在高输出功率模式下,该射频功率放大器的输出1 dB压缩点为18.05 dBm,PAE为30.2%;在两档低输出功率模式下的输出1 dB压缩点分别为14.9 dBm和11 dBm,PAE分别为24.11%和17.1%。     

基于BSIM3V3模型的E类CMOS功率放大器设计

为减小功率放大器的尺寸和提高放大器的效率,可以利用晶体管的漏端寄生结电容作为E类射频功率放大器的分流电容.文章提出根据晶体管漏体寄生结电容来设计E类CMOS功率放大器,在BSIM3V3漏体结电容模型的基础上,分析了漏端边缘电容对设计的影响,同时,采用数据拟合来降低计算复杂度.仿真结果表明,该方法可运用于实际设计.文章的研究为低功耗E类CMOS功率放大器的小型化设计提供了一种新的方法,具有一定的应用参考价值.     

CMOS射频集成电路的最新进展和应用

本文介绍RF(射频)CMOS集成电路的最新进展和应用.着重于深亚微米CMOS技术在实现高端射频(几十GHz频带)集成系统方面的潜能.首先,综述CMOS技术的主要特点,继而介绍CMOS射频集成电路的最新进展.其中有63GHz的毫米波段的CMOS压控振荡器,数据速率达50Gb/s的2:1多路复用器,40GHzCMOS低功耗注入锁定分频器,24GHzCMOS射频前端和17GHzISM/WLAN的CMOS射频前端等.同时,介绍CMOS射频集成电路的几种主要应用,如无线局域网和射频识别等.     

A fully integrated UHF RFID reader SoC for handheld applications in the 0.18 μm CMOS process

A low cost fully integrated single-chip UHF radio frequency identification(RFID) reader SoC for short distance handheld applications is presented.The SoC integrates all building blocks—including an RF transceiver,a PLL frequency synthesizer,a digital baseband and an MCU—in a 0.18μm CMOS process.A high-linearity RX frontend is designed to handle the large self-interferer.A class-E power amplifier with high power efficiency is also integrated to fulfill the function of a UHF passive RFID reader.The measure...     

A 900 MHz,21 dBm CMOS linear power amplifier with 35% PAE for RFID readers

A two-stage differential linear power amplifier(PA) fabricated by 0.18μm CMOS technology is presented. An output matching and harmonic termination network is exploited to enhance the output power,efficiency and harmonic performance.Measurements show that the designed PA reaches a saturated power of 21.1 dBm and the peak power added efficiency(PAE) is 35.4%,the power gain is 23.3 dB from a power supply of 1.8 V and the harmonics are well controlled.The total area with ESD protected PAD is 1.2×0.55 mm~2.Sy...     

读卡器末级功率放大器的设计与实现

在研究了平衡功率放大器的电路结构和工作原理基础上,设计了一个工作中心频率为915MHz,输出功率为32dBm应用于读卡器系统的末级功率放大器。为了在工作频段内实现平坦的功率增益和获得良好的输入、输出驻波比,本文采用了平衡放大技术来设计该功率放大器。仿真优化和实际测试结果表明,在整个工作频段内放大器的增益平坦度小于±0.5dB,输入、输出驻波比小于1.5,完全满足设计指标要求。因此这种运用平衡放大技术设计的放大器可以很好地应用在读卡器系统中,从而提高读卡器的读卡性能。     

A multimode,power-adjustable transmitter for UHF mobile RFID reader

Aiming at the expansive application of RFID technology, design considerations are expatiated to a highly-integrated, multimode, power-adjustable transmitter in mobile UHF RFID reader with CMOS process. The transmitter consists of digital, baseband and RF sections, including an up-conversion mixer and a gain-variable power amplifier (PA). Multiple data modes can be generated in digital section. The direct-conversion RF section is proposed to minimize the off-chip components and provide a low-cost, highly efficient solution. The highlight of the paper is the PA can achieve a maximum output power of 26 dBm and maintain a power-added efficiency (PAE) higher than 40% over the 18–26 dBm power range. Feasibility of the transmitter is validated by ADS simulator.     

RFID transceiver for wireless powering brain implanted microelectrodes and backscattered neural data collection

The developments in micro-nano-electronics, biology and neuro-sciences make possible interfaces between the human brain and the environment. Implantable and smart microprobes have been proposed that are able to transmit neural data at the outside world in RFID mode. In this paper a high resolution RFID reader, collecting neural data from implanted electrodes while powering the tag is proposed. The system gives power to the implanted tag, using a class E power amplifier (PA) and in between receives the data by an asynchronous demodulation. The technology used is a standard 65 nm CMOS TSMC. Simulations shown here, reveal an average power consumption of the overall system of 65 mW with a supply of 1.2 V and a BER less than 10⁻⁵.     

Design of wideband hybrid silicon carbide single-stage power amplifier

RF wideband power amplifiers are desirable as they will reduce equipment, power consumption and operating cost for the RF communication infrastructure. For decades, the realization of single-stage broadband power amplifier has posed a significant challenge due to the electrical and thermal limitations of GaAs transistor technology. Silicon carbide (SiC) MESFET technology is a strong contender for such applications due to its superior properties. In particular, its high impedance reduces mismatch commonly encountered in such power amplifier.In this work, design of wideband hybrid single-stage power amplifier using a commercial 4H-SiC MESFET CRF24010 from Cree Inc is presented. The amplifier has been designed and fabricated for operating frequencies 650-1800 MHz, which is equivalent to more than 90% bandwidth, compared to only 3-4% bandwidth achievable using GaAs technology.     

一种新型的基于无源射频身份识别应答器的电源供给方案

提出了一种基于全集成的无源射频身份识别(RFID)应答器芯片的电源供给方案,并在特许半导体的0.35μm嵌入EEPROM的CMOS工艺线上流片成功.提出的AC/DC和DC/DC电荷泵能够为RFID的应答器芯片提供稳定的工作电压,同时具有极低的功耗和很高的充电效率.还给出了电压倍增器的分析模型、与其他电荷泵的升压原理的比较以及仿真结果和芯片测试结果.     

A 900-MHz fully integrated SOI power amplifier for single-chipwireless transceiver applications

This paper presents a silicon-on-insulator (SOI) fully integrated RF power amplifier for single-chip wireless transceiver applications. The integrated power amplifier (IPA) operates at 900 MHz, and is designed and fabricated using a 1.5-μm SOI LDMOS/CMOS/BJT technology. This technology is suitable for the complete integration of the front-end circuits with the baseband circuits for low-cost low-power high-volume production of single-chip transceivers. The IPA is a two-stage Class E power amplifier. It is fabricated along with the on-chip input and output matching networks. Thus, no external components are needed. At 900 MHz and with a 5-V supply, the power amplifier delivers 23-dBm output power to a 50-Ω load with 16-dB gain and 49% power-added efficiency     

ZigBee无线网络功放的设计与仿真

ZigBee是一种低速无线个域网技术,适用于通信数据量小,速度相对较低,并且功耗低的场合。组网灵活是其一大特点,但是由于传输距离比较短,从而限制了其发展。基于ZigBee无线通信网络技术,提出了一种通过增大发射信号功率、提高接收信号灵敏度来增加系统传输距离的方法。使用ADS软件主要对功率放大电路和低噪声放大电路进行仿真与性能优化,从而得出最佳设计方案。仿真结果基本满足了系统功率和增益的要求。