DC offset calibration method for zero-IF receiver removing the PGA-gain-correlated offset residue

This paper presents a novel DC offset calibration method for the zero-IF (intermediate frequency) receiver that removes the PGA-gain-correlated offset residue. The conventional calibration method usually uses the classic input/output referred offset model, in which the receiver IF programmable gain amplifiers (PGAs) have offset sources that varies a lot with different gain settings. Consequently, the conventional calibration method needs to generate the calibration code at each gain step and requires a huge look up table (LUT) to store the calibration values. This paper presents a new DC offset model which is gain non-correlated, by analyzing two types of commonly used PGA. Based on the new model, a LUT-free single-step DC offset calibration method in together with the implementation circuit is designed. The proposed method has been verified on a practical zero-IF receiver circuit in a standard 0.18 μm CMOS technology through the Monte Carlo (MC) simulation. The simulation results show that the receiver IF output offset residue after calibration using the proposed method is reduced to below 12 mV, in contrast to 200 mV by the conventional method.     

A self-calibration technique for wide tuning range PLLs

This paper presents a new calibration technique applicable for wide tuning range phase locked loops (PLLs) using very low gain voltage controlled oscillators (VCO). This technique uses the PLL main loop for the coarse and fine tuning of the VCO. Instead of using two loops which has been reported in previous works, in this work the VCO tuning voltage is used to calibrate the VCO switch capacitor array. Since the proposed calibration circuit operates in a closed loop form, it can be used for channel selection as well as adjusting for process, voltage and temperature variations. In addition, the calibration circuit has been used to set the VCO tail current in order to optimize VCO phase noise. A prototype frequency synthesizer has been designed in 0.18-μm CMOS process to work for a frequency range from 2.4 to 2.72 GHz. Simulation results show that using the proposed technique, a spur level of ?60 dB at 5 MHz offset from carrier was achieved while having negligible power overhead.     

A 0.5 V offset cancelled latch comparator in standard 0.18 μm CMOS process

This paper presents a new 0.5 V high-speed dynamic latch comparator with built-in foreground offset cancellation capability and rail-to-rail input range. Traditional latch comparators lose their speed performance in low voltage condition, especially in sub-1V applications. The proposed latch comparator utilizes a speed-up technique based on a novel boosting method to mitigate the low voltage imperfections on circuit operation. Employing a new offset cancellation technique based on the same boosting capacitors is another key idea. This enhances the accuracy of the ultra low-voltage latch comparators and relaxes the need for preamplifier stage, which is conventionally used in the low offset latch comparator. The performed Monte Carlo simulations over corners in 0.18 μm standard CMOS process show the improvement of input referred offset voltage with a standard deviation of 29.9 mV/299 μV before and after offset cancellation, respectively. The designed comparator dissipates 34 μW power from 0.5 V voltage supply while operating in 200 MHz clock frequency and detects 1 mV input difference.     

A low-power spread-spectrum clock generator with three-step frequency and VCO gain calibration for serial-ATA applications

This paper presents a low power ring oscillator-based spread-spectrum clock generator with three-step frequency and voltage-controlled oscillator (VCO) gain calibration for S-ATA applications. To meet the low jitter requirements with a small VCO gain, a ring-type VCO with three step frequency calibration and gain calibration scheme is proposed. The proposed coarse tuning method selects the optimal tuning currents and capacitances of the ring VCO to optimize the phase noise. The gain of ring-type VCO can be reduced and kept constant with the proposed three-step frequency and VCO gain calibration. As a result, it can improve the phase noise characteristics of the ring-type VCO and make it more robust to the PVT variations. Also, charge pump up/down current mismatches are compensated with the current mismatch compensation block. This chip is fabricated with 65 nm CMOS technology, and the die area is 430 × 460 μm². The power consumption is 12 mW at 1.2 V supply voltage. The measured RMS jitter and phase noise are 2.835 ps and ?96.83 dBc/Hz at 1 MHz offset, respectively.     

A novel analog/digital reconfigurable automatic gain control with a novel DC offset cancellation circuit

An analog/digital reconfigurable automatic gain control(AGC) circuit with a novel DC offset cancellation circuit for a direct-conversion receiver is presented.The AGC is analog/digital reconfigurable in order to be compatible with different baseband chips.What’s more,a novel DC offset cancellation(DCOC) circuit with an HPCF(high pass cutoff frequency) less than 10 kHz is proposed.The AGC is fabricated by a 0.18μm CMOS process.Under analog control mode,the AGC achieves a 70 dB dynamic range with a 3 dB-bandwidth larger than 60 MHz.Under digital control mode,through a 5-bit digital control word,the AGC shows a 64 dB gain control range by 2 dB each step with a gain error of less than 0.3 dB.The DC offset cancellation circuits can suppress the output DC offset voltage to be less than 1.5 mV,while the offset voltage of 40 mV is introduced into the input.The overall power consumption is less than 3.5 mA,and the die area is 800×300μm~2.     

A fully on-chip 1-μW capacitor-free low-dropout regulator with adaptive output stage

A fully on-chip 1-μW fast-transient response capacitor-free low-dropout regulator (LDO) using adaptive output stage (AOS) is presented in this paper in standard 0.13-μm CMOS process. The AOS circuit is proposed to deliver extra four times of output current of the operational amplifier at medium to heavy load to extend the bandwidth of the LDO and enhance the slew rate at the gate of the power transistor. And the AOS circuit is shut off at light load to reduce the quiescent current and maintain the stability without requiring area-consuming on-chip capacitor. Meanwhile, the proposed AOS circuit introduces V_OUT offset at medium to heavy load to counteract the V_OUT drop, which is caused by I_LOAD increase. Hence, transient performances of LDO and V_OUT drop between light load and full load are improved significantly with 1.1-μA quiescent current at light load. From the post simulation results, the LDO regulates the output voltage at 0.7 V from a 0.9-V supply voltage with a 100-mA maximum load current. The undershoot, the overshoot and the recovery time of the proposed LDO with I_LOAD switching from 50 μA to 100 mA in 1 μs are about 130 mV, 130 mV and 1.5 μs, respectively. And the V_OUT drop between light load and full load reduces to 0.16 mV.     

Wide Dynamic Range CMOS Amplifier Design for RF Signal Power Detection via Electro-Thermal Coupling

A differential temperature sensor for on-chip signal and DC power monitoring is presented for built-in testing and calibration applications. The amplifiers in the sensor are designed with class AB output stages to extend the dynamic range of the temperature/power measurements. Two high-gain amplification stages are used to achieve high sensitivity to temperature differences at points close to devices under test. Designed in 0.18 μm CMOS technology, the sensor has a simulated sensitivity that is tunable up to 210 mV/°C with a corresponding dynamic range of 13 °C. The sensor consumes 2.23 mW from a 1.8 V supply. A low-power version of the sensor was designed that consumes 1.125 mW from a 1.8 V supply, which has a peak sensitivity of 185.7 mV/°C over a 8 °C dynamic range.     

A 0.003-mm2, 0.35-V, 82-pJ/conversion ultra-low power CMOS all digital temperature sensor for on-die thermal management

In this paper, a 0.35 V, 82 pJ/conversion ring oscillator based ultra-low power CMOS all digital temperature sensor is presented for on-die thermal management. We utilize subthreshold circuit operation to reduce power and adopt an all-digital architecture, consisting of only standard digital gates. Additionally, a linearization technique is proposed to correct the nonlinear characteristics of subthreshold MOSFETs. A bulk-driven 1-bit gated digitally controlled oscillator is designed for the temperature sensing node. Also, a 1-bit time-to-digital converter is employed in order to double the fine effective resolution of the sensor. The proposed digital temperature sensor has been designed in a 90-nm regular V _T CMOS process. After a two-point calibration, the sensor has a maximum error of ?0.68 to +0.61 °C over the operating temperature range from 0 to 100 °C, while the effective resolution reaches 0.069 °C/LSB. Under a supply voltage of 0.35 V, the power dissipation is only 820 nW with the conversion rate of 10K samples/s at room temperature. Also, the sensor occupies a small area of 0.003 mm².     

An ultra-low power energy-efficient microsystem for hydrogen gas sensing applications

This paper presents a fully integrated power management and sensing microsystem that harvests solar energy from a micro-power photovoltaic module for autonomous operation of a miniaturized hydrogen sensor. In order to measure H₂ concentration, conductance change of a miniaturized palladium nanowire sensor is measured and converted to a 13-bit digital value using a fully integrated sensor interface circuit. As these nanowires have temperature cross-sensitivity, temperature is also measured using an integrated temperature sensor for further calibration of the gas sensor. Measurement results are transmitted to the base station, using an external wireless data transceiver. A fully integrated solar energy harvester stores the harvested energy in a rechargeable NiMH microbattery. As the harvested solar energy varies considerably in different lighting conditions, the power consumption and performance of the sensor is reconfigured according to the harvested solar energy, to guarantee autonomous operation of the sensor. For this purpose, the proposed energy-efficient power management circuit dynamically reconfigures the operating frequency of digital circuits and the bias currents of analog circuits. The fully integrated power management and sensor interface circuits have been implemented in a 0.18 μm CMOS process with a core area of 0.25 mm². This circuit operates with a low supply voltage in the 0.9–1.5 V range. When operating at its highest performance, the power management circuit features a low power consumption of less than 300 nW and the whole sensor consumes 14.1 μA.     

A high-gain complementary metal-oxide semiconductor op amp using composite cascode stages

In this work, a complementary metal-oxide semiconductor (CMOS) op amp design using composite cascode stages is reported. The design follows the classic Widlar architecture and is fabricated on a 0.25 μm CMOS process. The measured gain of 117 dB is comparable to that achieved in bipolar designs in this architecture. This design is suited for precision instrumentation applications where high gain, low input offset voltage and small cell size are important. It provides a common-mode input range of ?1 to 0.7 V using±1 V power supplies with a quiescent current of 55 μA. The use of the composite cascode also allows for dominant pole compensation with a single capacitor. A phase margin of 43° is achieved with a 3.5 pF compensation capacitor. The resulting cell size for the core op-amp circuit is approximately 24 × 16 mils, including large common centroid input devices that achieve an input offset voltage in the 1 mV range.     

一种应用于CMOS图像传感器数字双采样ADC的PGA电路

提出了一种应用于CMOS图像传感器数字双采样模数转换器(ADC)的可编程增益放大器(PGA)电路。通过增加失调采样电容,采集PGA运放和电容失配引入的失调电压,在PGA复位阶段和放大阶段进行相关双采样和放大处理,通过数字双采样ADC将两个阶段存储电压量化,并在数字域做差,降低了PGA电路引入的固定模式噪声。采用0.18μm CMOS图像传感器专用工艺进行仿真,结果表明:在输入失调电压-30~30mV变化区间,提出的PGA的输出失调电压可以降低到1mV以下,相比传统PGA输出失调电压随输入失调电压单倍线性关系而言大大降低了列固定模式噪声。     

Low-power wake-up receiver with subthreshold CMOS circuits for wireless sensor networks

We developed a wake-up receiver comprised of subthreshold CMOS circuits. The proposed receiver includes an envelope detector, a high-gain baseband amplifier, a clock and data recovery (CDR) circuit, and a wake-up signal recognition circuit. The drain nonlinearity in the subthreshold region effectively detects the baseband signal with a microwave carrier. The offset cancellation method with a biasing circuit operated by the subthreshold produces a high gain of more than 100 dB for the baseband amplifier. A pulse-width modulation (PWM) CDR drastically reduces the power consumption of the receiver. A 2.4-GHz detector, a high-gain amplifier and a PWM clock recovery circuit were designed and fabricated with 0.18-μm CMOS process with one poly and six metal layers. The fabricated detector and high-gain amplifier achieved a sensitivity of ?47.2 dBm while consuming only 6.8 μW from a 1.5 V supply. The fabricated clock recovery circuit operated successfully up to 500 kbps.     

A $$3\,\hbox{nV}/{\sqrt{\hbox{Hz}}}$$ rail-to-rail operational amplifier in silicon-on-sapphire with constant transconductance

This paper presents the design, fabrication, and electrical measurement results from a low-noise high-performance amplifier fabricated in the 0.5 μm silicon-on-sapphire (SOS) technology. The amplifier was designed with rail-to-rail input and output swing and constant transconductance in its entire common-mode range and targets biomedical instrumentation in SOS/SOI technologies. The amplifier reports \(3\,\hbox{nV}/{\sqrt{\hbox{Hz}}}\) of input-referred voltage noise at 10 kHz and has 0.4 mV of input-referred offset. The gain-bandwidth product of the amplifier is 12 MHz and the open-loop gain is 75 dB. The amplifier occupies 0.08 mm² of area and consumes 1.4 mW of power.     

A 2.5-V 56-mW baseband chain in a multistandard TV tuner for mobile and multimedia applications

This paper presents post-layout simulated results of an analog baseband chain for mobile and multimedia applications in a 0.13-μm SiGe BiCMOS process.A programmable 7th-order Chebyshev low pass filter with a calibration circuit is used in the analog baseband chain,and the programmable bandwidth is 1.8/2.5/3/3.5/4 MHz with an attenuation of 26/62 dB at offsets of 1.25/4 MHz.The baseband programmable gain amplifier can achieve a linear 40-dB gain range with 0.5-dB steps.Design trade-offs are carefully considered in designing the baseband circuit,and an automatic calibration circuit is used to achieve the bandwidth accuracy of 2%.A DC offset cancellation loop is also introduced to remove the offset from the layout and self-mixing,and the remaining offset voltage is only 1.87 mV.Implemented in a 0.13-μm SiGe technology with a 0.6-mm~2 die size,this baseband achieves IIP3 of 23.16 dBm and dissipates 22.4 mA under a 2.5-V supply.     

一种新型高精度宽电压范围的CMOS温度传感器

介绍了一种用于环境温度监测的新型高精度宽电压范围的CMOS温度传感器,采用0.13μm标准CMOS工艺的厚氧器件实现,芯片面积为37μm×41μm。该温度传感器在-20～60°C的温度范围内,采用两点校正方法之后,温度误差为-0.2°C/0.5°C。该温度传感器可以在1.8～3.6V的电源电压范围内安全可靠地工作,并且具有较高的电源抑制比。测试结果表明,其输出电压斜率为3.9mV/°C,1.8V下功耗为1.3μW。     

一种低功耗混合信号直流失调消除电路

设计了一种应用于直接变频接收机的低功耗混合信号直流失调消除(DCOC)电路。该电路采用混合信号的方式消除直流失调电压,避免了传统模拟域直流失调消除系统环路响应速度与高通带宽之间的折中,具有功耗低、建立时间快、面积小等优点。采用该DCOC后,直接变频接收机的输出剩余直流失调电压小于37mV,直流失调消除环路的建立时间小于200μs。电路采用0.13μm CMOS工艺实现,芯片尺寸为0.372mm×0.419mm,工作于1.2V电源电压时,消耗电流仅为196μA。     

A low power mixed signal DC offset calibration circuit for direct conversion receiver applications

A low power mixed signal DC offset calibration(DCOC) circuit for direct conversion receiver applications is designed.The proposed DCOC circuit features low power consumption,fast settling time and a small die area by avoiding the trade-off between loop response time and the high pass frequency of the DCOC servo loop in conventional analog DCOC systems.By applying the proposed DC offset correction circuitry,the output residue DC offset voltages are reduced to less than 38 mV and the DCOC loop settling time is less than 100μs.The DCOC chip is fabricated in a standard 0.13-μm CMOS technology and drains only 196μA from a 1.2-V power supply with its chip area of only 0.372×0.419 mm~2.     

0.5 V CMOS inverter-based tunable transconductor

A new technique for CMOS inverter-based tunable transconductors is proposed in this paper. The proposed technique employs the master–slave approach and offers large transconductance tuning range using a control current. The transconductor was designed using triple-well 0.13 μm CMOS process under the ultra low supply voltage of 0.5 V. The circuit features 37 dB open loop gain, CMRR = 31 dB at each output node, PSRR = 90 dB and GBW = 530 MHz for 120 μA current consumption.     

A very compact, 0.4 V DTMOS CCII employed in an audio-frequency filter

This paper presents an ultra low-voltage, ultra low-power, very compact, dynamic threshold voltage MOS transistor (DTMOS)-based CCII circuit. The proposed circuit is capable of operating under ± 0.2 V symmetric supply voltages. The circuit topology is very compact and consists of only four DTMOS transistors and four ordinary NMOS transistors. The total power consumption of the circuit is found as only 214 nW while all transistors are working in the subthreshold region. The current conveyor has 570 kHz 3 dB-bandwidth from X to Y terminal for the voltage gain and has low, 0.2 % following error between these terminals for inputs not exceeding ± 60 mV. TSMC 0.18 µm process technology parameters are used in the design of the proposed CCII block which is then employed in an audio-frequency, second-order, band-pass filter configuration where real speech signals are fed to the input of the filter to further investigate its characteristics. Close agreement is found between theoretical study and simulated responses.     

A 6 Gb/s transmitter with data-dependent jitter reduction technique for displayport physical layer

In this paper, a 6 Gb/s transmitter with data-dependent jitter (DDJ) reduction technique for DisplayPort physical layer is presented. We propose a novel technique to minimize DDJ introduced while the output driver is operating with pre-emphasis mode, which is called DDJ reduction technique. The output driver circuit is designed in 0.13 μm 1P6 M CMOS process and fully compliant to the DisplayPort standard. With the proposed technique, observed DDJ at the output of the driver is reduced from 10 ps to under 1 ps while the output driver producing 400 mV output swing with 6 dB pre-emphasis. The output driver consumes minimum 66 mW and adopts 1.2 V supply voltage for core and 3.3 V supply voltage for I/O including pre-drivers.