A high efficiency transmitter and receiver for magnetic resonant wireless battery charging system in 0.35 μm BCD

This paper presents a transmitter and receiver for magnetic resonant wireless battery charging system. In the receiver, a wide-input range CMOS multi-mode active rectifier is proposed for a magnetic resonant wireless battery charging system. The configuration is automatically changed with respect to the magnitude of the input AC voltage. The output voltage of the multi-mode rectifier is sensed by a comparator. Furthermore, the configuration of the multi-mode rectifier is automatically selected by switches as original rectifier mode, 1-stage voltage multiplier or 2-stage voltage multiplier mode. As a result, a rectified DC voltage is output from 7.5 to 19 V for an input AC voltage of 5–20 V. In the transmitter, a class-E power amplifier (PA) with an automatic power control loop and load compensation circuit is proposed to improve the power efficiency. The transmitted power is controlled by adjusting the signal applied to the gate of the power control transistor. In addition, a parallel capacitor is also controlled to enhance the efficiency and compensate for the load variation. This chip is implemented using 0.35 μm BCD technology with an active area of around 5,000 × 2,500 μm. When the magnitude of the input AC voltage is 10 V, the power conversion efficiency of the multi-mode active rectifier is about 94 %.The maximum power efficiency of the receiver is about 70 %. The transmitter provides an output power control range of 10–30.2 dBm. The maximum power efficiency of the PA is 71.5 %.     

A compact 1–30 μH, 1–350 μF, 5–50 mΩ ESR compliant, 1.5% accurate 0.6 μm CMOS differential ΣΔ boost dc–dc converter

Emerging high-end portable electronics demand on-chip integration of high-performance dc–dc power supplies not only to save pin count, printed circuit board (PCB) real estate, and the cost of off-chip components but also to better regulate the point of load (PoL). In the face of a widely variable LC filter, however, integrating the frequency-compensation circuit is difficult without sacrificing stability performance, which is why integrated controller ICs only cater to relatively narrow LC ranges. While ΣΔ control addresses this LC compliance issue in buck dc–dc converters with high equivalent series resistance (ESR) output capacitors, it is not clear how it applies to ΣΔ boost converters. To that end, this paper discusses, analyzes, and experimentally evaluates a prototyped 0.6 μm CMOS differential ΣΔ boost converter. Experimental results verified the switching supply was stable across 1–30 μH, 1–350 μF, and 5–50 mΩ of inductance, capacitance, and ESR while keeping output voltage variations in response to 0.1–0.8 A load and 2.7–4.2 V line changes to less than ±1.5%, peak efficiency at 95%, and switching frequency variation to less than 27%.     

Temperature compensated and gated CMOS ring oscillator for time-to-digital converter application

This paper presents a CMOS voltage controlled ring oscillator with temperature compensation for low power time-to-digital converters (TDCs). In order to maintain the oscillation frequency stable, a novel compensation circuit is proposed through adaptively sensing temperature variations. This design has been implemented in TSMC 0.35 μm CMOS standard process with an active area of under 0.039 mm². Experimental results show that the clock frequency is around 159.0 MHz only with a power consumption of 550 μA. As respective to the room temperature the maximum frequency variation is between ?3.46 and +3.08 % under temperature range of ?40 to 85 °C. The bit error time induced by clock jitter is limited within 4.8 % in the whole clock period, and the differential nonlinearity of the TDC is less than 0.408 LSB.     

A transient enhanced DVS DC–DC converter based on state trajectory analysis

Dynamic voltage scaling (DVS) can effectively reduce energy consumption by dynamically varying the supply voltage of the system accordingly to the clock frequency. A new DVS-enabled DC–DC converter is presented in this paper. State trajectory is employed to analyze the transient features of PWM and PFM Buck converters. A novel transient enhancement circuit is designed to improve the transient response of the DVS-enabled Buck converter. To further expand the output voltage range of the converter, a current-starved voltage controlled delay line is proposed in the controller of DC–DC converter to obtain an ultra low voltage of 0.5 V. When the input voltage is 3.3 V, the output voltage of the converter can be dynamically regulated from 0.5 to 2.0 V. The output voltage tracking speed is less than 7.5 μs/V and the recovery speed is 33 μs/A for a load current step from 0.6 to 0.2 A at output voltage of 0.5 V. The chip area is 1.75 mm × 1.33 mm in a 0.18 μm standard CMOS process.     

Sub 1-V highly-linear low-power class-AB bulk-driven tunable CMOS transconductor

This paper describes the design and realization of a sub 1-V low power class-AB bulk-driven tunable linear transconductor using a 0.18-μm CMOS technology. The proposed transconductor employs a class-AB bulk-driven differential input voltage follower and a passive resistor to achieve highly linear voltage-to-current conversion. Transconductance tuning is achieved by tuning the differential output current of the core transconductor with gain-adjustable current mirrors. With 10.4-μA current consumption from a 0.8-V single power supply voltage, simulation results show that the proposed transconductor achieves the total harmonic distortion (THD) of <?40 dB for a peak differential input voltage range of 800 mV at frequencies up to 10 kHz. The simulated input-referred noise voltage integrated over 10-kHz bandwidth is 100 μV, resulting to an input signal dynamic range of 75 dB for THD <?40 dB. A biquadratic G_m-C filter is designed to demonstrated the performance of the proposed transconductor. At the nominal 10-kHz cut-off frequency, the filter dissipates 34.4 μW from a 0.8-V supply voltage and it achieves an input signal dynamic range of 67.4 dB for the third-order intermodulation distortion of <?40 dB.     

Wide input range,high-efficiency magnetic resonant wireless power receiver

This article presents a full-CMOS receiver for magnetic resonant wireless battery charging system. A wide-input range CMOS multi-mode active rectifier is proposed for a magnetic resonant wireless battery charging system. The configuration is automatically changed with respect to the magnitude of the input AC voltage. The output voltage of the multi-mode rectifier is sensed by a comparator. Furthermore, the configuration of the multi-mode rectifier is automatically selected by switches as original rectifier mode, one-stage voltage multiplier or two-stage voltage multiplier mode. As a result, a rectified DC output voltage is from 7.5 to 19 V for an input AC voltage of 5–20 V. This chip is implemented using 0.35 μm BCD technology with an active area of around 5 × 2.5 mm². When the magnitude of the input AC voltage is 10 V, the power conversion efficiency of the multi-mode active rectifier is about 94%.The efficiency of the receiver is about 60% when the distance between the transmitter and receiver is about 1 m.     

Equalization and pre-emphasis based LVDS transceiver

This work presents an area-efficient, low-power, high data rate low voltage differential signal (LVDS) transmitter and receiver with signal quality enhancing techniques. The proposed common mode feedback scheme significantly reduces the size of the LVDS transmitter by eliminating the use of area consuming passive resistor and capacitor used for close loop stability compensation. A preemphasis technique has been introduced to enhance the transmitter output’s signal quality without significantly increasing the power draw. On the receiver part, an equalization technique has also been introduced to further enhance signal quality, increases data rate and improved jitter with relatively low power consumption. The LVDS transmitter consumes 5.4 mA of current while driving an external 100 ohm resistor with an output voltage swing of 440 mV. The chip consumes an area of 0.044 mm². This LVDS receiver has an input common mode range from 0.1 to 1.6 V. It consumes 34 mW of power with a maximum data rate of 2 Gbps. It consumes an area of 0.147 mm² a jitter of 11.74 ps rms. A test chip is implemented using 0.18 μm CMOS process.     

A Temperature Compensated CMOS Ring Oscillator for Wireless Sensing Applications

This paper presents a CMOS voltage controlled ring oscillator (VCO) with temperature compensation circuit suitable for low-cost and low-power MEMS gas sensor. This compensated ring oscillator is dedicated to Chopper Stabilized CMOS Amplifier (CHS-A). To operate at low frequency, a control voltage generated by a CMOS bandgap reference (BGR) is described and the measurement results of the fabricated chips are presented. The output voltage of the reference is set by resistive subdivision. In order to achieve small area and low power consumption, n-well resistors are used. This design features a reference voltage of 1 V. The chip is fabricated in AMS 0.35 μm CMOS process with an area of 0.032 mm². Operating at 1.25 V, the output frequency is within 200?±?l0 kHz over the temperature range of ?25 °C to 80 °C with power consumption of 810 μW.     

Inductor-less PVT robust gain switching balun LNA for multistandard applications

An inductor-less single to differential low-noise amplifier (LNA) is proposed for multistandard applications in the frequency band of 0.2–2 GHz. The proposed LNA incorporates noise cancellation and voltage shunt feedback configuration to achieve minimum noise characteristics and low power consumption. In addition to noise cancellation, trans-conductance of common-source stage is scaled to improve the noise performance. In this way, noise figure (NF) of LNA below 3 dB is achieved. An additional capacitor C_c is used to correct the gain and phase imbalance at the output. The gain switching has been enabled with a step size of 4 dB for high linearity and power efficiency. The bias point of all transistors is chosen such that the variation in g_m is not more than 10%. The proposed LNA is implemented in UMC 0.18-μm RF CMOS technology. The core area is 182 μm × 181 μm. Moreover, the LNA has better ratio of relevant performance to area. The proposed balun LNA is validated by rigorous Monte Carlo simulation. The 3σ deviation of gain and NF is less than 5%. Finally, the proposed LNA is robust to unavoidable PVT variations.     

A continuous conduction mode low-ripple high-efficiency charge-pump boost converter

In this paper, a new continuous conduction mode (CCM) low-ripple high-efficiency charge-pump boost converter is presented. Its components include a double voltage charge pump and a low pass LC filter. The voltage boost ratio of the positive low-ripple output voltage of the proposed converter is (1 + D) where D is the duty cycle of the control switching signal waveform. Since the energy storage inductor is connected to the power source and the load at all times, the proposed converter always operates in CCM, the transient responses are fast, and the current stress on the output capacitor is reduced and the output voltage ripple is small. In this paper, the operation principles of the CCM low-ripple high-efficiency charge-pump boost converter are described in detail. Its circuitry is designed and implemented with a TSMC 0.35 μm CMOS processes whose operation frequency is 1 MHz. The circuitry is simple and the power conversion efficiency is up to 90.95 %, and the transient response is only 7 μs.     

A high CMRR, class AB, fully differential current output stage

A true class ‘AB’ fully differential current output stage with very high common mode rejection ratio is presented in this study. The operational principle of this unique structure is discussed, its most important formulas are derived and its outstanding performance is verified by SPICE simulation in TSMC 0.18 μm CMOS, and Level49 technology. Owing to the elaborately arranged components, the proposed circuit demonstrates very high common-mode rejection ratio (CMRR), high slew rate, high current drive capability, high output compliance, and very low power consumption while operating at power supply of ±0.9 V. The interesting results such as current drive capability of ±100 μA, high output voltage swing of ±0.8 V, low static power consumption of 21 μW, and very high CMRR of 84.5 dB is achieved utilizing standard CMOS technology. The performance of circuit at the presence of process and voltage variations evaluated through corner case and Monte Carlo analysis. The harmonic distortion is evaluated to investigate the circuit’s linearity. The transient stepwise response analysis is also done to verify the stability of proposed class ‘AB’ FDCOS.     

An ANFIS based fuzzy controller for corner compensation

As threshold voltage of CMOS transistors is the main parameter that takes effect from process variations, in this paper a novel method for corner detection is presented which senses the variations of fabrication process through threshold voltage of the devices. A new general purpose 2-input, 2-output, 25 rules, ANFIS based fuzzy controller is proposed to compensate the variations subsequently. In this controller novel structures are presented for each block including membership function generator, Min–Max selector and defuzzifier. As an application, bias points of comparators of a typical flash ADC are controlled through introduced system in order to compensate the process variation effects and minimizing total power consumption consequently. Due to differential structures used in the architecture of the blocks, major part of the power supply noise is rejected. The Hspice (level 49) simulation results are given using a generic 0.35 μm standard CMOS technology parameters and power supply of 3.3 V with total power consumption of 15.6 mW for 7.4 MFLIPS. Because of simple and symmetrical circuitry, layout of the proposed controller is very compact, about 410 μm × 210 μm.     

Temperature compensated CMOS ring VCO for MEMS gas sensor

This paper presents a CMOS voltage controlled ring oscillator with temperature compensation circuit suitable for low-cost and low-power gas sensor. To operate at low frequency, a control voltage generated by a CMOS bandgap reference is described and the measurement results of the fabricated chips are presented. The output voltage of the reference is set by resistive subdivision. In order to achieve small area and low power consumption, n-well resistors are used. This design features a reference voltage of 1 V. The chip is fabricated in AMS 0.35 μm CMOS process with an area of 0.032 mm². Operating at 1.25 V, the output frequency is within 200 ± l0 kHz over the temperature range of ?25 to 80 °C with a power consumption of 810 μW.     

A small area 8 bits 50 MHz CMOS DAC for Bluetooth transmitter

This paper presents a small-area CMOS current-steering segmented digital-to-analog converter (DAC) design intended for RF transmitters in 2.45 GHz Bluetooth applications. The current-source design strategy is based on an iterative scheme whose variables are adjusted in a simple way, minimizing the area and the power consumption, and meeting the design specifications. A theoretical analysis of static-dynamic requirements and a new layout strategy to attain a small-area current-steering DAC are included. The DAC was designed and implemented in 0.35 μm CMOS technology, requiring an active area of just 200 μm × 200 μm. Experimental results, with a full-scale output current of 700 μA and a 3.3 V power supply, showed a spurious-free dynamic range of 58 dB for a 1 MHz output sine wave and sampling frequency of 50 MHz, with differential and integral nonlinearity of 0.3 and 0.37 LSB, respectively.     

A 0.7 V 6.66–9.36 GHz wide tuning range CMOS LC VCO with small chip size

The circuit designs are based on TSMC 0.18 μm CMOS standard technology model. The designed circuit uses transformer coupling technology in order to decrease chip area and increase the Q value. The switched-capacitor topology array enables the voltage-controlled oscillator (VCO) to be tuned between 6.66 and 9.36 GHz with 4.9 mW power consumption at supply voltage of 0.7 V, and the tuning range of the circuit can reach 33.7%. The measured phase noise is ?110.5 dBc/Hz at 1 MHz offset from the carrier frequency of 7.113 GHz. The output power level is about ?1.22 dBm. The figure-of-merit and figure-of-merit-with-tuning range of the VCO are about ?180.7 and ?191.25 dBc/Hz, respectively. The chip area is 0.429 mm² excluding the pads. The presented ultra-wideband VCO leads to a better performance in terms of power consumption, tuning range, chip size and output power level for low supply voltage.     

A wide supply voltage range and low-power all-digital clock generator

This study presents a low-power all-digital clock generator (ADCG) for a wide supply voltage range system. The proposed ADCG limits the maximum supply current to 100 μA at a supply voltage ranging from 1.6 to 3.6 V. The ADCG also uses a digitally controlled oscillator (DCO) to extend its operational frequency range. The proposed DCO controls the supply current and divider circuits for a wide supply voltage range. The output duty cycle of ADCG falls within 50 ± 1.9 % using a duty cycle corrector. The maximum peak-to-peak jitter is less than 2.7 % at 8.38 MHz for a digital water meter application (DWM). The operational frequencies of 1.45 and 8.38 MHz at 1.8 V are 3.1 and 36.7 μA, respectively. The core area of ADCG is 0.14 mm² for a 0.35 μm CMOS process. The operational frequency of ADCG ranges from 4.5 to 9.2 MHz at a supply voltage ranging from 1.6 to 3.6 V. This clock generator can also be applied to microcontroller applications.     

CMOS integrated MPP tracker with analog power measurement at the PV converter input

An integrated converter controller with maximum power point (MPP) regulation in 0.35 μm CMOS for photovoltaic (PV) applications is reported. The implemented MPP tracker bases on a perturb and observe algorithm and acquires the information concerning the power flow via an analog processing circuit which is connected at the switched mode converter input respectively the output of the attached PV string of nine cells. There the solar cell current is measured via a very low-ohmic shunt resistor of 1 mΩ and analogously multiplied with the cell voltage. As output the fabricated test chip directly generates a 530 kHz PWM signal for the external switched mode converter. Measurements show that under similar conditions analog MPP tracking of the converter input power improves the robustness with respect to settling times of the power path compared to those topologies at which the power is measured at the converter output. Between 0.4 and 7.5 A photocurrent the chip achieves tracking efficiencies better than 99.5 % while the power consumption is only 750 μW and a very low chip area demand of 0.043 mm² for the MPP tracking core is achieved.     

A fully-differential OTA based on CMOS cascode inverters operating from 1-V power supply

A low voltage operating fully-differential CMOS OTA construction, which uses dual-input CMOS cascode inverters, is proposed. The OTA is a two-stage configuration with dual-input CMOS cascode inverters at the input stage, and traditional CMOS inverters in the output stage, with a common-mode feedback path from the output terminals to one of the input terminals of cascode inverters. In order to effectively reduce its threshold voltages by bulk bias technique, the OTA has been designed and fabricated by using a 0.15 μm triple-well CMOS process. The OTA successfully operated from 1-V power supply, with 59 dB of differential voltage gain, 80.9 dB of CMRR and 25 MHz of unity gain frequency, at 60 μA of current consumption.     

A novel monolithic white LED driver with dual dimming mode

This paper presents a hysteretic-current-control LED driver with the dual dimming mode. This novel monolithic driver includes an output switch and a high-side output current sensing circuit using an external resistor to set the nominal average output current (I_OUTnom). By applying an external control signal to the DIM pin, it can alter flexibly the control mode between the analog (DC) and switching (PWM) dimming. In the DC dimming mode, when the input DC control voltage is adjusted from 0.5 to 2.5 V, the average output current can be changed from 20 to 100 % of the current I_OUTnom. While in the switching dimming mode, the output current is proportional to the duty cycle of the input switching signal and changed from about 0 to 100 % of the current I_OUTnom. The driver circuit has been verified in a 0.5 μm HVCMOS process and the die size is about 1.2 × 1.5 mm². This proposed driver can work in 8–40 V power supply, the maximum average output current is up to 1.0 A.     

A wide frequency range delay line for fast-locking and low power delay-locked-loops

A voltage controlled delay cell with wide frequency range is presented in this paper. The delay-line which is resulted by connecting five series of delay cells generating a wide range of delay from 1.9 to 13.24 ns. It can be used in an analog delay locked loop. The linear characteristic of the circuit with respect to the conventional delay line structures is improved, and a better performance of noise is obtained using differential structure. This circuit is designed by ADS software and TSMC CMOS 0.18 μm technology, with supply voltage 1.8 V. By changing control voltage from 0.335 to 1.8 V in delay line, a wide range of frequency from 75.52 to 917.43 MHz will be covered. Simulation results show that the proposed delay line has power consumption of maximum 3.77 mW at frequency of 75.52 MHz. It also shows that increasing of frequency will reduce power dissipation which is the one of the main characteristics of this novel circuit. Moreover, the delay locked loop which uses these delay cells has a very high lock speed so that the maximum lock time in just five clock cycles.