Deterministic tests for detecting singleV-coupling faults in RAMs

We consider the problem of detecting singleV-coupling faults (as defined by Nair, Thatte, and Abraham) inn×1 random-access memories (RAMs). First we derive a lower bound of 2 ^V–2 nlog₂ n+(2 ^V +3)n on the length of any test that detects all singleV-coupling faults, for 2V47 andn=2 ^e wheree{8,...,34}. In the derivation we make use of a family of binary codes which we call (n, )-exhaustive codes. We then describe a procedure which, given any (n, V–1)-exhaustive code, constructs a test that detects all singleV-coupling faults, fornV>2. Following this approach, optimal (n,1)- and (n, 2)-exhaustive codes are used to construct S2CTEST and S3CTEST, which are efficient tests of length 10n and 4nlog₂ n+18n that detect all single 2- and 3-coupling faults, respectively. S3CTEST is roughly five times shorter, for current RAM capacities, than Papachristou and Sahgal's test of length 24n[log₂ n]+n. Codes generated according to Tang and Chen are used similarly to construct S4CTEST and S5CTEST, which are tests of approximate length 8.6n(log₂ n)^1.585 and 9.6n(log₂ n)^2.322 that detect all single 4- and 5-coupling faults, respectively. S5CTEST has the interesting property of being able to detect all single physical neighborhood pattern-sensitive faults without requiring the mapping from logical cell addresses to physical cell locations. S5CTEST also detects the scrambled pattern-sensitive fault recently proposed by Franklin and Saluja; moreover, the new test is approximately fourteen times shorter (for 1 and 4 Mbit RAMs) than the test they describe.This work was supported by operating grants from the Central Research Fund of the University of Alberta and the Natural Sciences and Engineering Research Council of Canada under grant OGP0105567.     

Near-optimal tests for classes of write-triggered coupling faults in RAMs

This article is concerned with the detection of write-triggered coupling faults and toggling faults (certain double coupling faults) in n × 1 random-access memories (RAMs), where n is the number of one-bit words in the memory. In an earlier article we showed that any functional test that detects all multiple coupling faults must have a length of at least 2n ² + 3n. Since such a test is prohibitively long, given modern RAM capacities, we study more manageable subclasses of the class of all coupling faults. We show that there exist two hierarchies of fault models corresponding to nested subclasses of toggling faults and coupling faults, respectively, of increasing maximum multiplicities. We then identify optimal or near-optimal tests for two classes of toggling faults and five classes of coupling faults; these tests are of order n or nlog₂ n.This work was supported by the Natural Sciences and Engineering Research Council of Canada under Grants OGP0105567 and OGP0000871, and by the Information Technology Research Centre of Ontario.     

On the generation of test patterns for multiple faults

This article presents a new method to generate test patterns for multiple stuck-at faults in combinational circuits. We assume the presence of all multiple faults of all multiplicities and we do not resort to their explicit enumeration: the target fault is a single component of possibly several multiple faults. New line and gate models are introduced to handle multiple fault effect propagation through the circuits. The method tries to generate test conditions that propagate the effect of the target fault to primary outputs. When these conditions are fulfilled, the input vector is a test for the target fault and it is guaranteed that all multiple faults of all multiplicities containing the target fault as component are also detected. The method uses similar techniques to those in FAN and SOCRATES algorithms to guide the search part of the algorithm, and includes several new heuristics to enhance the performance and fault detection capability. Experiments performed on the ISCAS'85 benchmark circuits show that test sets for multiple faults can be generated with high fault coverage and a reasonable increase in cost over test generation for single stuck-at faults.     

Testing for Bounded Faults in RAMs

We study the class of bounded faults in random-access memories;these are faults that involve a bounded number of cells. This is avery general class of memory faults that includes, for example, theusual stuck-at, coupling, and pattern-sensitive faults, but also manyother types of faults. Some bounded faults are known to requiredeterministic tests of length proportional to n log2 n, where nis the total number of memory cells. The main result of this paper isthat, for any bounded fault satisfying certain very mild conditions,the random test length required for a given level of confidence isalways O(n).     

Efficient Transition Fault ATPG Algorithms Based on Stuck-At Test Vectors

This paper proposes novel algorithms for computing test patterns for transition faults in combinational circuits and fully scanned sequential circuits. The algorithms are based on the principle that s@ vectors can be effectively used to construct good quality transition test sets. Several algorithms are discussed. Experimental results obtained using the new algorithms show that there is a 20% reduction in test set size, test data volume and test application time compared to a state-of-the-art native transition test ATPG tool, without any reduction in fault coverage. Other benefits of our approach, viz. productivity improvement, constraint handling and design data compression are highlighted.     

Trade-offs in scan path and BIST implementations for RAMs

In this article we propose efficient scan path and BIST schemes for RAMs. Tools for automatic generation of these schemes have been implemented. They reduce the design effort and thus allow the designer to select the more appropriate scheme with respect to various constraints.     

Multifault and delay-fault testability of multilevel circuits

This paper investigates the relationship between test sets for multiple stuck-at faults and robust path-delay-fault tests in multilevel combinational circuits. It is shown that, in multilevel circuits, a complete robust path-delay-fault test set may not detect all multiple stuck-at faults. We also show that the detectability of the former does not imply the detectability of the latter, as suggested in a recent paper. The presence of undetectable or untested multiple stuck-at faults may invalidate some path delay tests.Supported in part by NSF Grant MIP-9320886.     

March SR3C: A Test for a reduced model of all static simple three-cell coupling faults in random-access memories

A fault primitive-based analysis of all static simple (i.e., not linked) three-cell coupling faults in n×1 random-access memories (RAMs) is discussed. All realistic static coupling faults that have been shown to exist in real designs are considered: state coupling faults, transition coupling faults, write disturb coupling faults, read destructive coupling faults, deceptive read destructive coupling faults, and incorrect read coupling faults. A new March test with 66n operations able to detect all static simple three-cell coupling faults is proposed. To compare this test with other industrial March tests, simulation results are also presented in this paper.     

Guaranteed fault detection sequences for single transition faults in finite state machine models using concurrent fault simulation

This paper presents a new algorithm for the generation of test sequences for finite state machines. Test sequence generation is based on the transition fault model, and the generation of state-pair distinguishing sequences. We show that the use of state-pair distinguishing sequences generated from a fault-free finite state machine will remain a distinguishing sequence even in the presence of a single transition fault, thus guaranteeing complete single transition fault coverage. Analysis and experimental results show that the complexity of the test sequence generation algorithm is less than those of the previous algorithms. The utility of the transition fault model, and the generated test sequences is shown by their application to sequential logic circuits. These results show more than a factor of 10 improvement in the test generation time and some reduction in test length while maintaining 100% transition fault coverage.Now with Intel Corporation, FM5-161, 1900 Prairie City Road, Folsom, CA 95630.Now with Chrysalis Symbolic Design, 101 Billerica Ave., North Billerica, MA 01862.     

基于FPGA的多路视频通道控制

根据织布机告警系统的需求,提出一种开关设计思想,阐述开关设计过程中遇到的问题以及解决方法。首先在FPGA中设计一个开关控制信号,利用这个信号结合双口RAM中的编码数据识别两个拨动开关状态．从而达到控制多路视频通道的目的,使本告警系统更方便的应用于实际工业中。介绍整个控制系统的工作原理,给出硬件结构图和软件设计过程,然后利用QnartusⅡ中的SignalTapⅡLogic Analyzer工具对控制信号进行实时采样分析．最后在织布机告警系统中成功实现视频通道控制功能。     

光缆故障点的精确定位与成因分析

针对当前排除光缆故障时所存在的问题进行剖析，并相应地提出了解决办法；着重强调了光缆故障发生后，维修人员应在分步测试的基础上，加强对测试曲线的分析，查找其中规律，为今后光缆维护提供故障防范的依据。     

A quasi-optimal scheduling of intermediate signatures for multiple signature analysis compaction testing schemes

In this article, a strategy based on the use of intermediate signatures is proposed that enables the exact fault coverage of compact testing schemes to be determined in a feasible computation time. Two models to predict fault simulation time, a fault simulator dependent and independent model, are developed and used by a dynamic programming based algorithm to find the optimal scheduling of the signatures with respect to the total simulation time. Simulation results for both models are then presented demonstrating the feasibility of the proposed strategy.This work was supported in part by grants from the Natural Sciences and Engineering Research Council (NSERC) of Canada, the Canadian Microelectronics Corporation (CMC) and the British Columbia Advanced Systems Institute (B.C. A.S.I.).     

Testable design of large random access memories

In this paper we propose a method for testable design of large Random Access Memories. The design technique relies on modification of address decoders to achieve multi-writes and multi-reads during test mode. Almost no modification is required in the design of memory array.A number of different designs for decoders are proposed. In all the designs the objective has been to keep the extra hardware for enhancing testability to as small as possible while causing a minimal or no degradation at all in the speed performance of RAM. Use of extra control and observation points is allowed as long as such points cause only a very small increase in the number of extra pins.We also propose the design of decorders in which only a limited number of cells of RAM are written to or read from during test mode.     

An advanced diagnostic method for delay faults in combinational faulty circuits

Due to physical defects or process variations, a logic circuit may fail to operate at the desired clock speed. So, verifying the timing behavior of digital circuits is always necessary, and needs to test for delay faults. When a delay fault has been detected, a specific diagnostic method is required to locate the site of the fault in the circuit. So, a reliable method for delay fault diagnosis is proposed in this paper. Firstly, we present the basic diagnostic method for delay faults, which is based on multivalued simulation and critical path tracing. Next, heuristics are given that decrease the number of critical paths and improve diagnosis results. In the second part of this paper, we provide an approximate method to refine the results obtained with the basic diagnostic process. We compute the detection threshold of the potential delay faults, and use statistical studies to classify the faults from the most likely to be the cause of failure to the less likely. Finally, results obtained with ISCAS'85 circuits are presented to show the effectiveness of the method.     

Detection of Delay Faults in Memory Address Decoders

In this paper we present an efficient test concept for detection of delay faults in memory address decoders based on the march test tactic. The proposed Transition Sequence Generator (TSG) generates an optimal transition sequence for sensitization of the delay faults in address decoders by Hayes's transformation on a reflected Gray code. It can be used for parallel Built-In Self-Testing (BIST) of high-density RAMs. We also present an efficient Design For Test (DFT) approach for immediate detection of the effects of the delay faults in the address decoders which does not change memory access time. It requires extra logic to be attached to the outputs of the address decoders. This DFT approach can be used to increase memory testability for both on-line and off-line testing of single- and multi-port RAMs.     

Concurrent Error Detection in a Bit-Parallel Systolic Multiplier for Dual Basis of GF(2<Superscript><Emphasis Type="Italic">m</Emphasis></Superscript>)

The finite field is widely used in error-correcting codes and cryptography. Among its important arithmetic operations, multiplication is identified as the most important and complicated. Therefore, a multiplier with concurrent error detection ability is elegantly needed. In this paper, a concurrent error detection scheme is presented for bit-parallel systolic dual basis multiplier over GF(2^m) according to the Fenn’s multiplier in [7]. Although, the proposed method increases the space complexity overhead about 27% and the latency overhead about one extra clock cycle as compared to Fenn’s multiplier. Our analysis shows that all single stuck-at faults can be detected concurrently.     

电子产品寿命检测中异常数据的检验

讨论在电子产品的寿命数据中,对同时存在的异常大数据和异常小数据的检验方法,给出了一个明确的判别标准,并以一例说明其应用.     

Performance analysis of MIMO DUCA multiple antenna system

A MIMO multi-antenna system of compact double uniform circular array (DUCA) in three dimensional direc-tional frequency non-selective Rayleigh fading channel was analyzed and investigated. Equivalent network model of MIMO multi-antenna array considering MC effect was established, general expressions of correlations were derived and the relationship between correlations with and without MC was classfied. Then, the results were compared with general uniform linear array (ULA) and uniform circular array (UCA). It was concluded that the deployment of antennas plays a decisive role in correlations between antennas. The research has a good sense on designation of spatial massive MIMO multi-antenna array and system optimization.     

An efficient architecture for accumulator-based test generation of SIC pairs

Research conducted over the years has shown that the application of single input change (SIC) pairs of test patterns for sequential, i.e. stuck-open and delay fault testing is extremely efficient. In this paper, a novel architecture for the generation of SIC pairs is presented. The implementation of the proposed architecture is based on Ling adders that are commonly utilized in current data paths due to their high-operating speed. Since the timing characteristics of the adder are not modified, the presented architecture provides a practical solution for the built-in testing of circuits that contain such adders.