辐射加固SOI工艺FPGA的设计与验证

进行了一款辐射加固SRAM基VS1000 FPGA的设计与验证。该芯片包含196个逻辑模块、56个IO模块、若干布线通道模块及编程电路模块等。每个逻辑模块由2个基于多模式4输入查找表的逻辑单元组成,相对传统的4输入查找表,其逻辑密度可以提高12%;采用编程点直接寻址的编程电路,为FPGA提供了灵活的部分配置功能;通过对编程点的完全体接触提高了全芯片的抗辐射能力。VS1000 FPGA基于中电集团第58所0.5μm部分耗尽SOI工艺进行辐射加固设计并流片,样片的辐照试验表明,其抗总剂量水平达到1.0×105rad(Si),瞬态剂量率水平超过1.5×1011rad(Si)/s,抗中子注量水平超过1.0×1014n/cm2。     

辐射加固SOI的SRAM基FPGA中IO模块阵列的设计与实现

本文中我们提出了一个用于辐射加固的SRAM基FPGA VS100的输入输出模块阵列,该FPGA用0.5微米部分耗尽SOI工艺设计,在中电集团58所流片。与FPGA的特性一致,每一个IO单元都由布线资源和两个IOC组成,IOC包括信号通路电路,可编程输入/输出驱动器和ESD保护网络组成。IO模块能用于不同的工作模式时,边界扫描电路既可以插入在输入输出数据路径电路和驱动器之间,也可以作为透明电路。可编程IO驱动器使IO模块能够用于TTL和CMOS电平标准。布线资源使得IO模块和内部逻辑之间的连接更加灵活和方便。辐射加固设计,包括A型体接触晶体管,H型体接触晶体管和特殊的D触发器的设计提高了抗辐射性能。ESD保护网络为端口上的高脉冲提供了放电路径,防止大电流损坏内部逻辑。这些设计方法可以适用于不同大小和结构的FPGA设计。IO单元阵列的功能和性能经过了功能测试和辐射测试的考验,辐照实验结果表明,抗总剂量水平超过100Krad(Si), 抗瞬态剂量率水平超过1.510¹¹rad(Si)/s,抗中子注入量水平达到110¹⁴ n/cm²。     

FDP FPGA芯片的设计实现

研究了新型的FDP FPGA电路结构及其设计实现.新颖的基于3输入查找表的可编程单元结构,与传统的基于4输入查找表相比,可以提高约11%的逻辑利用率;独特的层次化的分段可编程互联结构以及高效的开关盒设计,使得不同的互联资源可以快速直接相连,大大提高了可编程布线资源效率.FDP芯片包括1600个可编程逻辑单元、160个可用IO、内嵌16k双开块RAM,采用SMIC 0.18μm CMOS工艺全定制方法设计并流片,其裸芯片面积为6.104mm×6.620mm.最终芯片软硬件测试结果表明:芯片各种可编程资源可以高效地配合其软件正确实现用户电路功能.     

FDP FPGA芯片的设计实现

研究了新型的FDP FPGA电路结构及其设计实现.新颖的基于3输入查找表的可编程单元结构,与传统的基于4输入查找表相比,可以提高约11%的逻辑利用率;独特的层次化的分段可编程互联结构以及高效的开关盒设计,使得不同的互联资源可以快速直接相连,大大提高了可编程布线资源效率.FDP芯片包括1600个可编程逻辑单元、160个可用IO、内嵌16k双开块RAM,采用SMIC 0.18μm CMOS工艺全定制方法设计并流片,其裸芯片面积为6.104mm×6.620mm.最终芯片软硬件测试结果表明:芯片各种可编程资源可以高效地配合其软件正确实现用户电路功能.     

可编程ASIC基本资源的发展趋势

可编程ＡＳＩＣ可以由用户编程实现专门要求的功能是由于其提供了三种可编程资源：１位于芯片中央的可编程功能单元;２位于芯片四周的可编程Ｉ／Ｏ;３．分布在芯片各处的可编程布线资源。可编程ＡＳＩＣ器件要实现芯片上集成系统,还要具有第四种资源一片内ＲＡＭ,本文介绍这些资源及其技术发展趋势。１功能单元当今可配置逻辑器件的功能单元有以下几种。１．１ＲＡＭ查找表在ＳＲＡＭ查找表结构中输入变量作为地址用来从ＲＡＭ存储器中选择数值,ＲＡＭ存储器中预先加载进去要实现函数的真值表数值,因此可以实现输入变量的所有可能的逻…     

一种采用四/五输入可配置查找表结构和优化进位链的新型FPGA

本文提出了一种FPGA可编程逻辑单元中新型的查找表结构和进位链结构。查找表被设计为同时支持四输入和五输入的结构,可根据用户需要进行配置,且不增加使用的互连资源;在新型的进位链中针对关键路径进行了优化。最后在可配置逻辑单元中插入了新设计的可配置扫描链。该可编程逻辑单元电路采用0.13μm 1P8M 1.2/2.5/3.3V Logic CMOS工艺制造。测试结果显示可正确实现四/五输入查找表功能,且进位链传播前级进位的速度在同一工艺下较传统进位链结构提高了约3倍,同时整个可编程逻辑单元的面积较之前增大了72.5%。结果还显示,本文设计的FPGA在仅使用四输入查找表时,逻辑资源利用率高于Virtex II/Virtex 4/Virtex 5/Virtex 6/Virtex 7系列FPGA;在仅使用五输入查找表时,逻辑资源利用率高于Virtex II/Virtex 4系列FPGA。     

FPGA的工作原理及其应用

<正> 现场可编程门阵列(FPGA)是可编程器件。与传统逻辑电路和门阵列(如PAL、GAL及CPLD器件)相比,FPGA具有不同的结构,FPGA利用小型查找表(16×1RAM)来实现组合逻辑;每个查找表连接到一个D触发器的输入端,触发器再来驱动其它逻辑电路或驱动I/O,由此构成了既可实现组合逻辑功能又可实现时序逻辑功能的基本逻辑单元模块;这些模块间利用金属连线互相连接或连接到I/O模块。FPGA的逻辑是通过     

硬件辅助验证产品解读之FPGA开发板vs原型验证系统

<正>在阅读本文之前,读者可以对FPGA芯片的基本含义及原理做基本的了解。FPGA的全称为Field Programmable Gate Array（现场可编程门阵列）,属于专用集成电路中的一种半定制电路,是可编程的逻辑阵列。FPGA的基本结构包括可编程输入输出单元、基本可编程逻辑单元、数字时钟管理模块、嵌入式块RAM、丰富的布线资源、内嵌专用硬核,以及底层内嵌功能单元。     

日盲紫外焦平面探测器的抗辐射加固设计

设计了一款320×256元抗辐射日盲紫外焦平面阵列探测器,重点针对探测器的读出电路版图、积分开关偏置点、探测器芯片外延结构及器件工艺开展了抗辐射加固设计。对加固样品开展了γ总剂量和中子辐照试验和测试,试验结果表明样品的抗电离辐照总剂量达到150krad(Si),抗中子辐照注量达到1×10¹³n/cm²(等效1MeV中子),验证了抗辐射加固措施的有效性。     

具有高资源利用率特征的改进型查找表电路结构与优化方法

该文着重研究了FPGA芯片中核心模块基本可编程逻辑单元(BLE)的电路结构与优化设计方法,针对传统4输入查找表(LUT)进行逻辑操作和算术运算时资源利用率低的问题,提出一种融合多路选择器的改进型LUT结构,该结构具有更高面积利用率;同时提出一种对映射后网表进行统计的评估优化方法,可以对综合映射后网表进行重新组合,通过预装箱产生优化后网表;最后,对所提结构进行了实验评估和验证。结果表明:与Intel公司Stratix系列FPGA相比,采用该文所提优化结构,在MCNC电路集和VTR电路集下,资源利用率平均分别提高了10.428% 和 10.433%,有效提升了FPGA的逻辑效能。     

A radiation-hardened SOI-based FPGA

A radiation-hardened SRAM-based field programmable gate array VS 1000 is designed and fabricated with a 0.5 μm partial-depletion silicon-on-insulator logic process at the CETC 58th Institute.The new logic cell (LC),with a multi-mode based on 3-input look-up-table (LUT),increases logic density about 12％ compared to a traditional 4-input LUT.The logic block (LB),consisting of 2 LCs,can be used in two functional modes:LUT mode and distributed read access memory mode.The hierarchical routing channel block and switch block can significantly improve the flexibility and routability of the routing resource.The VS1000 uses a CQFP208 package and contains 392 reconfigurable LCs,112 reconfigurable user I/Os and IEEE 1149.1 compatible with boundaryscan logic for testing and programming.The function test results indicate that the hardware and software cooperate successfully and the VS 1000 works correctly.Moreover,the radiation test results indicate that the VS 1000 chip has total dose tolerance of 100 krad(Si),a dose rate survivability of 1.5 × 1011 rad(Si)/s and a neutron fluence immunity of 1 × 1014 n/cm2.     

An Efficient Look-up Table-based Approach for Multiplication over GF(2 m ) Generated by Trinomials

In this paper, we present an efficient look-up table (LUT)-based approach to design multipliers for GF(2 ^m ) generated by irreducible trinomials. A straightforward LUT-based multiplication requires a table of size (m×2 ^m ) bits for the Galois field of degree m. The LUT size, therefore, becomes quite large for the fields of large degrees recommended by the National Institute of Standards and Technology (NIST). Keeping that in view, we have proposed a digit-serial LUT-based design, where operand bits are grouped into digits of fixed width, and multiplication is performed in serial/parallel manner. We restrict the digit size to 4 to store only 16 words in the LUT to have lower area-delay complexity. We have also proposed a digit-parallel LUT-based design for high-speed applications, using the same LUT as the digit-serial design, at the cost of some additional multiplexors and combinational logic for parallel modular reductions and additions. We have presented a simple circuit for the initialization of LUT content, which can be used to update the LUT in three cycles whenever required. The proposed digit-serial design involves less area-complexity and less time-complexity than those of the existing LUT-based designs. The proposed digit-parallel design offers nearly 28 % improvement in area-delay product over the best of the existing LUT-based designs. NIST has recommended five binary finite fields for elliptic curve cryptography, out of which two are generated by the trinomials Q(x)=x ²³³+x ⁷⁴+1 and Q(x)=x ⁴⁰⁹+x ⁸⁷+1. In this paper, we have designed a reconfigurable multiplier that can be used for both these fields. The proposed reconfigurable multiplier is shown to have a negligible reconfiguration overhead and would be useful for cryptographic applications.     

PVHArray:一种流水可伸缩的层次化可重构密码逻辑阵列结构

针对密码算法的高效能实现问题,该文提出了一种基于数据流的粗粒度可重构密码逻辑阵列结构PVHArray.通过研究密码算法运算及控制结构特征,基于可重构阵列结构设计方法,提出了以流水可伸缩的粗粒度可重构运算单元、层次化互连网络和面向周期级的分布式控制网络为主体的粗粒度可重构密码逻辑阵列结构及其参数化模型.为了提升可重构密码逻辑阵列的算法实现效能,该文结合密码算法映射结果,确定模型参数,构建了规模为4×4的高效能PVHArray结构.基于55nm CMOS工艺进行流片验证,芯片面积为12.25mm²,同时,针对该阵列芯片进行密码算法映射.实验结果表明,该文提出高效能PVHArray结构能够有效支持分组、序列以及杂凑密码算法的映射,在密文分组链接（CBC）模式下,相较于可重构密码逻辑阵列REMUS_LPP结构,其单位面积性能提升了约12.9%,单位功耗性能提升了约13.9%.     

Design and analysis of a dynamically reconfigurablethree-dimensional FPGA

This paper presents the design and analysis of a dynamically reconfigurable field programmable gate array (FPGA) that consists of three physical layers: routing and logic block layer, routing layer, and memory layer. The architecture was developed using a methodology that examines different architectural parameters and how they affect different performance criteria such as speed, area, and reconfiguration time. The resulting architecture has high performance while the requirement of balancing the areas of its constituent layers is satisfied     

Low-power compact composite field AES S-Box/Inv S-Box design in 65 nm CMOS using Novel XOR Gate

The Substitution box (S-Box) forms the core building block of any hardware implementation of the Advanced Encryption Standard (AES) algorithm as it is a non-linear structure requiring multiplicative inversion. This paper presents a full custom CMOS design of S-Box/Inversion S-Box (Inv S-Box) with low power GF (2⁸) Galois Field inversions based on polynomial basis, using composite field arithmetic. The S-Box/Inv S-Box utilizes a novel low power 2-input XOR gate with only six devices to achieve a compact module implemented in 65 nm IBM CMOS technology. The area of the core circuit is only about 288 μm² as a result of this transistor level optimization. The hardware cost of the S-Box/Inv S-Box is about 158 logic gates equivalent to 948 transistors with a critical path propagation delay of 7.322 ns enabling a throughput of 130 Mega-SubBytes per second. This design indicates a power dissipation of only around 0.09 μW using a 0.8 V supply voltage, and, is suitable for applications such as RFID tags and smart cards which require low power consumption with a small silicon die. The proposed implementation compares favorably with other existing S-Box designs.     

A nonvolatile programmable solid-electrolyte nanometer switch

A reconfigurable LSI employing a nonvolatile nanometer-scale switch, NanoBridge, is proposed, and its basic operations are demonstrated. The switch, composed of solid electrolyte copper sulfide, has a <30-nm contact diameter and <100-/spl Omega/ on-resistance. Because of its small size, it can be used to create extremely dense field-programmable logic arrays. A 4 /spl times/ 4 crossbar switch and a 2-input look-up-table circuit are fabricated with 0.18-/spl mu/m CMOS technology, and operational tests with them have confirmed the switch's potential for use in programmable logic arrays. A 1-kb nonvolatile memory is also presented, and its potential for use as a low-voltage memory device is demonstrated.     

A resource-efficient and scalable wireless mesh routing protocol

By binding logic addresses to the network topology, routing can be carried out without going through route discovery. This eliminates the initial route discovery latency, saves storage space otherwise needed for routing table, and reduces the communication overhead and energy consumption. In this paper, an adaptive block addressing (ABA) scheme is first introduced for logic address assignment as well as network auto-configuration purpose. The scheme takes into account the actual network topology and thus is fully topology-adaptive. Then a distributed link state (DLS) scheme is further proposed and put on top of the block addressing scheme to improve the quality of routes, in terms of hop count or other routing cost metrics used, robustness, and load balancing. The network topology reflected in logic addresses is used as a guideline to tell towards which direction (rather than next hop) a packet should be relayed. The next hop is derived from each relaying node’s local link state table. The routing scheme, named as topology-guided DLS (TDLS) as a whole, scales well with regard to various performance metrics. The ability of TDLS to provide multiple paths also precludes the need for explicit route repair, which is the most complicated part in many wireless routing protocols. While this paper targets low rate wireless mesh personal area networks (LR-WMPANs), including wireless mesh sensor networks (WMSNs), the TDLS itself is a general scheme and can be applied to other non-mobile wireless mesh networks.     

Using the Minimum Set of Input Combinations to Minimize the Area of Local Routing Networks in Logic Clusters Containing Logically Equivalent I/Os in FPGAs

Mapping digital circuits onto field-programmable gate arrays (FPGAs) usually consists of two steps. First, circuits are mapped into look-up tables (LUTs). Then, LUTs are mapped onto physical resources. The configuration of LUTs is usually determined during the first step and remains unchanged throughout the second. In this paper, we demonstrate that by reconfiguring LUTs during the second step, one can increase the flexibility of FPGA routing resources. This increase in flexibility can then be used to reduce the implementation area of FPGAs. In particular, it is shown that, for a logic cluster with $ I$ inputs and $ N$ $ k$-input LUTs, a set of $Ntimes kquad (I+N-k+1):1$ multiplexers can be used to connect logic cluster inputs to LUT inputs while maintaining logic equivalency among the logic cluster I/Os. The multiplexers (called a local routing network) are shown to be the minimum required to maintain logic equivalency. Comparing to the previous design, which employs a fully connected local routing network, the proposed design can reduce logic cluster area by 3%–25% and can reduce a significant amount of fanouts for logic cluster inputs.