TiN/TaN 厚度变化对nMOSCAP栅叠层有效功函数的影响

We evaluated the TiN/TaN/TiA1 triple-layer to modulate the effective work function （EWF） of a metal gate stack for the n-type metal-oxide-semiconductor （NMOS） devices application by varying the TiN/TaN thickness. In this paper, the effective work function of EWF ranges from 4.22 to 4.56 eV with different thicknesses of TiN and TaN. The thinner TiN and/or thinner in situ TaN capping, the closer to conduction band of silicon the EWF is, which is appropriate for 2-D planar NMOS. Mid-gap work function behavior is observed with thicker TiN, thicker in situ TaN capping, indicating a strong potential candidate of metal gate material for replacement gate processed three-dimensional devices such as FIN shaped field effect transistors. The physical understandings of the sensitivity of EWF to TiN and TaN thickness are proposed. The thicker TiN prevents the A1 diffusion then induces the EWF to shift to mid-gap. However, the TaN plays a different role in effective work function tuning from TiN, due to the Ta-O dipoles formed at the interface between the metal gate and the high-k layer.     

CMOS器件及其结构缺陷的显微红外发光现象研究

CMOS器件结构依靠其较低的功耗和高集成度而广泛应用于集成电路中,它在正常工作和发生失效时均存在微弱的显微红外发光现象。对CMOS结构的显微红外发光现象产生机制进行了研究和实际观察,将对深入了解CMOS器件中各种红外发光效应和分析其可靠性具有实际意义。     

多应力结构CMOS器件的模拟研究

使用TCAD仿真工具Sentaurus在45 nm节点工艺下模拟研究了包含多应力结构的应变Si CMOS器件。模拟所得的开关电流比与相同节点工艺下报道的实验结果能很好吻合,验证了所用模型及方法的正确性。用Sentaurus工艺模拟工具得到了器件内部的应力和掺杂分布,并用Sentaurus器件模拟工具分析了各种应力结构对电学特性的影响。结果表明：在nMOS中,SMT和DSL能有效提高器件性能,而STI却会降低器件性能;在pMOS中,SiGe S/D和DSL的存在是性能改善的主要原因,而STI对性能改善的帮助较小。     

基于标准CMOS工艺的光敏传感单元结构的研究

基于0.6μm标准N阱CM O S工艺,研究了光敏管的结深及其侧墙结构对有源感光单元的感光面积百分比、光电响应信号幅值、感光灵敏度以及感光动态范围等参数的影响。研究了包括传统N+/P衬底的光敏管结构,以及网格状N+/P衬底,N阱/P衬底,网格状N阱/P衬底,P+/N阱/P衬底的光敏管结构。测试结果表明,不同深结深的光敏管结构,可以将器件感光灵敏度提高8~16.5 dB;网格状光敏管结构可以增加光敏管的侧墙面积,改善器件感光灵敏度;非网格状光敏管结构具有较低的暗电流和较大的感光动态范围,其中P+/N阱/P衬底光敏管结构的传感单元在变频两次扫描的工作方式下的感光动态范围可达139.8 dB。     

基于应变Si/SiGe的CMOS电特性模拟研究

提出了一种应变Si/SiGe异质结CMOS结构,采用张应变Si作n-MOSFET沟道,压应变SiGe作p-MOSFET沟道,n-MOSFET与p-MOSFET采用垂直层叠结构,二者共用一个多晶SiGe栅电极.分析了该结构的电学特性与器件的几何结构参数和材料物理参数的关系,而且还给出了这种器件结构作为反相器的一个应用,模拟了其传输特性.结果表明所设计的垂直层叠共栅结构应变Si/SiGe HCMOS结构合理、器件性能提高.     

以非晶硅为硬掩膜的TaN金属栅的选择性湿法腐蚀

提出了一种在HfSiON介质上,采用非晶硅为硬掩膜的选择性去除TaN的湿法腐蚀工艺。由于SC1(NH4OH:H2O2:H2O)对金属栅具有合适的腐蚀速率且对硬掩膜和高K材料的选择比很高,所以选择它作为TaN的腐蚀溶液。与光刻胶掩膜和TEOS硬掩膜相比,因非晶硅硬掩膜不受SC1溶液的影响且很容易用NH4OH溶液去除（NH4OH溶液对TaN和HfSiON薄膜无损伤）,所以对于在HfSiON介质上实现TaN的选择性去除来说非晶硅硬掩膜是更好的选择。另外,在TaN金属栅湿法腐蚀和硬掩膜去除后, 高K介质的表面是光滑的,这可防止器件性能退化。因此,采用非晶硅为硬掩膜的TaN湿法腐蚀工艺可以应用于双金属栅集成,实现先淀积的TaN金属栅的选择性去除。     

用于太赫兹成像的CMOS肖特基二极管三维结构

提出了一种简单、科学、有效的高截止频率肖特基势垒二极管设计方法。通过SMIC 180 nm工艺制备的肖特基二极管的截止频率为800 GHz,分析测试结果和仿真数据优化后的肖特基势垒二极管截止频率可以达到1 THz左右。完成了包括天线、匹配电路和肖特基势垒二极管的集成探测器,在220 GHz下其测试响应率可达130 V/W,等效噪声功率估计为400 pw/。完成了陶瓷瓶内不可见液面的成像实验并取得了良好的效果。     

沟槽栅功率器件栅氧化膜特性的工艺研究

本文分析了沟槽栅功率器件中对栅氧化膜特性造成影响的主要工艺因素,报告了一种获得高性能栅氧特性的方法,并且对栅氧化膜特性改善的机理进行了研究。对于厚度55nm的沟槽栅氧化膜,其正向偏置和反向偏置下的击穿电压都高于30伏特。     

CMOS LC VCO中交叉耦合MOS管的结构和特点

在近年来的文献报道中,CMOS LC VCO中交叉耦合MOS管的电路结构变化多端.在不同的设计中,MOS管的类型、数目和连接方式有很多不同的结构.从其基本结构出发总结这些结构,就不同结构MOS管电路对振荡器性能做了简要分析.着重介绍了近年来在理论认识,低电压、低相位噪声和宽频率覆盖设计方面所做的努力.     

基于TMD材料的CMOS反相器电路研究现状

对目前基于过渡金属硫族化合物(TMD)材料(MoS2、WSe2等)的互补金属氧化物半导体(CMOS)反相器电路相关研究进行了综述.总结了TMD材料的物理性质、制备方法和基于TMD的场效应晶体管器件的研究进展.对基于TMD的集成电路技术研究进行了介绍与分析.分别在结构设计、集成工艺、性能优化及电路集成等方面对基于TMD材...     

Dry etching of poly-Si/TaN/HfSiON gate stack for advanced complementary metal-oxide-semiconductor devices

A novel dry etching process of a poly-Si/TaN/HfSiON gate stack for advanced complementary metal-oxide-semiconductor（CMOS） devices is investigated.Our strategy to process a poly-Si/TaN/HfSiON gate stack is that each layer of gate stack is selectively etched with a vertical profile.First,a three-step plasma etching process is developed to get a vertical poly-Si profile and a reliable etch-stop on a TaN metal gate.Then different BCl₃-based plasmas are applied to etch the TaN metal gate and find that BCl₃/Cl₂/O₂/Ar plasma is a suitable choice to get a vertical TaN profile.Moreover,considering that Cl₂ almost has no selectivity to Si substrate, BCl₃/Ar plasma is applied to etch HfSiON dielectric to improve the selectivity to Si substrate after the TaN metal gate is vertically etched off by the optimized BCl₃/Cl₂/O₂/Ar plasma.Finally,we have succeeded in etching a poly-Si/TaN/HfSiON stack with a vertical profile and almost no Si loss utilizing these new etching technologies.     

The fabrication and dry etching of poly-Si/TaN/Mo gate stack in the metal inserted poly-Si stack structure

The Mo-based metal inserted poly-Si stack (MIPS) structure is an appropriate choice for metal gate and high-k integration in sub-45 nm gate-first CMOS device. A novel metal nitride layer of TaN or AlN with high thermal stability has been introduced between Mo and poly-Si as a barrier material to avoid any reaction of Mo during poly-Si deposition. After Mo-based MIPS structure is successfully prepared, dry etching of poly-Si/TaN/Mo gate stack is studied in detail. The three-step plasma etching using the Cl₂/HBr chemistry without soft landing step has been developed to attain a vertical poly-Si profile and a reliable etch-stop on the TaN/Mo metal gate. For the etching of TaN/Mo gate stack, two methods using BCl₃/Cl₂/O₂/Ar plasma are presented to get both vertical profile and smooth etched surface, and they are critical to get high selectivity to high-k dielectric and Si substrate. In addition, adding a little SF₆ to the BCl₃/O₂/Ar plasma under the optimized conditions is also found to be effective to smoothly etch the TaN/Mo gate stack with vertical profile.     

Wet etching characteristics of a HfSiON high-k dielectric in HF-based solutions

The wet etching properties of a HfSiON high-k dielectric in HF-based solutions are investigated. HF-based solutions are the most promising wet chemistries for the removal of HfSiON, and etch selectivity of HF-based solutions can be improved by the addition of an acid and/or an alcohol to the HF solution. Due to densification during annealing,the etch rate of HfSiON annealed at 900℃ for 30 s is significantly reduced compared with as-deposited HfSiON in HF-based solutions. After the HfSiON film has been completely removed by HF-based solutions, it is not possible to etch the interracial layer and the etched surface does not have a hydrophobic nature, since N diffuses to the interface layer or Si substrate formation of Si-N bonds that dissolves very slowly in HF-based solutions. Existing Si-N bonds at the interface between the new high-k dielectric deposit and the Si substrate may degrade the carrier mobility due to Coulomb scattering. In addition, we show that N2 plasma treatment before wet etching is not very effective in increasing the wet etch rate for a thin HfSiON film in our case.     

HfSiON高K介质在HF基溶液中的湿法腐蚀特性研究

本文研究了HfSiON高K介质在HF基溶液中的湿法腐蚀特性。HF基溶液是最有希望实现HfSiON材料去除的湿法腐蚀溶液,而且通过在HF溶液中加入酸和/或无水乙醇可以提高HF基溶液的选择比。由于退火过程中引起的增密作用,与淀积后的HfSiON相比,经过900°C,30秒退火的HfSiON薄膜在HF基腐蚀溶液中的腐蚀速率显著降低。由于N扩散进入界面层或Si衬底形成在HF基溶液中很难溶解的Si-N键,采用HF基溶液完全去除HfSiON薄膜以后,存在一个不能被腐蚀干净的界面层且被腐蚀的表面未显示疏水特性。在新淀积的高K材料和Si衬底之间存在含有Si-N键的界面层可能因库伦散射而降低载流子迁移率。另外,对于很薄的HfSiON薄膜,在湿法腐蚀前采用N2等离子体处理对提高其湿法腐蚀速率并不是十分有效。     

Selective wet etch of a TaN metal gate with an amorphous-silicon hard mask

The appropriate wet etch process for the selective removal of TaN on the HfSiON dielectric with an amorphous-silicon(a-Si) hardmask is presented.SCI(NH_4OH:H_2O_2:H_2O),which can achieve reasonable etch rates for metal gates and very high selectivity to high-k dielectrics and hardmask materials,is chosen as the TaN etchant. Compared with the photoresist mask and the tetraethyl orthosilicate(TEOS) hardmask,the a-Si hardmask is a better choice to achieve selective removal of TaN on the HfSiON dielectric be...     

适用于双金属栅集成的TaN湿法腐蚀

Wet-etch etchants and the TaN film method for dual-metal-gate integration are investigated. Both HF/HN O3/H2O and NH4OH/H2O2 solutions can etch TaN effectively, but poor selectivity to the gate dielectric for the HF/HNO3/H2O solution due to HF being included in HF/HNO3/H2O, and the fact that TaN is difficult to etch in the NH4OH/H2O2 solution at the first stage due to the thin TaOxNy layer on the TaN surface, mean that they are difficult to individually apply to dual-metal-gate integration. A two-step wet etching strategy using the HF/HNO3/H2O solution first and the NH4OH/H2O2 solution later can fully remove thin TaN film with a photo-resist mask and has high selectivity to the HfSiON dielectric film underneath. High-k dielectric film surfaces are smooth after wet etching of the TaN metal gate and MOSCAPs show well-behaved C-V and Jg-Vg characteristics, which all prove that the wet etching of TaN has little impact on electrical performance and can be applied to dual-metal-gate integration technology for removing the first TaN metal gate in the PMOS region.     

TaN wet etch for application in dual-metal-gate integration technology

Wet-etch etchants and the TaN film method for dual-metal-gate integration are investigated. Both HF/HN O_3/H_2O and NH_4OH/H_2O_2 solutions can etch TaN effectively, but poor selectivity to the gate dielectric for the HF/HNO_3/H_2O solution due to HF being included in HF/HNO_3/H_2O, and the fact that TaN is difficult to etch in the NH_4OH/H_2O_2 solution at the first stage due to the thin TaO_xN_y layer on the TaN surface, mean that they are difficult to individually apply to dual-metal-gate integration. A two-step wet etching strategy using the HF/HNO_3/H_2O solution first and the NH_4OH/H_2O_2 solution later can fully remove thin TaN film with a photo-resist mask and has high selectivity to the HfSiON dielectric film underneath. High-k dielectric film surfaces are smooth after wet etching of the TaN metal gate and MOSCAPs show well-behaved C-V and J_g-V_g characteristics, which all prove that the wet etching of TaN has little impact on electrical performance and can be applied to dual-metal-gate integration technology for removing the first TaN metal gate in the PMOS region.     

通过多次淀积多次退火与Ti吸氧技术相结合来改善后栅工艺中高k金属栅的性能

本文的原子层淀积（ALD） HfO2薄膜采用新颖的多次淀积多次退火（MDMA）技术进行制备,并在有Ti吸氧层和没有Ti吸氧层两种情况下分别进行性能研究。 与传统的一次淀积一次退火相比,采用多次淀积多次退火后的器件漏电明显减小,同时,等效氧化层厚度（EOT）也被Ti吸氧层有效控制。器件性能的提升与淀积和退火次数密切相关（在保持总介质层厚度相同的情况下）。透射电子显微镜（TEM）和能量色散X射线光谱（EDX）分析表明,氧同时注入高k（HK）薄膜和中间层（IL）很可能是导致器件性能提升的主要原因。因此在后栅工艺中MDMA技术是一种改善栅极特性的有效方法。