Dry etching of poly-Si/TaN/HfSiON gate stack for advanced complementary metal-oxide-semiconductor devices

A novel dry etching process of a poly-Si/TaN/HfSiON gate stack for advanced complementary metal-oxide-semiconductor（CMOS） devices is investigated.Our strategy to process a poly-Si/TaN/HfSiON gate stack is that each layer of gate stack is selectively etched with a vertical profile.First,a three-step plasma etching process is developed to get a vertical poly-Si profile and a reliable etch-stop on a TaN metal gate.Then different BCl₃-based plasmas are applied to etch the TaN metal gate and find that BCl₃/Cl₂/O₂/Ar plasma is a suitable choice to get a vertical TaN profile.Moreover,considering that Cl₂ almost has no selectivity to Si substrate, BCl₃/Ar plasma is applied to etch HfSiON dielectric to improve the selectivity to Si substrate after the TaN metal gate is vertically etched off by the optimized BCl₃/Cl₂/O₂/Ar plasma.Finally,we have succeeded in etching a poly-Si/TaN/HfSiON stack with a vertical profile and almost no Si loss utilizing these new etching technologies.     

基于BCl3感应耦合等离子体的蓝宝石光滑表面刻蚀

利用Ar/BCl3、Cl2/BCl3和SF6/BCl3感应耦合等离子体(ICP),研究了蓝宝石(Al2O3)材料的干法刻蚀特性.实验表明,优化BCl3含量(80%),可以提高对Al2O3衬底的刻蚀速率;在BCl3刻蚀气体中加入20%的Ar气可以在高刻蚀速率下同时获得优于未刻蚀Al2O3衬底表面的光滑刻蚀表面和较好的刻蚀侧壁,原子力显微镜(AFM)分析得到最优刻蚀平整度为0.039 nm,俄歇电子能谱(AES)分析其归一化Al/O原子比为0.94.     

ICP刻蚀对光刻胶掩模及刻蚀图形侧壁的影响

采用AZ1500光刻胶作为掩模对GaAs和InP进行ICP刻蚀,研究了刻蚀参数对光刻胶掩模及刻蚀图形侧壁的影响。结果表明,光刻胶的碳化变性与等离子体的轰击相关,压强、ICP功率和RF功率的增加以及Cl2比例的减小都会加速光刻胶的碳化变性,Cl2/Ar比Cl2/BCl3更易使光刻胶发生变性。对于GaAs样品刻蚀,刻蚀气体中Cl2含量越高,刻蚀图形侧壁的横向刻蚀越严重。Cl2/BCl3对GaAs的刻蚀速率比Cl2/Ar慢,但刻蚀后样品的表面粗糙度比Cl2/Ar小。刻蚀InP时的刻蚀速率比GaAs样品慢,且存在图形侧壁倾斜现象。该工作有助于推动在器件制备工艺中以光刻胶作为掩模进行ICP刻蚀,从而提高器件制备效率。     

GaAs/AlGaAs多层膜刻蚀的陡直度

GaAs/AlGaAs多层膜的陡直度较大程度地关系到其实际应用效果,但在实际加工中较难控制,因此有必要研究刻蚀过程中一些主要因素对其陡直度的影响。结合具体工作情况,用AZ1500光刻胶作为掩模,GaAs/Al0.15Ga0.85As多层膜为刻蚀材料,分别使用湿法和干法对其进行刻蚀。湿法刻蚀的刻蚀剂为H3PO4+H2O2溶液,干法刻蚀采用感应耦合等离子体(ICP)刻蚀法,等离子体由Cl2+BCl3(蒸汽)混合气体电离形成。通过控制变量方法,发现湿法刻蚀中刻蚀剂配比和温度以及干法刻蚀中BCl3(蒸汽)流量对刻蚀陡直度的影响规律。由此得出,提高H3PO4所占比例和降低刻蚀温度虽然会降低刻蚀速率,但可以提高多层膜的陡直度;ICP刻蚀的陡直度优于湿法刻蚀,BCl3(蒸汽)的流量在一定范围内对刻蚀陡直度的影响较小。     

以非晶硅为硬掩膜的TaN金属栅的选择性湿法腐蚀

提出了一种在HfSiON介质上,采用非晶硅为硬掩膜的选择性去除TaN的湿法腐蚀工艺。由于SC1(NH4OH:H2O2:H2O)对金属栅具有合适的腐蚀速率且对硬掩膜和高K材料的选择比很高,所以选择它作为TaN的腐蚀溶液。与光刻胶掩膜和TEOS硬掩膜相比,因非晶硅硬掩膜不受SC1溶液的影响且很容易用NH4OH溶液去除（NH4OH溶液对TaN和HfSiON薄膜无损伤）,所以对于在HfSiON介质上实现TaN的选择性去除来说非晶硅硬掩膜是更好的选择。另外,在TaN金属栅湿法腐蚀和硬掩膜去除后, 高K介质的表面是光滑的,这可防止器件性能退化。因此,采用非晶硅为硬掩膜的TaN湿法腐蚀工艺可以应用于双金属栅集成,实现先淀积的TaN金属栅的选择性去除。     

Cl2/Ar感应耦合等离子体刻蚀Si工艺研究

采用Cl2/Ar感应耦合等离子体（ICP）对单晶硅进行了刻蚀,工艺中用光刻胶作掩膜。研究了气体组分、ICP功率和RF功率等工艺参数对硅刻蚀速率和硅与光刻胶刻蚀选择比的影响,同时还研究了不同工艺条件对侧壁形貌的影响。结果表明,由于物理刻蚀机制和化学刻蚀机制的相对强度受到混合气体中Cl2和Ar比例的影响,硅刻蚀速率随着Ar组分的增加而降低,同时选择比也随之降低。硅刻蚀速率随着ICP功率的增大先增大继而减小,选择比则成上升趋势。硅刻蚀速率和选择比均随RF功率的增大单调增大。在Cl2/Ar混合气体的刻蚀过程中,离子辅助溅射是决定硅刻蚀效果的重要因素。同时,文中还研究分析了刻蚀工艺对于微槽效应和刻蚀侧壁形貌的影响,结果表明,通过提高ICP功率可以有效减小微槽和平滑侧壁。进一步研究了SiO2掩膜下,压强改变对于硅刻蚀形貌的影响,发现通过降低压强,可以明显地抑制杂草的产生。     

p-GaN在不同掩膜和刻蚀气体中的ICP刻蚀

p-GaN栅沟槽侧壁与AlGaN表面特性直接影响栅注入(GIT)型AlGaN/GaN HEMT器件的输出特性及击穿特性.对比研究了两种刻蚀气体(SF6/BCl3和Cl2/N2/O2)及不同的刻蚀掩膜层(SiO2,Si3N4和光刻胶)对AlGaN上p-GaN的选择性刻蚀结果,利用原子力显微镜(AFM)对刻蚀沟槽的表面形貌进行表征,并通过I-V测试其电学性能.结果显示,以Cl2/N2/O2为刻蚀气体,且体积流量为18,10和2 cm3/min时,p-GaN刻蚀速率稳定且与AlGaN的刻蚀选择比较高(约30),并且可使p-GaN刻蚀自动停止在AlGaN界面处.此外,以Si3N4作为刻蚀掩膜,可以获得表面光滑、无微沟槽且侧壁垂直度较好的沟槽结构.采用上述刻蚀工艺制备的GIT结构器件的漏端关态电流相比肖特基栅降低约2个量级,阈值电压约为0.61 V,峰值跨导为36 mS/mm.     

Ar/CHF_3反应离子束刻蚀SiO_2的研究

介绍了Ar/CHF3反应离子束刻蚀和离子束入射角对图形侧壁陡直度及刻蚀选择比的影响。使用紫外曝光技术在SiO2基片上获得光刻胶掩模图形,采用Ar CHF3来刻蚀石英基片,调节二者的流量配比,混合后通入离子源。在Ar和CHF3的流量比为1∶2,总压强为2×10-2Pa,离子束流能量为450 eV,束流为80 mA,加速电压220 V~240 V,离子束入射角15°并旋转样品台的情况下,刻蚀20 min后,得到光栅剖面倾角陡直度为80°~90°。同时发现,添加CHF3后,提高了SiO2的刻蚀速率和刻蚀SiO2与光刻胶的选择比,最高可达7∶1。     

Ar/CHF3反应离子束刻蚀SiO2的研究

介绍了Ar/CHF3反应离子束刻蚀和离子束入射角对图形侧壁陡直度及刻蚀选择比的影响.使用紫外曝光技术在SiO2基片上获得光刻胶掩模图形,采用Ar+CHF3来刻蚀石英基片,调节二者的流量配比,混合后通入离子源.在Ar和CHF3的流量比为12,总压强为2×10-2 Pa,离子束流能量为450 eV,束流为80 mA,加速电压220 V～240 V,离子束入射角15°并旋转样品台的情况下,刻蚀20 min后,得到光栅剖面倾角陡直度为80°～90°.同时发现,添加CHF3后,提高了SiO2的刻蚀速率和刻蚀SiO2与光刻胶的选择比,最高可达71.     

Cl2基气体感应耦合等离子体刻蚀GaN的工艺

采用Cl2/He对GaN基片进行感应耦合等离子体刻蚀,并比较了相同条件下使用Cl2/He,Cl2/Ar对GaN基片进行刻蚀的优劣.实验中通过改变ICP功率、直流自偏压、气体总流量和气体组分等方式,讨论了这些因素对刻蚀速率和刻蚀后表面粗糙度的影响.实验结果表明,用Cl2/He气体刻蚀GaN材料可以获得较高的刻蚀速率,最高可达420nm/min.同时刻蚀后GaN材料的表面形貌也较为平整,均方根粗糙度(RMS)可达1nm以下.SEM图像显示刻蚀后表面光洁,刻蚀端面陡直.最后比较了相同条件下使用Cl2/He,Cl2/Ar刻蚀GaN基片的刻蚀速率、表面形貌,以及制作n型电极后的比接触电阻.     

The fabrication and dry etching of poly-Si/TaN/Mo gate stack in the metal inserted poly-Si stack structure

The Mo-based metal inserted poly-Si stack (MIPS) structure is an appropriate choice for metal gate and high-k integration in sub-45 nm gate-first CMOS device. A novel metal nitride layer of TaN or AlN with high thermal stability has been introduced between Mo and poly-Si as a barrier material to avoid any reaction of Mo during poly-Si deposition. After Mo-based MIPS structure is successfully prepared, dry etching of poly-Si/TaN/Mo gate stack is studied in detail. The three-step plasma etching using the Cl₂/HBr chemistry without soft landing step has been developed to attain a vertical poly-Si profile and a reliable etch-stop on the TaN/Mo metal gate. For the etching of TaN/Mo gate stack, two methods using BCl₃/Cl₂/O₂/Ar plasma are presented to get both vertical profile and smooth etched surface, and they are critical to get high selectivity to high-k dielectric and Si substrate. In addition, adding a little SF₆ to the BCl₃/O₂/Ar plasma under the optimized conditions is also found to be effective to smoothly etch the TaN/Mo gate stack with vertical profile.     

Selective wet etch of a TaN metal gate with an amorphous-silicon hard mask

The appropriate wet etch process for the selective removal of TaN on the HfSiON dielectric with an amorphous-silicon(a-Si) hardmask is presented.SCI(NH_4OH:H_2O_2:H_2O),which can achieve reasonable etch rates for metal gates and very high selectivity to high-k dielectrics and hardmask materials,is chosen as the TaN etchant. Compared with the photoresist mask and the tetraethyl orthosilicate(TEOS) hardmask,the a-Si hardmask is a better choice to achieve selective removal of TaN on the HfSiON dielectric be...     

Model‐Based Analysis of the ZrO2 Etching Mechanism in Inductively Coupled BCl3/Ar and BCl3/CHF3/Ar Plasmas

The etching mechanism of ZrO₂ thin films and etch selectivity over some materials in both BCl₃/Ar and BCl3/CHF3/Ar plasmas are investigated using a combination of experimental and modeling methods. To obtain the data on plasma composition and fluxes of active species, global (0‐dimensional) plasma models are developed with Langmuir probe diagnostics data. In BCl3/Ar plasma, changes in gas mixing ratio result in nonlinear changes of both densities and fluxes for Cl, BCl2, and BCl2⁺. In this work, it is shown that the nonmonotonic behavior of the ZrO2 etch rate as a function of the BCl3/Ar mixing ratio could be related to the ion‐assisted etch mechanism and the ion‐flux‐limited etch regime. The addition of up to 33% CHF₃ to the BCl₃‐rich BCl3/Ar plasma does not influence the ZrO2 etch rate, but it non‐monotonically changes the etch rates of both Si and SiO2. The last effect can probably be associated with the corresponding behavior of the F atom density.     

TaN wet etch for application in dual-metal-gate integration technology

Wet-etch etchants and the TaN film method for dual-metal-gate integration are investigated. Both HF/HN O_3/H_2O and NH_4OH/H_2O_2 solutions can etch TaN effectively, but poor selectivity to the gate dielectric for the HF/HNO_3/H_2O solution due to HF being included in HF/HNO_3/H_2O, and the fact that TaN is difficult to etch in the NH_4OH/H_2O_2 solution at the first stage due to the thin TaO_xN_y layer on the TaN surface, mean that they are difficult to individually apply to dual-metal-gate integration. A two-step wet etching strategy using the HF/HNO_3/H_2O solution first and the NH_4OH/H_2O_2 solution later can fully remove thin TaN film with a photo-resist mask and has high selectivity to the HfSiON dielectric film underneath. High-k dielectric film surfaces are smooth after wet etching of the TaN metal gate and MOSCAPs show well-behaved C-V and J_g-V_g characteristics, which all prove that the wet etching of TaN has little impact on electrical performance and can be applied to dual-metal-gate integration technology for removing the first TaN metal gate in the PMOS region.     

Plasma Etching for Sub-45-nm TaN Metal Gates on High-k Dielectrics

Etching of TaN gates on high-k dielectrics (HfO₂ or HfAlO) is investigated using HBr/Cl₂ chemistry in a decoupled plasma source (DPS). The patterning sequence includes 248-nm lithography, plasma photoresist trimming, etching of a SiN-SiO₂ hard mask, and photoresist stripping, followed by TaN etching. TaN etching is studied by design of experiment (DOE) with four variables using a linear model with interactions. It is found that at a fixed substrate temperature and wafer chuck power, etch critical dimensions (CD) gain decreases with decreasing HBr/Cl₂ flow rate ratio and pressure and with increasing source power and total gas flow rate. Based on these DOE findings, subsequent optimization is performed and a three-step etching process is developed; a main feature of the process is progressively increasing HBr/Cl₂ flow rate ratio. The optimized process provides etch CD gain within 2 nm and gate profile close to vertical and reliable etch-stop on high-k dielectric. This process is successfully applied to the fabrication of the 40-nm HfAlO/TaN gate stack p-MOSFETs with good electrical parameters     

Fluorine Passivation in Gate Stacks of Poly-Si/TaN/HfO2 (and HfSiON/HfO2)/Si Through Gate Ion Implantation

Fluorine passivation in poly-Si/TaN/HfO₂/p-Si and poly-Si/TaN/HfSiON/HfO₂/p-Si gate stacks with varying TaN thickness through gate ion implantation has been studied. It has been found that when TaN thickness was less than 15 nm, mobility and subthreshold swing improved significantly in HfO₂ nMOSFETs; while there was little performance improvement in HfSiON/HfO₂ nMOSFETs due to the blocking of F atoms by the HfSiON layer in gate dielectrics, as has been proved by the electron energy loss spectroscopy mapping     

Process design for plasma etching of polysilicon/silicon nitride/polysilicon sandwich structures for sensor applications

An in situ two-step process has been developed for plasma etching of poly-Si/silicon nitride/poly-Si sandwich structures for a surface micromachined tactile sensor. The first step of the process uses a CF₄-based gas mixture to etch the upper poly-Si layer and the second uses a CHF₃-based gas mixture to etch the silicon nitride with an etching selectivity of three over the lower poly-Si layer. Both the upper poly-Si and the silicon nitride of the sandwich structure can be etched with the same photoresist mask, while the lower poly-Si layer remains relatively un-etched. Compared with a one-step process which uses the same chemistry as in step one of the two-step process, the two-step process provides the desired etch selectivity, better uniformity and process tolerance.