共查询到20条相似文献,搜索用时 15 毫秒
1.
《Electron Device Letters, IEEE》2008,29(6):557-560
In this letter, we report the fabrication and characterization of self-aligned inversion-type enhancement-mode In0.53Ga0.47As metal-oxide-semiconductor field-effect transistors (MOSFETs). The In0.53Ga0.47As surface was passivated by atomic layer deposition of a 2.5-nm-thick AIN interfacial layer. In0.53Ga0.47As MOS capacitors showed an excellent frequency dispersion behavior. A maximum drive current of 18.5 muA/mum was obtained at a gate overdrive of 2 V for a MOSFET device with a gate length of 20 mum. An Ion/off ratio of 104, a positive threshold voltage of 0.15 V, and a subthreshold slope of ~165 mV/dec were extracted from the transfer characteristics. The interface-trap density is estimated to be ~7-8 times 1012 cm-2 ldr eV-1 from the subthreshold characteristics of the MOSFET. 相似文献
2.
Chia-Yu Chen Yang Liu Dutton R.W. Sato-Iwanaga J. Inoue A. Sorada H. 《Electron Devices, IEEE Transactions on》2008,55(7):1741-1748
Device-level simulation capabilities have been developed to investigate low-frequency noise behavior in p-type Si0.7Ge0.3/Si heterostructure MOS (SiGe p-HMOS) transistors. The numerical model is based on the impedance field method; it accounts for a trap-induced carrier number fluctuation, a layer-dependent correlated mobility fluctuation, and a Hooge mobility fluctuation in the buried and parasitic surface channels, respectively. Simulations based on such models have been conducted for SiGe p-HMOS transistors, and the results have been carefully correlated with experimental data. Quantitative agreement has been obtained in terms of the noise level dependence on gate biases, drain currents, and body biases, revealing the important role of the dual channels in the low-frequency noise behavior of SiGe p-HMOS devices. 相似文献
3.
Chang S.Z. Yu H.Y. Adelmann C. Delabie A. Wang X.P. Van Elshocht S. Akheyar A. Nyns L. Swerts J. Aoulaiche M. Kerner C. Absil P. Hoffmann T.Y. Biesemans S. 《Electron Device Letters, IEEE》2008,29(5):430-433
In this letter, we report that by employing the La2O3/SiOx interfacial layer between HfLaO (La = 10%) high- and Si channel, the Ta2C metal-gated n-MOSFETs VT can be significantly reduced by ~350 mV to 0.2 V, satisfying the low-Vy device requirement. The resultant n-MOSFETs also exhibit an ultrathin equivalent oxide thickness (~1.18 nm) with a low gate leakage (JG = 10 mA/cm2 at 1.1 V), good drive performance (Ion = 900 muA/mum at Isoff = 70 nA/mum), and acceptable positive-bias-temperature-instability reliability. 相似文献
4.
Veloso A. Yu H.Y. Chang S.Z. Adelmann C. Onsia B. Brus S. Demand M. Lauwers A. O'Sullivan B.J. Singanamalla R. Pourtois G. Lehnen P. Van Elshocht S. De Meyer K. Jurczak M. Absil P.P. Biesemans S. 《Electron Device Letters, IEEE》2007,28(11):980-983
This letter reports that the effective work function (eWF) of Ni-Fully Silicided (Ni-FUSI) devices with HfSiON gate dielectrics can be modulated toward the silicon conduction band-edge by deposition of an ultra-thin Dy2O3 cap layer on the host dielectric. The obtained eWF depends on the deposited cap layer thickness and the Ni-FUSI phase, with 10 Aring Dy2O3 cap resulting in DeltaeWF ap 400 meV and final eWF ap 4.08 eV for NiSi-FUSI. Dielectric intermixing occurs without impacting the VT uniformity, gate leakage, mobility, and reliability. Well-behaved short-channel devices ( Lg ~ 100 nm, SS ~ 70 mV/dec, and DIBL ~ 65 mV/V) are demonstrated for both HfSiON and [HfSiON/Dy2O3 cap (5 Aring)] devices with NiSi-FUSI gates, corresponding to a similar . This capping approach, when combined with Ni-silicide FUSI phase engineering, allows (n-p) values up to 800 meV, making it promising for low- CMOS. 相似文献
5.
Sun Y. Kiewra E.W. Koester S.J. Ruiz N. Callegari A. Fogel K.E. Sadana D.K. Fompeyrine J. Webb D.J. Locquet J.-P. Sousa M. Germann R. Shiu K.T. Forrest S.R. 《Electron Device Letters, IEEE》2007,28(6):473-475
The operation of long- and short-channel enhancement-mode In0.7Ga0.3As-channel MOSFETs with high-k gate dielectrics are demonstrated for the first time. The devices utilize an undoped buried-channel design. For a gate length of 5 mum, the long-channel devices have Vt= +0.25 V, a subthreshold slope of 150 mV/dec, an equivalent oxide thickness of 4.4 +/ - 0.3 nm, and a peak effective mobility of 1100 cm2/Vldrs. For a gate length of 260 nm, the short-channel devices have Vt=+0.5 V and a subthreshold slope of 200 mV/dec. Compared with Schottky-gated high-electron-mobility transistor devices, both long- and short-channel MOSFETs have two to four orders of magnitude lower gate leakage. 相似文献
6.
Niu Jin Ronghua Yu Sung-Yong Chung Berger P.R. Thompson P.E. 《Electron Device Letters, IEEE》2008,29(6):599-602
Strain-engineered Si-based resonant interband tunneling diodes grown on commercially available Si0.8Ge0.2 virtual substrates were developed that address issues of P dopant diffusion and electron confinement. Strain-induced band offsets were effectively utilized to improve tunnel diode performance versus the control device, particularly the peak-to-valley current ratio (PVCR). By growing tensilely strained Si layers cladding the P delta-doping plane, the quantum well formed by the P delta-doping plane is deepened, which concurrently increases the optimal annealing temperature from 800 to 835 and facilitates an increase in the PVCR up to 1.8times from 1.6 to 2.8 at room temperature, which is significantly better than previous results on strained substrates. 相似文献
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8.
《Electron Device Letters, IEEE》2009,30(5):463-465
9.
The electrical characteristics of germanium p-metal-oxide-semiconductor (p-MOS) capacitor and p-MOS field-effect transistor (FET) with a stack gate dielectric of HfO2/TaOxNy are investigated. Experimental results show that MOS devices exhibit much lower gate leakage current than MOS devices with only HfO2 as gate dielectric, good interface properties, good transistor characteristics, and about 1.7-fold hole-mobility enhancement as compared with conventional Si p-MOSFETs. These demonstrate that forming an ultrathin passivation layer of TaOxNy on germanium surface prior to deposition of high-k dielectrics can effectively suppress the growth of unstable GeOx, thus reducing interface states and increasing carrier mobility in the inversion channel of Ge-based transistors. 相似文献
10.
《Electron Devices, IEEE Transactions on》2008,55(9):2361-2369
11.
Ming-Wen Ma Tien-Sheng Chao Chun-Jung Su Woei-Cherng Wu Kuo-Hsing Kao Tan-Fu Lei 《Electron Device Letters, IEEE》2008,29(6):592-594
In this letter, high-performance low-temperature poly-Si p-channel thin-film transistor with metal-induced lateral- crystallization (MILC) channel layer and TaN/HfO2 gate stack is demonstrated for the first time. The devices of low threshold voltage VTH ~ 0.095 V, excellent subthreshold swing S.S. ~83 mV/dec, and high field-effect mobility muFE ~ 240 cm2/V ldr s are achieved without any defect passivation methods. These significant improvements are due to the MILC channel film and the very high gate-capacitance density provided by HfO2 gate dielectric with the effective oxide thickness of 5.12 nm. 相似文献
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13.
《Electron Device Letters, IEEE》2009,30(6):614-616
14.
《Electron Device Letters, IEEE》2009,30(4):340-342
15.
Tunneling Effective Mass of Electrons in Lightly N-Doped $hbox{SiO}_{x} hbox{N}_{y}$ Gate Insulators
《Electron Devices, IEEE Transactions on》2008,55(9):2462-2468
16.
Kang-Sung Lee Young-Su Kim Yun-Ki Hong Yoon-Ha Jeong 《Electron Device Letters, IEEE》2007,28(8):672-675
Metamorphic GaAs high electron mobility transistors (mHEMTs) with the highest-f max reported to date are presented here. The 35-nm zigzag T-gate In0.52Al0.48As/In0.53Ga0.47As metamorphic GaAs HEMTs show f maxof 520 GHz, f T of 440 GHz, and maximum transconductance (g m) of 1100 mS/mm at a drain current of 333 mA/mm. The combinations of f max and f T are the highest data yet reported for mHEMTs. These devices are promising candidates for aggressively scaled sub-35-nm T-gate mHEMTs. 相似文献
17.
《Electron Devices, IEEE Transactions on》2009,56(9):1966-1973
18.
《Electron Device Letters, IEEE》2008,29(7):655-657
19.
《Electron Device Letters, IEEE》2008,29(12):1353-1355
20.
Alatise O.M. Olsen S.H. Cowern N. O'Neill A.G. Majhi P. 《Electron Devices, IEEE Transactions on》2009,56(10):2277-2284
The short-channel performance of compressively strained Si0.77Ge0.23 pMOSFETs with HfSiOx/TiSiN gate stacks has been characterized alongside that of unstrained-Si pMOSFETs. Strained-SiGe devices exhibit 80% mobility enhancement compared with Si control devices at an effective vertical field of 1 MV middotcm-1. For the first time, the on-state drain-current enhancement of intrinsic strained-SiGe devices is shown to be approximately constant with scaling. Intrinsic strained-SiGe devices with 100-nm gate lengths exhibit 75% enhancement in maximum transconductance compared with Si control devices, using only ~20% Ge (~0.8% strain). The origin of the loss in performance enhancement commonly observed in strained-SiGe devices at short gate lengths is examined and found to be dominated by reduced boron diffusivity and increased parasitic series resistance in compressively strained SiGe devices compared with silicon control devices. The effective channel length was extracted from I- V measurements and was found to be 40% smaller in 100-nm silicon control devices than in SiGe devices having the same lithographic gate lengths, which is in good agreement with the metallurgical channel length predicted by TCAD process simulations. Self-heating due to the low thermal conductivity of SiGe is shown to have a negligible effect on the scaled-device performance. These findings demonstrate that the significant on-state performance gains of strained-SiGe pMOSFETs compared with bulk Si devices observed at long channel lengths are also obtainable in scaled devices if dopant diffusion, silicidation, and contact modules can be optimized for SiGe. 相似文献