Fabrication of Self-Aligned Enhancement-Mode $ hbox{In}_{0.53}hbox{Ga}_{0.47}hbox{As}$ MOSFETs With $ hbox{TaN/HfO}_{2}hbox{/AlN}$ Gate Stack

In this letter, we report the fabrication and characterization of self-aligned inversion-type enhancement-mode In_0.53Ga_0.47As metal-oxide-semiconductor field-effect transistors (MOSFETs). The In_0.53Ga_0.47As surface was passivated by atomic layer deposition of a 2.5-nm-thick AIN interfacial layer. In_0.53Ga_0.47As MOS capacitors showed an excellent frequency dispersion behavior. A maximum drive current of 18.5 muA/mum was obtained at a gate overdrive of 2 V for a MOSFET device with a gate length of 20 mum. An I_on/_off ratio of 104, a positive threshold voltage of 0.15 V, and a subthreshold slope of ~165 mV/dec were extracted from the transfer characteristics. The interface-trap density is estimated to be ~7-8 times 10¹² cm^-2 ldr eV^-1 from the subthreshold characteristics of the MOSFET.     

Numerical Study of Flicker Noise in p-Type $ hbox{Si}_{0.7}hbox{Ge}_{0.3}/hbox{Si}$ Heterostructure MOSFETs

Device-level simulation capabilities have been developed to investigate low-frequency noise behavior in p-type Si_0.7Ge_0.3/Si heterostructure MOS (SiGe p-HMOS) transistors. The numerical model is based on the impedance field method; it accounts for a trap-induced carrier number fluctuation, a layer-dependent correlated mobility fluctuation, and a Hooge mobility fluctuation in the buried and parasitic surface channels, respectively. Simulations based on such models have been conducted for SiGe p-HMOS transistors, and the results have been carefully correlated with experimental data. Quantitative agreement has been obtained in terms of the noise level dependence on gate biases, drain currents, and body biases, revealing the important role of the dual channels in the low-frequency noise behavior of SiGe p-HMOS devices.     

Electrical Properties of Low-$V_{T}$ Metal-Gated n-MOSFETs Using $hbox{La}_{2}hbox{O}_{3}/hbox{SiO}_{x}$ as Interfacial Layer Between HfLaO High- $kappa$ Dielectrics and Si Channel

In this letter, we report that by employing the La₂O₃/SiO_x interfacial layer between HfLaO (La = 10%) high- and Si channel, the Ta₂C metal-gated n-MOSFETs V_T can be significantly reduced by ~350 mV to 0.2 V, satisfying the low-Vy device requirement. The resultant n-MOSFETs also exhibit an ultrathin equivalent oxide thickness (~1.18 nm) with a low gate leakage (J_G = 10 mA/cm² at 1.1 V), good drive performance (I_on = 900 muA/mum at I_soff = 70 nA/mum), and acceptable positive-bias-temperature-instability reliability.     

Achieving Low-$V_{T}$ Ni-FUSI CMOS by Ultra-Thin $hbox{Dy}_{2}hbox{O}_{3}$ Capping of Hafnium Silicate Dielectrics

This letter reports that the effective work function (eWF) of Ni-Fully Silicided (Ni-FUSI) devices with HfSiON gate dielectrics can be modulated toward the silicon conduction band-edge by deposition of an ultra-thin Dy₂O₃ cap layer on the host dielectric. The obtained eWF depends on the deposited cap layer thickness and the Ni-FUSI phase, with 10 Aring Dy₂O₃ cap resulting in DeltaeWF ap 400 meV and final eWF ap 4.08 eV for NiSi-FUSI. Dielectric intermixing occurs without impacting the VT uniformity, gate leakage, mobility, and reliability. Well-behaved short-channel devices ( Lg ~ 100 nm, SS ~ 70 mV/dec, and DIBL ~ 65 mV/V) are demonstrated for both HfSiON and [HfSiON/Dy₂O₃ cap (5 Aring)] devices with NiSi-FUSI gates, corresponding to a similar . This capping approach, when combined with Ni-silicide FUSI phase engineering, allows (n-p) values up to 800 meV, making it promising for low- CMOS.     

Strain-Engineered Si/SiGe Resonant Interband Tunneling Diodes Grown on $hbox{Si}_{0.8}hbox{Ge}_{0.2}$ Virtual Substrates With Strained Si Cladding Layers

Strain-engineered Si-based resonant interband tunneling diodes grown on commercially available Si_0.8Ge_0.2 virtual substrates were developed that address issues of P dopant diffusion and electron confinement. Strain-induced band offsets were effectively utilized to improve tunnel diode performance versus the control device, particularly the peak-to-valley current ratio (PVCR). By growing tensilely strained Si layers cladding the P delta-doping plane, the quantum well formed by the P delta-doping plane is deepened, which concurrently increases the optimal annealing temperature from 800 to 835 and facilitates an increase in the PVCR up to 1.8times from 1.6 to 2.8 at room temperature, which is significantly better than previous results on strained substrates.     

Enhancement-Mode Buried-Channel $hbox{In}_{0.7} hbox{Ga}_{0.3}hbox{As/In}_{0.52}hbox{Al}_{0.48}hbox{As}$ MOSFETs With High- $kappa$ Gate Dielectrics

The operation of long- and short-channel enhancement-mode In_0.7Ga_0.3As-channel MOSFETs with high-k gate dielectrics are demonstrated for the first time. The devices utilize an undoped buried-channel design. For a gate length of 5 mum, the long-channel devices have V_t= +0.25 V, a subthreshold slope of 150 mV/dec, an equivalent oxide thickness of 4.4 +/ - 0.3 nm, and a peak effective mobility of 1100 cm²/Vldrs. For a gate length of 260 nm, the short-channel devices have V_t=+0.5 V and a subthreshold slope of 200 mV/dec. Compared with Schottky-gated high-electron-mobility transistor devices, both long- and short-channel MOSFETs have two to four orders of magnitude lower gate leakage.     

Fabrication and Properties of $hbox{Pt}/hbox{Bi}_{3.15}hbox{Nd}_{0.85} hbox{Ti}_{3}hbox{O}_{12}/breakhbox{HfO}_{2}/hbox{Si}$ Structure for Ferroelectric DRAM (FEDRAM) FET

Metal–ferroelectric–insulator–semiconductor (MFIS) capacitors with 400-nm-thick $hbox{Bi}_{3.15}hbox{Nd}_{0.85}hbox{Ti}_{3}hbox{O}_{12}$ (BNdT) ferroelectric film and 4-nm-thick hafnium oxide $(hbox{HfO}_{2})$ layer on silicon substrate have been fabricated and characterized. It is demonstrated that the $hbox{Pt}/hbox{Bi}_{3.15}hbox{Nd}_{0.85}hbox{Ti}_{3}hbox{O}_{12}/ hbox{HfO}_{2}/hbox{Si}$ structure exhibits a large memory window of around 1.12 V at an operation voltage of 3.5 V. Moreover, the MFIS memory structure suffers only 10% degradation in the memory window after $hbox{10}^{10}$ switching cycles. The retention time is 100 s, which is enough for ferroelectric DRAM field-effect-transistor application. The excellent performance is attributed to the formation of well-crystallized BNdT perovskite thin film on top of the $ hbox{HfO}_{2}$ buffer layer, which serves as a good seed layer for BNdT crystallization, making the proposed $hbox{Pt}/hbox{Bi}_{3.15}hbox{Nd}_{0.85}hbox{Ti}_{3}hbox{O}_{12}/ hbox{HfO}_{2}/hbox{Si}$ suitable for high-performance ferroelectric memories.      

Improved Electrical Properties of Ge p-MOSFET With $ hbox{HfO}_{2}$ Gate Dielectric by Using $hbox{TaO}_{x} hbox{N}_{y}$ Interlayer

The electrical characteristics of germanium p-metal-oxide-semiconductor (p-MOS) capacitor and p-MOS field-effect transistor (FET) with a stack gate dielectric of HfO₂/TaOxNy are investigated. Experimental results show that MOS devices exhibit much lower gate leakage current than MOS devices with only HfO₂ as gate dielectric, good interface properties, good transistor characteristics, and about 1.7-fold hole-mobility enhancement as compared with conventional Si p-MOSFETs. These demonstrate that forming an ultrathin passivation layer of TaOxNy on germanium surface prior to deposition of high-k dielectrics can effectively suppress the growth of unstable GeOx, thus reducing interface states and increasing carrier mobility in the inversion channel of Ge-based transistors.     

High-Performance Metal-Induced Laterally Crystallized Polycrystalline Silicon P-Channel Thin-Film Transistor With $hbox{TaN/HfO}_{2}$ Gate Stack Structure

In this letter, high-performance low-temperature poly-Si p-channel thin-film transistor with metal-induced lateral- crystallization (MILC) channel layer and TaN/HfO₂ gate stack is demonstrated for the first time. The devices of low threshold voltage V_TH ~ 0.095 V, excellent subthreshold swing S.S. ~83 mV/dec, and high field-effect mobility mu_FE ~ 240 cm²/V ldr s are achieved without any defect passivation methods. These significant improvements are due to the MILC channel film and the very high gate-capacitance density provided by HfO₂ gate dielectric with the effective oxide thickness of 5.12 nm.     

Electrical Properties of $hbox{Bi}_{5}hbox{Nb}_{3} hbox{O}_{15}$ Thin Film Grown on $hbox{TiN}/hbox{SiO}_{2}/ hbox{Si}$ at Room Temperature for Metal–Insulator–Metal Capacitors

Buckling was observed in $hbox{Bi}_{5}hbox{Nb}_{3}hbox{O}_{15}$ (BiNbO) films grown on $hbox{TiN}/hbox{SiO}_{2}/hbox{Si}$ at 300 $^{circ}hbox{C}$ but not in films grown at room temperature and annealed at 350 $^{circ}hbox{C}$. The 45-nm-thick films showed a high capacitance density and a low dissipation factor of 8.81 $hbox{fF}/muhbox{m}^{2}$ and 0.97% at 100 kHz, respectively, with a low leakage current density of 3.46 $hbox{nA}/hbox{cm}^{2}$ at 2 V. The quadratic and linear voltage coefficients of capacitance of this film were 846 $hbox{ppm}/hbox{V}^{2}$ and 137 ppm/V, respectively, with a low temperature coefficient of capacitance of 226 $hbox{ppm}/^{circ}hbox{C}$ at 100 kHz. This suggests that a BiNbO film grown on a $hbox{TiN}/ hbox{SiO}_{2}/hbox{Si}$ substrate is a good candidate material for high-performance metal–insulator–metal capacitors.      

35-nm Zigzag T-Gate $hbox{In}_{0.52}hbox{Al}_{0.48} hbox{As/In}_{0.53}hbox{Ga}_{0.47}hbox{As}$ Metamorphic GaAs HEMTs With an Ultrahigh $f_{max}$ of 520 GHz

Metamorphic GaAs high electron mobility transistors (mHEMTs) with the highest-f _max reported to date are presented here. The 35-nm zigzag T-gate In_0.52Al_0.48As/In_0.53Ga_0.47As metamorphic GaAs HEMTs show f _maxof 520 GHz, f _T of 440 GHz, and maximum transconductance (g _m) of 1100 mS/mm at a drain current of 333 mA/mm. The combinations of f _max and f _T are the highest data yet reported for mHEMTs. These devices are promising candidates for aggressively scaled sub-35-nm T-gate mHEMTs.     

First Insight Into the Lifetime Acceleration Model of High-$k$ $hbox{ZrO}_{2}/hbox{SiO}_{2}/hbox{ZrO}_{2}$ Stacks for Advanced DRAM Technology Nodes

Long-term reliability results over six orders of magnitude in time are presented showing that the voltage acceleration model for $hbox{ZrO}_{2}/hbox{SiO}_{2}/hbox{ZrO}_{2}$ exhibits an exponential dependence with voltage, down to 2 V. The voltage acceleration parameter $gamma$ is between 10 and 15 $hbox{V}^{-1}$, depending on the biasing polarity. Soft-breakdown behavior (SILC) is evident prior to the onset of hard breakdown as a result of barrier lowering or charge accumulation in the high- $k$ film. Under ac stress conditions, this SILC branch is lowered in magnitude, translating to a gain in lifetime to breakdown.      

Comparative Study of the Low-Frequency-Noise Behaviors in a-IGZO Thin-Film Transistors With $hbox{Al}_{2}hbox{O}_{3}$ and $hbox{Al}_{2}hbox{O}_{3}/hbox{SiN}_{x}$ Gate Dielectrics

A comparative study is made of the low-frequency noise (LFN) in amorphous indium–gallium–zinc oxide (a-IGZO) thin-film transistors (TFTs) with $hbox{Al}_{2}hbox{O}_{3}$ and $hbox{Al}_{2}hbox{O}_{3}/hbox{SiN}_{x}$ gate dielectrics. The LFN is proportional to $hbox{1}/f^{gamma}$, with $gamma sim hbox{1}$ for both devices, but the normalized noise for the $hbox{Al}_{2}hbox{O}_{3}/hbox{SiN}_{x}$ device is two to three orders of magnitude lower than that for the $hbox{Al}_{2} hbox{O}_{3}$ device. The mobility fluctuation is the dominant LFN mechanism in both devices, but the noise from the source/drain contacts becomes comparable to the intrinsic channel noise as the gate overdrive voltage increases in $hbox{Al}_{2}hbox{O}_{3}/hbox{SiN}_{x}$ devices. The $hbox{SiN}_{x}$ interfacial layer is considered to be very effective in reducing LFN by suppressing the remote phonon scattering from the $hbox{Al}_{2}hbox{O}_{3}$ dielectric. Hooge's parameter is extracted to $sim !!hbox{6.0} times hbox{10}^{-3}$ in $hbox{Al}_{2}hbox{O}_{3}/hbox{SiN}_{x}$ devices.      

Low Turn-On Voltage and High-Current $hbox{InP}/ hbox{In}_{0.37}hbox{Ga}_{0.63}hbox{As}_{0.89}hbox{Sb}_{0.11}/hbox{In}_{0.53}hbox{Ga}_{0.47}hbox{As}$ Double Heterojunction Bipolar Transistors

We report on the dc and microwave characteristics of an $ hbox{InP/In}_{0.37}hbox{Ga}_{0.63}hbox{As}_{0.89}hbox{Sb}_{0.11}/hbox{In}_{0.53}hbox{Ga}_{0.47}hbox{As}$ double heterojunction bipolar transistor grown by solid-source molecular beam epitaxy. The pseudomorphic $hbox{In}_{0.37}hbox{Ga}_{0.63}hbox{As}_{0.89}hbox{Sb}_{0.11}$ base reduces the conduction band offset $Delta E_{C}$ at the emitter/base junction and the base band gap, which leads to a very low $V_{rm BE}$ turn-on voltage of 0.35 V at 1 $hbox{A/cm}^{2}$ . A current gain of 125 and a peak $f_{T}$ of 238 GHz have been obtained on the devices with an emitter size of $hbox{1}times hbox{10} muhbox{m}^{2}$, suggesting that a high collector average velocity and a high current capability are achieved due to the type-II lineup at the InGaAsSb/InGaAs base/collector junction.      

Second-Bit-Effect-Free Multibit-Cell Flash Memory Using $hbox{Si}_{3} hbox{N}_{4}/hbox{ZrO}_{2}$ Split Charge Trapping Layer

In this paper, a $hbox{Si}_{3}hbox{N}_{4}/hbox{ZrO}_{2}$ split charge trapping layer (SCTL) is proposed for multibit-cell Flash memory. The complementary potential wells of $hbox{Si}_{3}hbox{N}_{4}/hbox{ZrO}_{2}$ storage nodes enable independent node control when the Fowler–Nordheim (F–N) method is applied for programming/erasing (P/E). Experiment and simulation results suggest that the 2-bit (2-b) charge storage is accomplished by physical data node separation for the SCTL rather than charge injection control. The well-confined charge storages suppress the second-bit effect, enabling excellent 2-b data clearance for short-channel SCTL devices. It was found that the remaining memory windows after $hbox{10}^{5} hbox{s}$ decrease, dependent on the difference of the trap properties between $ hbox{Si}_{3}hbox{N}_{4}$ and $hbox{ZrO}_{2}$.      

RF and Logic Performance Improvement of $ hbox{In}_{0.7}hbox{Ga}_{0.3}hbox{As}/hbox{InAs}/hbox{In}_{0.7}hbox{Ga}_{0.3}hbox{As}$ Composite-Channel HEMT Using Gate-Sinking Technology

Eighty-nanometer-gate In_0.7Ga_0.3As/InAs/In_0.7Ga_0.3As composite-channel high-electron mobility transistors (HEMTs), which are fabricated using platinum buried gate as the Schottky contact metal, were evaluated for RF and logic application. After gate sinking at 250degC for 3 min, the device exhibited a high g_m value of 1590 mS/mm at V_d = 0.5 V, the current-gain cutoff frequency f_T was increased from 390 to 494 GHz, and the gate-delay time was decreased from 0.83 to 0.78 ps at supply voltage of 0.6 V. This is the highest f_T achieved for 80-nm-gate-length HEMT devices. These superior performances are attributed to the reduction of distance between gate and channel and the reduction of parasitic gate capacitances during the gate-sinking process. Moreover, such superior performances were achieved through a very simple and straightforward fabrication process with optimal epistructure of the device.     

Equivalent Circuit Model for the Gate Leakage Current in Broken Down $hbox{HfO}_{2}/hbox{TaN/TiN}$ Gate Stacks

We propose an equivalent circuit model for the post-breakdown (BD) current–voltage ( $I$–$V$) characteristics in $hbox{HfO}_{2}/hbox{TaN/TiN}$ gate stacks in n-MOSFETs. The model consists of two opposite-biased diodes with series resistances and a shunt leakage path. The circuit admits analytical solution using the Lambert $W$-function and is tested for both negative and positive gate biases in the voltage range of $-$1.5 to $+$1.5 V. We also show the versatility of the proposed approach to deal with the post-BD $I$– $V$ when source and drain contacts are grounded or floating and analyze the obtained results in terms of the charge available for conduction.      

Performance Enhancements in Scaled Strained-SiGe pMOSFETs With $ hbox{HfSiO}_{x}/hbox{TiSiN}$ Gate Stacks

The short-channel performance of compressively strained Si_0.77Ge_0.23 pMOSFETs with HfSiOx/TiSiN gate stacks has been characterized alongside that of unstrained-Si pMOSFETs. Strained-SiGe devices exhibit 80% mobility enhancement compared with Si control devices at an effective vertical field of 1 MV middotcm^-1. For the first time, the on-state drain-current enhancement of intrinsic strained-SiGe devices is shown to be approximately constant with scaling. Intrinsic strained-SiGe devices with 100-nm gate lengths exhibit 75% enhancement in maximum transconductance compared with Si control devices, using only ~20% Ge (~0.8% strain). The origin of the loss in performance enhancement commonly observed in strained-SiGe devices at short gate lengths is examined and found to be dominated by reduced boron diffusivity and increased parasitic series resistance in compressively strained SiGe devices compared with silicon control devices. The effective channel length was extracted from I- V measurements and was found to be 40% smaller in 100-nm silicon control devices than in SiGe devices having the same lithographic gate lengths, which is in good agreement with the metallurgical channel length predicted by TCAD process simulations. Self-heating due to the low thermal conductivity of SiGe is shown to have a negligible effect on the scaled-device performance. These findings demonstrate that the significant on-state performance gains of strained-SiGe pMOSFETs compared with bulk Si devices observed at long channel lengths are also obtainable in scaled devices if dopant diffusion, silicidation, and contact modules can be optimized for SiGe.     

Gate Influence on the Layout Sensitivity of $ hbox{Si}_{1 - x}hbox{Ge}_{x} hbox{S/D}$ and $hbox{Si}_{1 - y}hbox{C}_{y} hbox{S/D}$ Transistors Including an Analytical Model

We present a simulation study on the effect of the gate module on the channel stress in Si_1-xGe_x and Si_1-yC_y S/D MOS transistors. Stiff gate materials, such as titanium nitride, lead to a decreased channel stress, while a replacement-gate scheme allows the increase of the effectiveness of the Si_1-xGe_x and Si_1-yC_y S/D techniques significantly, independent of the gate material used. The drawback of using a replacement gate is that the channel stress becomes more sensitive to layout variations. In terms of effect on Si_1-xGe_x/Si_1-yC_y S/D stress generation, using a thin metal gate capped by polysilicon is similar to a full metal gate if the thin metal gate thickness exceeds 10 nm. Even metal gates as thin as 1 nm have a clear influence on the stress generation by Si_1-xGe_x/Si_1-yC_y S/D. Removing and redepositing the polysilicon layer while leaving the underlying metal gate unchanged increases the stress, although not to the same extent as for complete gate removal. A simple analytical model that estimates the stress in nested short-channel Si_1-xGe_x and Si_1-yC_y S/D transistors is presented. This model includes the effect of germanium/carbon concentration, active-area length, as well as the effect of gate length and the Young's modulus of the gate. Good qualitative agreement with 2-D finite element modeling is demonstrated.