一个电容阵列定制的100MS/s，9bit，0.43mW逐次逼近型模数转换器

本论文介绍了一个带定制电容阵列的低功耗9bit,100MS/s逐次比较型模数转换器。其电容阵列的基本电容单元是一个新型3D,电容值为1fF的MOM电容。除此之外,改进后的电容阵列结构和开关转换方式也降低了不少功耗。为了验证设计的有效性,该比较器在TSMC IP9M 65nm LP CMOS工艺下流片。测试结果如下：采样频率100MS/s,输入频率1MS/s时,有效位数（ENOB）为7.4,bit,信噪失真比（SNDR）为46.40dB,无杂散动态范围（SFDR）为62.31dB。整个芯片核面积为0.030mm2,在1.2V电源电压下功耗为0.43mW。该设计的品质因数（FOM）为23.75fJ/conv。     

ADI推出面向MRI市场的1ppm超高精度数模转换器

随着中国人口老龄化的加剧、医疗条件的改善以及中国政府大规模投资医疗保健产业等有利因素的推动,中国电子医疗市场尤其是高端医疗电子市场的需求不断增长。针对医院及专业医疗机构的高端医疗设备包括例如计算机断层扫描（CT）、核磁共振成像（MRI）、     

A 10-bit 300-MS/s asynchronous SAR ADC with strategy of optimizing settling time for capacitive DAC in 65 nm CMOS

A 10-bit 300-MS/s asynchronous SAR ADC in 65 nm CMOS is presented in this paper. To achieve low power, binary-weighed capacitive DAC is employed without any digital correction or calibration. Consequently, settling time for the capacitive DAC would be a dominant limiting factor for the ADC operating speed. A novel architecture is proposed to optimize the settling time for the capacitive DAC, which depends merely on the on-resistance of switches and the capacitance of unit capacitor and irrelevant to the resolution. Therefore, high-speed high-resolution SAR ADC is possible. What is deserved to highlight is that the architecture improves the ADC performance at a fraction of the cost, with only some capacitors and control logic added. Post-layout simulation has been made for the SAR ADC. At a 1.2-V supply voltage and a sampling rate of 300 MS/s, it consumes 1.27 mW and achieves an SNDR of 60 dB, an SFDR of 67.5 dB, with the Nyquist input. The SAR ADC occupies a core area of 450×380 μm².     

应用于高速CMOS图像传感器的具有动态功耗控制的12比特紧凑型列并行逐次逼近ADC

本文提出了一个应用于高速CMOS图像传感器的12比特列并行逐次逼近模数转换器。为了减小面积并使它的版图与两倍的像素间距相适应,采用了分段二进制权重开关电容数模转化器和交错结构的金属-氧化物-金属单位电容。为了消除单位电容上极板的寄生电容,提出了电场屏蔽的版图结构画法。提出了动态功耗控制技术,有效地降低了读出通道的功耗。用片外前台数字校准算法补偿开关电容数模转化器电容失配引起的非线性。芯片采用1P5M CMOS图像传感器工艺制造,其面积为20×2020μm2。采样率为833kS/s时,校准后的DNL、INL、ENOB分别为：0.9/-1 LSB、1/-1.1LSB、11.24比特。在1.8V的电源电压下,功耗为0.26 mW。随着帧率的减小,功耗线性减少。     

高分辨率SAR图像中矩形建筑物特性分析与三维重建

近年来不断发展成熟的合成孔径雷达技术将获取的图像分辨率提高到分米级.在高分辨率条件下,建筑物在SAR图像上表现出的空间信息更加丰富,结构特征更加明显.首先提出了分解模型对高分辨SAR图像中矩形建筑物的特性进行详细分析.在此模型中,散射效应根据不同的贡献来源被细分,以便于解析建筑物图像特征在不同的SAR成像条件下的几何结构和空间分布规律.然后基于建筑物图像表征的结构先验,提出了一种新的单幅高分辨率SAR图像建筑物检测和3-D重建算法,其中包括模型匹配的图像特征的提取,以及先验引导的重建过程.最后,选用了实际高分辨率SAR图像进行建筑物检测和三维重建实验并对重建结果进行了讨论.     

A DLL clock generator for a high speed A/D-converter with 1 ps jitter and skew calibrator with 1 ps precision in 0.35 μm CMOS

This paper presents a clock generator circuit for a high-speed analog-to-digital converter (ADC). A time-interleaved ADC requires accurate clocking for the converter fingers. The target ADC has 12 interleaved fingers each running at a speed of 166 MS/s, which corresponds to an equivalent sampling frequency of 2 GS/s. A delay-locked loop (DLL) based clock generator has been proposed to provide multiple clock signals for the converter. The DLL clock generator has been implemented with a 0.35 μm SiGe BiCMOS process (only MOS-transistor were used in DLL) by Austria Micro Systems and it occupies a 0.6 mm² silicon area. The measured jitter of the DLL is around 1 ps and the delay between phases can be adjusted using 1 ps precision.