利用简单电阻偏置网络实现的高线性度电流驱动型无源混频器

A high linearity current communicating passive mixer including the mixing cell and transimpedance amplifier(TIA) is introduced.It employs the resistor in the TIA to reduce the source voltage and the gate voltage of the mixing cell.The optimum linearity and the maximum symmetric switching operation are obtained at the same time.The mixer is implemented in a 0.25μm CMOS process.The test shows that it achieves an input third-order intercept point of 13.32 dBm,conversion gain of 5.52 dB,and a single sideband noise figure of 20 dB.     

低中频接收机中高线性度正交混频器设计

本文首先以Gilbert单元为核心,利用折叠结构,设计了一种具有高线性度的CMOS单通道混频器。该混频器的输入射频信号设用了600MHz、输出中频为8MHz。接着本文应用这一混频器设计了低中频接收机中所需的双通道正交混频器。经仿真得到其在3.3V的电源电压下,转换增益为8.4dB,输入1dB压缩点和IIP3分别达到0dBm和10dBm,单边带噪声系数为16.8dB。     

一种应用于DRM/DAB/DVB-H的噪声抵消和IP3改进的CMOS射频前端设计

本文给出了一种应用于数字广播标准的CMOS射频前端电路芯片,其包括宽带低噪声放大器、正交混频器和可变增益放大器,该前端能够支持200kHz-2GHz频率范围内的多种无线通信标准,该电路在没有牺牲其他电路性能包括电压增益和功耗的情况下,改善了NF和IP3。通过噪声抵消技术降低前端的NF,通过差分多栅晶体管结构（DMGTR）提高前端的IP3。dB线性可变增益放大器的增益控制通过采用工作在线性区的PMOS晶体管来实现。芯片采用0.18um CMOS工艺实现。测试结果表明在200kHz-2GHz范围内S11小于-11.4,增益变化范围在250MHz为12-42dB,在2GHz为4-36dB。单边带NF为3.1-6.1 dB。在中等增益情况下IIP3为-4.7-2.0dBm。整个前端在1.8V电源电压情况下功耗仅仅为36mW。     

应用于DRM/DAB系统的高转换增益及线性度优化的新结构混频器

This paper focuses on a new design of a down-conversion mixer for a low-IF wideband receiver.Based on the folded structure and differential multiple gated transistor(DMGTR) technique,a novel quadrature mixer with a high conversion gain,a moderate linearity,and a moderate NF is proposed.The mixer is designed and implemented in a 0.18-m CMOS process,and can operate in a frequency range from 150 kHz to 1.5 GHz.The circuit performance is confirmed by both simulation and measurement results.The measurement results exhibit a peak conversion gain of 13.35 dB,a high third order input referred intercept point of 14.85 dBm,and a moderate single side band noise figure of 10.67 dB.Moreover,the whole quadrature mixer core occupies a compact die area of 0.122 mm2.It consumes a current of 3.96 mA(excluding the output buffers) under a single supply voltage of 1.8 V.     

Noise-canceling and IP3 improved CMOS RF front-end for DRM/DAB/DVB-H applications

A CMOS RF (radio frequency) front-end for digital radio broadcasting applications is presented that contains a wideband LNA, I/Q-mixers and VGAs, supporting other various wireless communication standards in the ultra-wide frequency band from 200 kHz to 2 GHz as well. Improvement of the NF (noise figure) and IP3 (third-order intermodulation distortion) is attained without significant degradation of other performances like voltage gain and power consumption. The NF is minimized by noise-canceling technology, and the IP3 is improved by using differential multiple gate transistors (DMGTR). The dB-in-linear VGA (variable gain amplifier) exploits a single PMOS to achieve exponential gain control. The circuit is fabricated in 0.18-μm CMOS technology. The S_(11) of the RF front-end is lower than -11.4 dB over the whole band of 200 kHz-2 GHz. The variable gain range is 12-42 dB at 0.25 GHz and 4-36 dB at 2 GHz. The DSB NF at maximum gain is 3.1-6.1 dB. The IIP3 at middle gain is -4.7 to 0.2 dBm. It consumes a DC power of only 36 mW at 1.8 V supply.     

Design of a high linearity and high gain accuracy analog baseband circuit for DAB receiver

本文基于0.18 ?m RFCMOS工艺设计了一种用于DAB数字广播接收机的高线性度高增益精确度模拟基带电路。电路包含一个三阶有源RC复数滤波器（CF）和一个可编程增益放大器（PGA）。复数滤波器包含了自动调谐电路用于调谐滤波器受工艺电压温度等影响的通带特性。电路采用了具有大输出电流摆幅的AB类全差分运放,取代了传统设计中采用的A类全差分运放,实现了高线性度和增益精确度,同时降低了静态工作电流。本文提出了一个新型的基于MOS电阻的直流失调消除电路,大大的减小了电路的建立时间。另外,一种改进的开关电阻网络有效地消除了开关的电阻对可编程增益放大器的增益精确度的影响。 测试结果表明,电路可提供10-50dB的增益控制范围,增益步长为1dB,增益误差小于0.3dB。在增益为10dB的情况下,差分OIP3为23.3dBm。仿真结果表明,建立时间从100mS减小到了1mS。复数滤波器镜频抑制达到了40dB。电路在1.8V电源电压下消耗4.5mA电流。     

一种高线性度,宽动态范围的电流模乘法器/除法器

本文提出了一种高线性,宽动态范围的电流模乘法器/除法器(current mode multiplier/divider,CMM/D)。该CMM/D基于二极管的对数-反对数性质实现,因此能达到更宽的动态范围。其输出电流与温度、工艺参数无关,且电路采用高精度电流镜,因此能实现高线性。此外,该电路不需要为输入信号提供额外的偏置电流,节省了功耗。通过正确的选择输入输出端口,在不改变拓扑结构的前提下,该电路可以实现乘法,除法功能。本文提出的CMM/D采用0.25μm BCD 工艺实现,芯片面积为0.26×0.24mm₂。输入电流从0到200μA变化时,结果显示该CMM/D的最大静态误差为±1.8%, 总谐波失真为0.4%。     

采用balun低噪声放大器的5GHz 7.2-dB NF低功耗直接转换接收机前端电路

A 5GHz low power direct conversion receiver radio frequency front-end with balun LNA is presented. A hybrid common gate and common source structure balun LNA is adopted, and the capacitive cross-coupling technique is used to reduce the noise contribution of the common source transistor. To obtain low 1/f noise and high linearity, a current mode passive mixer is preferred and realized. A current mode switching scheme can switch between high and low gain modes, and meanwhile it can not only perform good linearity but save power consumption at low gain mode. The front-end chip is manufactured on a 0.13-μm CMOS process and occupies an active chip area of 1.2 mm². It achieves 35 dB conversion gain across 4.9-5.1 GHz, a noise figure of 7.2 dB and an IIP3 of -16.8 dBm, while consuming 28.4 mA from a 1.2 V power supply at high gain mode. Its conversion gain is 13 dB with an IIP3 of 5.2 dBm and consumes 21.5 mA at low gain mode.     

A 5 GHz 7.2 dB NF low power direct conversion receiver front-end with balun LNA

A 5GHz low power direct conversion receiver radio frequency front-end with balun LNA is presented. A hybrid common gate and common source structure balun LNA is adopted,and the capacitive cross-coupling technique is used to reduce the noise contribution of the common source transistor.To obtain low l/f noise and high linearity,a current mode passive mixer is preferred and realized.A current mode switching scheme can switch between high and low gain modes,and meanwhile it can not only perform good linearity but save power consumption at low gain mode.The front-end chip is manufactured on a 0.13-μm CMOS process and occupies an active chip area of 1.2 mm~2.It achieves 35 dB conversion gain across 4.9-5.1 GHz,a noise figure of 7.2 dB and an IIP3 of -16.8 dBm,while consuming 28.4 mA from a 1.2 V power supply at high gain mode.Its conversion gain is 13 dB with an IIP3 of 5.2 dBm and consumes 21.5 mA at low gain mode.     

应用于IMT-A与UWB系统的高线性度双频带混频器

The design and analysis of a reconfigurable dual-band down-conversion mixer for IMT-advanced(3.4–3.6 GHz) and UWB(4.2–4.8 GHz) applications are presented.Based on a folded double-balanced Gilbert cell,which is well known for its low voltage,simplicity and well balanced performance,the mixer adopts a capacitive cross-coupling technique for input matching and performance improvement.Switched capacitors and resistors are added to shift the working bands.Fabricated in a TSMC 0.13 m process,the test results show flat conversion gains from 9.6 to 10.3 d B on the IMT-A band and from 9.7 to 10.4 d B on the UWB band,with a noise figure of about 15 d B on both bands.The input third-order intercept points(IIP3) are about 7.3 d Bm on both of the frequency bands.The whole chip consumes 11 m W under 1.2 V supply and the total area of the layout is 0.760.65 mm2.     

一种适用于0.8VCMOS助听器的电流模前馈增益控制系统

摘要：本文介绍了一种适用于助听器前端系统的电流模前馈增益控制系统。和传统自动增益控制系统相比,电流模前馈增益控制通过数字增益控制码来实现前端系统总谐波失真的显著降低。为了从麦克风微弱的输出信号中得到数字控制码, 本文提出了用电流模实现的整流电路和电流模状态控制电路.该设计基于0.13微米CMOS工艺. 测试表明芯片可工作于0.6V的电源电压.在电源电压为0.8V下, 输出摆幅500mVp-p的信号总谐波失真在0.06% (-64dB)以下, 且功耗控制在40uW以内.另外,系统的等效输入噪声达到4uVrms,最大增益保持在33dB.