一个适用于短沟HALO结构MOS器件的直接隧穿栅电流模型

对沟道长度从10μm到0.13μm,栅氧化层厚度为2.5nm的HALO结构nMOS器件的直接隧穿栅电流进行了研究,得到了一个适用于短沟道HALO结构MOS器件的直接隧穿栅电流模型.随着沟道尺寸的缩短,源/漏扩展区占据沟道的比例越来越大,源漏扩展区的影响不再可以忽略不计.文中考虑了源/漏扩展区对直接隧穿栅电流的影响,给出了适用于不同HALO掺杂剂量的超薄栅(2～4nm)短沟(0.13～0.25μm)nMOS器件的半经验直接隧穿栅电流模拟表达式.     

一个适用于短沟HALO结构MOS器件的直接隧穿栅电流模型

对沟道长度从10μm到0.13μm,栅氧化层厚度为2.5nm的HALO结构nMOS器件的直接隧穿栅电流进行了研究,得到了一个适用于短沟道HALO结构MOS器件的直接隧穿栅电流模型.随着沟道尺寸的缩短,源/漏扩展区占据沟道的比例越来越大,源漏扩展区的影响不再可以忽略不计.文中考虑了源/漏扩展区对直接隧穿栅电流的影响,给出了适用于不同HALO掺杂剂量的超薄栅(2～4nm)短沟(0.13～0.25μm)nMOS器件的半经验直接隧穿栅电流模拟表达式.     

考虑源漏隧穿的DG MOSFET弹道输运及其模拟

在经典弹道输运模型中引入源漏隧穿(S/D tunneling),采用WKB方法计算载流子源漏隧穿几率,对薄硅层(硅层厚度为1nm)DG(dual gate)MOSFETs的器件特性进行了模拟.模拟结果表明当沟道长度为10nm时,源漏隧穿电流在关态电流中占25%,在开态电流中占5%.随着沟道长度进一步减小,源漏隧穿比例进一步增大.因此,模拟必须包括源漏隧穿.     

考虑源漏隧穿的DG MOSFET弹道输运及其模拟

在经典弹道输运模型中引入源漏隧穿 (S/ D tunneling) ,采用 WKB方法计算载流子源漏隧穿几率 ,对薄硅层(硅层厚度为 1nm) DG(dual gate) MOSFETs的器件特性进行了模拟 .模拟结果表明当沟道长度为 10 nm时 ,源漏隧穿电流在关态电流中占 2 5 % ,在开态电流中占 5 % .随着沟道长度进一步减小 ,源漏隧穿比例进一步增大 .因此 ,模拟必须包括源漏隧穿 .     

量子效应和小型化对隧穿晶体管特性的影响

基于二维器件仿真工具,研究了量子效应和小型化对双栅隧穿场效应晶体管的特性和可靠性的影响.隧穿晶体管中的量子效应除了带间隧穿,还包括量子统计效应和垂直沟道方向的量子限制效应.研究表明,量子统计效应和量子限制效应对隧穿晶体管的电流电压特性,特别是正偏压温度不稳定性(PBTI)是非常重要的.另外,随着沟道长度和体硅厚度的缩小,隧穿晶体管的电流电压特性和可靠性都得到了改善,但在保持相同等效氧化层厚度的情况下,使用高介电常数的栅介质不会改善器件的电流电压特性及可靠性.     

堆叠栅介质MOS器件栅极漏电流的计算模型

采用顺序隧穿理论和传输哈密顿方法并考虑沟道表面量子化效应,建立了高介电常数堆叠栅介质MOS器件栅极漏电流的顺序隧穿模型。利用该模型数值,研究了Si3N4/SiO2、Al2O3/SiO2、HfO2/SiO2和La2O3/SiO2四种堆叠栅介质结构MOS器件的栅极漏电流随栅极电压和等效氧化层厚度变化的关系。依据计算结果,讨论了堆叠栅介质MOS器件按比例缩小的前景。     

超薄栅介质MOSFET直接隧穿电流自洽解模型

采用自洽解方法求解一维薛定谔方程和二维泊松方程,得到电子的量子化能级和相应的浓度分布,利用MWKB方法计算电子隧穿几率,从而得到不同栅偏置下超薄栅介质MOSFET的直接隧穿电流模型。一维模拟结果与实验数据十分吻合,表明了模型的准确性和实用性。二维模拟结果表明,低栅压下,沟道边缘隧穿电流远大于沟道中心隧穿电流,沟道各处的隧穿电流均大于一维模拟结果;高栅压下,隧穿电流在沟道的分布趋于一致,且逼近一维模拟结果。     

一种新型隧穿场效应晶体管

提出了一种新型隧穿场效应晶体管(TFET)结构,该结构通过在常规TFET靠近器件栅氧化层一侧的漏-体结界面引入一薄层二氧化硅(隔离区),从而减小甚至阻断反向栅压情况下漏端到体端的带带隧穿(BTBT),减弱TFET的双极效应,实现大幅度降低器件泄漏电流的目的。利用TCAD仿真工具对基于部分耗尽绝缘体上硅(PDSOI)和全耗尽绝缘体上硅(FDSOI)的TFET和新型TFET结构进行了仿真与对比。仿真结果表明,当隔离区宽度为2 nm,高度大于10 nm时,可阻断PDSOI TFET的BTBT,其泄漏电流下降了4个数量级;而基于FDSOI的TFET无法彻底消除BTBT和双极效应,其泄漏电流下降了2个数量级。因此新型结构更适合于PDSOI TFET。     

纳米级MOS器件中电子直接隧穿电流的研究

文章从分析量子力学效应对纳米级MOS器件的影响出发,采用顺序隧穿理论和巴丁传输哈密顿方法,建立了纳米级MOS器件直接隧穿栅电流的计算模型。通过和实验数据的比较,证明了该模型的有效性。计算结果表明,在纳米级MOS器件中,采用SiO2作栅介质时,1.5 nm厚度是按比例缩小的极限。该计算模型还可以用于高介电常数栅介质和多层栅介质MOS器件的直接隧穿电流的计算。     

弹道MOSFET中栅隧穿电流的自洽计算

本文用非平衡Green函数方法和模式表象技术对弹道MOSFET中的栅隧穿电流进行了研究.为了简化计算,我们把栅分解成一系列的小栅并用相应的自能项来概括它们.计算结果表明栅电势和栅绝缘层厚度是起主导作用的因素.尽管沟道区态密度的复杂变化和硅层的厚度对栅隧穿电流也有影响,但并不显著.     

一种具有高K栅介质与低k侧壁介质的PNPN型隧穿晶体管研究

本文提出了一种具有高K栅介质及低K侧壁介质的PNPN型隧穿场效应晶体管,并通过二维仿真研究了栅电场和侧壁电场对隧穿场效应晶体管性能的影响。结果表明高K栅介质可以增强栅对沟道的控制能力,同时低K侧墙介质有助于增大带带隧穿的几率。具有这种结构的隧穿场效应晶体管器件具有很好的开关特性、大的开态电流以及良好的工艺容差。该器件可以应用于低功耗领域,并有可能作为下一代CMOS技术的替代者之一。     

A PNPN tunnel field-effect transistor with high-k gate and Iow-k fringe dielectrics

A PNPN tunnel field effect transistor(TFET) with a high-k gate dielectric and a low-k fringe dielectric is introduced.The effects of the gate and fringe electric fields on the TFET’s performance were investigated through two-dimensional simulations.The results showed that a high gate dielectric constant is preferable for enhancing the gate control over the channel,while a low fringe dielectric constant is useful to increase the band-to-band tunneling probability.The TFET device with the proposed structure has good switching characteristics,enhanced on-state current,and high process tolerance.It is suitable for low-power applications and could become a potential substitute in next-generation complementary metal-oxide-semiconductor technology.     

Two-dimensional analytical model of double-gate tunnel FETs with interface trapped charges including effects of channel mobile charge carriers

A two-dimensional analytical model of double-gate(DG) tunneling field-effect transistors(TFETs) with interface trapped charges is proposed in this paper. The influence of the channel mobile charges on the potential profile is also taken into account in order to improve the accuracy of the models. On the basis of potential profile, the electric field is derived and the expression for the drain current is obtained by integrating the BTBT generation rate. The model can be used to study the impact of interface trapped charges on the surface potential, the shortest tunneling length, the drain current and the threshold voltage for varying interface trapped charge densities, length of damaged region as well as the structural parameters of the DG TFET and can also be utilized to design the charge trapped memory devices based on TFET. The biggest advantage of this model is that it is more accurate, and in its expression there are no fitting parameters with small calculating amount. Very good agreements for both the potential, drain current and threshold voltage are observed between the model calculations and the simulated results.     

Insights into channel potentials and electron quasi-Fermi potentials for DGtunnel FETs

A detailed investigation carried out, with the help of extensive simulations using the TCAD device simulator Sentaurus, with the aim of achieving an understanding of the effects of variations in gate and drain potentials on the device characteristics of a silicon double-gate tunnel field effect transistor (Si-DG TFET) is reported in this paper. The investigation is mainly aimed at studying electrical properties such as the electric potential, the electron density, and the electron quasi-Fermi potential in a channel. From the simulation results, it is found that the electrical properties in the channel region of the DG TFET are different from those for a DG MOSFET. It is observed that the central channel potential of the DG TFET is not pinned to a fixed potential even after the threshold is passed (as in the case of the DG MOSFET); instead, it initially increases and later on decreases with increasing gate voltage, and this is also the behavior exhibited by the surface potential of the device. However, the drain current always increases with the applied gate voltage. It is also observed that the electron quasi-Fermi potential (eQFP) decreases as the channel potential starts to decrease, and there are hiphops in the channel eQFP for higher applied drain voltages. The channel regime resistance is also observed for higher gate length, which has a great effect on the I-V characteristics of the DG TFET device. These channel regime electrical properties will be very useful for determining the tunneling current; thus these results may have further uses in developing analytical current models.     

Gate leakage properties of MOS devices with tri-layer high-k gate dielectric

Gate leakage of deep-submicron MOSFET with stack high-k dielectrics as gate insulator is studied by building a model of tunneling current. Validity of the model is checked when it is used for MOSFET with SiO₂ and high-k dielectric material as gate dielectrics, respectively, and simulated results exhibit good agreement with experimental data. The model is successfully used for a tri-layer gate-dielectric structure of HfON/HfO₂/HfSiON with a U-shape nitrogen profile and a like-Si/SiO₂ interface, which is proposed to solve the problems of boron diffusion into channel region and high interface-state density between Si and high-k dielectric. By using the model, the optimum structural parameters of the tri-layer dielectric can be determined. For example, for an equivalent oxide thickness of 2.0 nm, the tri-layer gate-dielectric MOS capacitor with 0.3-nm HfON, 0.5-nm HfO₂ and 1.2-nm HfSiON exhibits the lowest gate leakage.     

Impact of parameter fluctuations on RF stability performance of DG Tunnel FET

This paper presents the impact of parameter fluctuation due to process variation on radio frequency (RF) stability performance of double gate tunnel FET (DG TFET). The influence of parameter fluctuation due to process variation leads to DG TFET performance degradation. The RF figures of merit (FoM) such as cut-off frequency (f_t), maximum oscillation frequency (f_max) along with stability factor for different silicon body thickness, gate oxide thickness and gate contact alignment are obtained from extracted device parameters through numerical simulation. The impact of parameter fluctuation of silicon body thickness, gate oxide thickness and gate contact alignment was found significant and the result provides design guidelines of DG TFET for RF applications.     

长沟道圆柱围栅高K栅栈结构MOSFETs器件的直接隧穿电流解析模型

An analytical direct tunneling gate current model for cylindrical surrounding gate（CSG） MOSFETs with high-k gate stacks is developed. It is found that the direct tunneling gate current is a strong function of the gate＇s oxide thickness, but that it is less affected by the change in channel radius. It is also revealed that when the thickness of the equivalent oxide is constant, the thinner the first layer, the smaller the direct tunneling gate current.Moreover, it can be seen that the dielectric with a higher dielectric constant shows a lower tunneling current than expected. The accuracy of the analytical model is verified by the good agreement of its results with those obtained by the three-dimensional numerical device simulator ISE.     

A low-frequency noise model for advanced gate-stack MOSFETs

A new unified noise model is presented that accurately predicts the low-frequency noise spectrum exhibited by MOSFETs with high dielectric constant (high-k), multi-stack gate dielectrics. The proposed multi-stack unified noise (MSUN) model is based on number and correlated mobility fluctuations theory developed for native oxide MOSFETs, and offers scalability with respect to the high-k/interfacial layer thicknesses. In addition, it incorporates the various electronic properties of high-k/interfacial layer materials such as energy barrier heights between different gate layers, and dielectric trap density with respect to band energy and position in the dielectric. For verification of the new model, the low-frequency noise, DC and conventional split C-V measurements were performed in the 78-350 K temperature range on TaSiN/HfO₂ n-channel MOSFETs. The interfacial layer in these devices was either thermal SiO₂ by Stress Relieved Pre-Oxide (SRPO) pretreatment or chemical SiO₂ resulting from standard RCA (Radio Corporation of America) clean process. Using the experimental noise data, the channel carrier number fluctuations mechanism was at first established to be the underlying mechanism responsible for the noise observed at all temperatures considered. Secondly, the normalized noise exhibited a weak dependence on temperature implying that the soft optical phonons, although known to result in mobility degradation, have no effect on the noise characteristics in these high-k gate stack MOSFETs. Finally, the new model was shown to be in excellent agreement with the measured noise in 1-100 Hz frequency range at temperatures of 78-350 K for both gate stacks.     

具有复合k介质埋层的高压SOI器件解析模型

An analytical model for a novel high voltage silicon-on-insulator device with composite-k(relative permittivity) dielectric buried layer(CK SOI) is proposed. In this structure, the composite-k buried layer is composed by alternating Si3N4 and low-k(k D 2.65) dielectric in the lateral direction. Due to the composite-k buried layer, the breakdown voltage(BV) is improved both by the vertical and lateral direction. Taking the modulation effect of accumulated interface holes into account, an analytical model is developed. In the blocking state, the proposed model revealed the mechanism of hole accumulation above the Si3N4 buried layer and investigated the modulation effect of accumulated holes on the two-dimensional(2-D) potential and electric field distributions. This analytical model is verified by the simulation results. Compared with the low-k dielectric buried layer SOI(LK SOI), simulation results show that the BV for CK SOI is enhanced by 21% and the specific on-resistance is reduced by 32%, respectively.     

A surface potential based drain current model for asymmetric double gate MOSFETs

In this paper, we present a generic surface potential based current voltage (I-V) model for doped or undoped asymmetric double gate (DG) MOSFET. The model is derived from the 1-D Poisson’s equation with all the charge terms included and the channel potential is solved for the asymmetric operation of DG MOSFET based on the Newton-Raphson iterative method. A noncharge sheet based drain current model based on the Pao-Sah’s double integral method is formulated in terms of front and back gate surface potentials at the source and drain end. The model is able to clearly show the dependence of the front and back surface potential and the drain current on the terminal voltages, gate oxide thicknesses, channel doping concentrations and the Silicon body thickness and a good agreement is observed with the 2-D numerical simulation results.