An accurate model for dynamic crosstalk analysis of CMOS gate driven on-chip interconnects using FDTD method

An accurate and time efficient model of CMOS gate driven coupled-multiple interconnects is presented in this paper for crosstalk induced propagation delay and peak voltage measurements. The proposed model is developed using the finite difference time domain (FDTD) technique for coupled RLC interconnects, whereas the alpha power law model is used to represent the transistors in a CMOS driver. As verified by the HSPICE simulation results, the transient response of the proposed model demonstrates high accuracy. Over the random number of test cases, crosstalk induced peak voltage and propagation delay show average errors of 1.1% and 4.3%, respectively, with respect to HSPICE results.     

An analytical approach to dynamic crosstalk in coupled interconnects

This paper deals with waveform analysis, crosstalk peak and delay estimation of CMOS gate driven capacitively and inductively coupled interconnects. Simultaneously switching inputs for the coupled interconnects are considered. A transmission line-based coupled model of interconnect is used for analysis. Alpha-power Law model of MOS transistor is used to represent the transistors in CMOS driver. Peaks and delays at far-end of victim line are estimated for conditions when the inputs to the two coupled interconnects are switching in-phase and out-of-phase. The comparison of analytically obtained results with SPICE simulations show that the proposed model captures noise peak and their timing; 90% propagation delay; transition time delay and waveform shape with good accuracy, such as not more than 5% error in crosstalk peak estimation.     

FDTD based transition time dependent crosstalk analysis for coupled RLC interconnects

The performance of high density chips operating in the GHz range is mostly affected by on-chip interconnects. The interconnect delay depends on many factors, a few of them are inputs toggling patterns, line ＆ coupling parasitics, input rise/fall time and source/load characteristics. The transition time of the input is of prime importance in high speed circuits. This paper addresses the FDTD based analysis of transition time effects on functional and dynamic crosstalk. The analysis is carried out for equal and unequal transition times of coupled inputs. The analysis of the effects of unequal rise time is equally important because practically, it is quite common to have mismatching in the rise time of the signals transmitting through different length wires. To demonstrate the effects, two distributed RLC lines coupled inductively and capacitively are taken into consideration. The FDTD technique is used because it gives accurate results and carries time domain analysis of coupled lines. The number of lumps in SPICE simulations is considered the same as those of spatial segments. To validate the FDTD computed results, SPICE simulations are run and results are compared. A good agreement of the computed results has been observed with respect to SPICE simulated results. An average error of less than 3.2% is observed in the computation of the performance parameters using the proposed method.     

Crosstalk noise modeling of multiwall carbon nanotube (MWCNT) interconnects using finite-difference time-domain (FDTD) technique

This paper presents an accurate and efficient model for the transient analysis of multiwall carbon nanotubes (MWCNT) using finite-difference time-domain (FDTD) method. The proposed model can be essentially used to analyze the functional and dynamic crosstalk effects of coupled-two MWCNT interconnect lines. Using the proposed model the voltage and current can be accurately estimated at any point on the interconnect line and furthermore, the model can be extended to coupled-n interconnect lines with a low computational cost. Crosstalk induced propagation delay, peak voltage, and its timing instance are measured using the proposed model and validated by comparing it to the HSPICE simulations. Over a random number of test cases it is observed that the average error in estimating the noise peak voltage on a victim line is less than 1%. The proposed model is extremely useful for accurate estimation of crosstalk induced performance parameters of MWCNT interconnects.     

Compact distributed RLC interconnect models-Part II: Coupled linetransient expressions and peak crosstalk in multilevel networks

For pt. I see ibid., vol. 47, no. 11, (Nov. 2000). Novel compact expressions that describe the transient response of high-speed resistance, inductance, and capacitance (RLC) coupled interconnects are rigorously derived. These new distributed rlc models reveal that peak crosstalk voltage is over 60% larger for 3 GHz high-speed interconnects than predicted by current distributed RC models. Simplified forms of the compact models enable physical insight and accurate estimation of peak crosstalk voltage between two and three distributed RLC interconnects     

Crosstalk modeling for coupled RLC interconnects with application to shield insertion

On-chip interconnect delay and crosstalk noise have become significant bottlenecks in the performance and signal integrity of deep submicrometer VLSI circuits. A crosstalk noise model for both identical and nonidentical coupled resistance-inductance-capacitance (RLC) interconnects is developed based on a decoupling technique exhibiting an average error of 6.8% as compared to SPICE. The crosstalk noise model, together with a proposed concept of effective mutual inductance, is applied to evaluate the effectiveness of the shielding technique.     

Analytical timing model for inductance-dominant interconnect based on traveling wave propagation

As accurate and efficient timing prediction is very important for integrated circuit design, an analytical timing model for inductive-effect dominated resistance-inductance-capacitance (RLC) transmission line with resistive driver and capacitive load is proposed by virtue of traveling wave propagation and perturbation technique. This model is theoretically stable and computationally efficient. Comparison with other analytical and SPICE models illustrates that this timing model can achieve excellent accuracy for inductance-dominant interconnect. Incorporating with decoupling technique, this model could be readily extended to coupled interconnects.     

Crosstalk analysis of simultaneously switching interconnects

This article focusses on the waveform analysis and crosstalk peak estimation at far-end of victim line for simultaneously switching inputs with resistive drivers. A low loss coupled transmission line-model of interconnect is used for analytical purpose. Noise peaks are estimated for the conditions when inputs to two coupled interconnects are switching in-phase and out-of-phase. Waveforms are analysed in general with homogeneous and non-homogeneous drivers for unipolar inputs. The driver is modelled as linear resistance. Comparison of the analytical results with simulation programme with integrated circuit emphasis (SPICE)-extracted results shows that the error involved is less than 2% and 5% for in-phase and out-of-phase switching, respectively. The comparisons of analytically obtained results with SPICE simulations show that the proposed model captures noise peaks, their timings and waveform shape for all switching conditions with an average error of less than 4%.     

CAD-oriented equivalent-circuit modeling of on-chip interconnectson lossy silicon substrate

A new, comprehensive CAD-oriented modeling methodology for single and coupled interconnects on an Si-SiO₂ substrate is presented. The modeling technique uses a modified quasi-static spectral domain electromagnetic analysis which takes into account the skin effect in the semiconducting substrate. Equivalent-circuit models with only ideal lumped elements, representing the broadband characteristics of the interconnects, are extracted. The response of the proposed SPICE compatible equivalent-circuit models is shown to be in good agreement with the frequency-dependent transmission line characteristics of single and general coupled on-chip interconnects     

Minimization of delay and crosstalk in high-speed VLSIinterconnects

Design optimization of time responses of high-speed VLSI interconnects modeled by distributed coupled transmission line networks is presented. The problem of simultaneous minimization of crosstalk, delay and reflection is formulated into minimax optimization. Design variables include physical/geometrical parameters of the interconnects and parameters in terminating/matching networks. A recently published simulation and sensitivity analysis technique for multiconductor transmission lines is expanded to directly address the VLSI interconnect environment. The new approach permits efficient physical/geometrical oriented interconnect design using exact gradient based minimax optimization. Examples of interconnect optimization demonstrate significant reductions of crosstalk, delay, distortion and reflection at all vital connection ports. The technique developed is an important step towards optimal design of circuit interconnects for high-speed digital computers and communication systems     

Analytical models and algorithms for the efficient signal integrity verification of inductance-effect-prominent multicoupled VLSI circuit interconnects

Novel signal integrity verification models and algorithms for inductance-effect- prominent RLC interconnect lines are developed by using a traveling-wave-based waveform approximation (TWA) technique. The multicoupled line responses are decoupled into the eigenmodes of the system in order to exploit the TWA technique. Then, the response signals are mathematically represented by the linear combination of each eigenmode response based on TWA, followed by reporting the signal integrity models and algorithms for the multicoupled lines. The signal integrity of VLSI circuit interconnects is complicatedly correlated with input signal switching-patterns, layout geometry, and termination conditions. It is shown that the technique can be efficiently employed for complicated multicoupled interconnect lines with various termination conditions and the signal transients based on the technique have excellent agreement with SPICE simulations. Thus, with the proposed technique, the switching-dependent signal delay, crosstalk, ringing, and glitches of the inductance-effect-prominent RLC interconnect lines can be accurately as well as efficiently determined.     

Moment computation of lumped and distributed coupled RC trees withapplication to delay and crosstalk estimation

In today's deep submicrometer technology the coupling capacitances among individual on-chip RC trees have an essential effect on the signal delay and crosstalk, and the interconnects should be modeled as coupled RC trees. In this paper we provide simple exact explicit formulas for the Elmore delay and higher order voltage moments and a linear order recursive algorithm for the voltage moment computation for lumped and distributed coupled RC trees. By using the formulas and algorithms, the moment-matching method can be efficiently implemented to deal with delay and crosstalk estimation, model order reduction, and optimal design of interconnects. As an application of the algorithm, we provide a new efficient and accurate model for crosstalk estimation in coupled RC trees. Simulation results show it works better than existing methods     

RLC传输线的精确矩模型及其在互连线网时延估计中的应用

快速估计互连线网的信号传输特性是VLSI设计中的重要问题,矩匹配是目前的主要方法.本文给出了获得RLC传输线精确矩模型的一个简单方法,避免了以往方法复杂的推导.文中还提出了互连线时延估计的一个新方法,这一方法不仅可用于目前通常的二阶模型,还可对高阶模型进行估计.     

Efficient timing modelling of coupled inductance dominant RLC interconnects

An efficient timing modelling scheme for coupled inductance dominant resistance inductance capacitance (RLC) interconnects is presented. The transfer function in the Laplace domain is expanded in a series of rational, polynomial and exponential products, the time-domain responses of which can be computed analytically. The resulting time-domain response has fast convergence yet maintains high fidelity of non-monotonic characteristics of RLC transmission line circuits. By using an analytical decoupling technique, an efficient analytical timing model for coupled inductance dominant RLC interconnects is constructed.     

Analysis of lossy multiconductor transmission lines using theasymptotic waveform evaluation technique

A method is described for the transient analysis of lossy coupled transmission line networks with nonlinear elements. The method combines the asymptotic waveform evaluation technique with a piecewise decomposition algorithm. Two to three orders of magnitude speedup can be achieved relative to previously published methods with comparable accuracy. The method is useful for delay and crosstalk simulation of high speed VLSI interconnects     

Crosstalk analysis for a CMOS gate driven inductively and capacitively coupled interconnects

This paper deals with crosstalk analysis of a CMOS driven capacitively and inductively coupled interconnect. The Alpha Power Law model of MOS transistor is used to represent a CMOS driver. This is combined with a transmission line-based coupled RLC model of interconnect to develop a composite model for analytical purpose. On this basis a transient analysis of crosstalk noise is carried out. Comparison of the analytical results with SPICE extracted results shows that the error involved is nominal.     

Dynamic Power Model of CMOS Gates Driving Transmission Lines Based on Fourier Analysis

This paper presents an analytical dynamic power model of CMOS gates driving transmission lines with distributed RLC parameters. It is shown that at high signal frequency, where the output voltage at the termination of a transmission line may not reach the steady state during a signal period, the charge and voltage at the end of the period become the initial conditions of the following periods and have a significant effect on dynamic power consumption. The proposed model takes these initial conditions into account, since it is based on Fourier series analysis. In this model, the dynamic power consumption is approximated by the summation of the first several Fourier-series-based terms. The accuracy of the model increases with the number of series terms, and arbitrary accuracy can be obtained by including appropriate number of the terms in the model. The model is much faster than simulation program with integrated circuit emphasis (SPICE), and its computational complexity is linear with the number of terms included. The model is also extended to CMOS gates driving distributed RLC trees and coupled multiconductor transmission lines.     

The Effect of Signal Activity on Propagation Delay of CMOS Logic Gates Driving Coupled On-Chip Interconnections

The effect of interconnect coupling capacitances on neighboring CMOS logic gates driving coupled interconnections strongly depends upon signal activity. A transient analysis of two capacitively coupled CMOS logic gates is presented in this paper for different combinations of signal activity. The uncertainty of the effective load capacitance and propagation delay due to signal activity is addressed. Analytical expressions characterizing the output voltage and propagation delay are also presented for different signal activity conditions. The propagation delay based on these analytical expressions is within 3% as compared to SPICE, while the estimated delay neglecting the difference between the load capacitances can exceed 45%. The logic gates should be properly sized to balance the load capacitances in order to minimize any uncertainty in the delay and load. The peak noise voltage on a quiet interconnection determined from the analytical expressions is within 4% of SPICE. The peak noise voltage on a quiet interconnection can be minimized if the effective output conductance of the quiet logic gate driving the interconnect is increased.     

Shielding effect of on-chip interconnect inductance

Interconnect inductance introduces a shielding effect which decreases the effective capacitance seen by the driver of a circuit, reducing the gate delay. A model of the effective capacitance of an RLC load driven by a CMOS inverter is presented. The interconnect inductance decreases the gate delay and increases the time required for the signal to propagate across an interconnect, reducing the overall delay to drive an RLC load. Ignoring the line inductance overestimates the circuit delay, inefficiently oversizing the circuit driver. Considering line inductance in the design process saves gate area, reducing dynamic power dissipation. Average reductions in power of 17% and area of 29% are achieved for example circuits. An accurate model for a CMOS inverter and an RLC load is used to characterize the propagation delay. The accuracy of the delay model is within an average error of less than 9% as compared to SPICE.     

Characteristic analysis of coupled HTS interconnects withtwo-dimensional FDTD

In this work, the frequency-dependent RLGC parameters of high-speed coupled high T_c superconductor (HTS) interconnects are extracted with a two-dimensional (2-D) FDTD algorithm. The response signals of an HTS interconnect circuit and a normal Al interconnect circuit are simulated and compared, showing that not only the signal dispersion, delay, and magnitude decay of HTS interconnects are smaller than that of Al interconnects, the crosstalk of HTS interconnects is much smaller, too