Impact of doped boron concentration in emitter on high- and low-dose-rate damage in lateral PNP transistors

The characteristics of radiation damage under a high or low dose rate in lateral PNP transistors with a heavily or lightly doped emitter is investigated. Experimental results show that as the total dose increases, the base current of transistors would increase and the current gain decreases. Furthermore, more degradation has been found in lightly-doped PNP transistors, and an abnormal effect is observed in heavily doped transistors. The role of radiation defects, especially the double effects of oxide trapped charge, is discussed in heavily or lightly doped transistors. Finally,through comparison between the high- and low-dose-rate response of the collector current in heavily doped lateral PNP transistors, the abnormal effect can be attributed to the annealing of the oxide trapped charge. The response of the collector current, in heavily doped PNP transistors under high- and low-dose-rate irradiation is described in detail.     

发射区硼掺杂浓度对横向PNP晶体管高低剂量率辐射损伤的影响

本文研究了发射区重硼掺杂和轻硼掺杂横向PNP晶体管的高低剂量率辐照损伤特性。实验结果表明,随总剂量的增加,晶体管基极电流增大,电流增益下降,且轻掺杂PNP晶体管的退化更为严重。文中讨论了辐照感生缺陷在发射区重掺杂和轻掺杂晶体管退化中的作用,特别是氧化物正电荷的双重作用。最后,文章详细论述了高低剂量率辐照下,重掺杂PNP晶体管集电极电流IC的辐照响应。     

In situ phosphorus-doped polysilicon emitter technology for veryhigh-speed, small emitter bipolar transistors

In situ phosphorus-doped polysilicon emitter (IDP) technology for very high-speed, small-emitter bipolar transistors is studied. The device characteristics of IDP transistors are evaluated and compared with those of conventional ion-implanted polysilicon emitter transistors. IDP technology is used to fabricate double polysilicon self-aligned bipolar transistors and the I-V characteristics, current gain, transconductance, emitter resistance, and cut-off frequency are measured. In conventional transistors, these device characteristics degrade when the emitter is small because of the emitter-peripheral-thick-polysilicon effect. In IDP transistors, the peripheral effect is completely suppressed and large-grain, high-mobility polysilicon can be used. The device characteristics, therefore, are not degraded in sub-0.2-μm emitter transistors. In addition, large-grain, high-mobility, and high phosphorus concentration IDP films increase current gain and lower emitter resistance. The use of IDP technology to build very small emitter transistors is evaluated and discussed     

双极晶体管发射极电阻的提取方法及应用研究

以双多晶自对准互补双极器件中NPN双极晶体管为例,阐述了发射极电阻提取的基本原理和数学方法。在大电流情况下,NPN管的基极电流偏离理想电流是发射极串联电阻效应引起的。该提取方法综合考虑了辐照过程中NPN管的电流增益退化特性,分析了总剂量辐照效应对NPN管的损伤机理和模式。该提取方法适用于多晶硅发射极器件,也适用于SiGe HBT器件。     

Transistor characteristics with Ta2O5 gatedielectric

As the gate oxide thickness decreases below 2 nm, the gate leakage current increases dramatically due to direct tunneling current. This large gate leakage current will be an obstacle to reducing gate oxide thickness for the high speed operation of future devices. A MOS transistor with Ta₂O₅ gate dielectric is fabricated and characterized as a possible replacement for MOS transistors with ultra-thin gate silicon dioxide. Mobility, I_d-V_d, I_d-V_g, gate leakage current, and capacitance-voltage (C-V) characteristics of Ta₂O₅ transistors are evaluated and compared with SiO₂ transistors. The gate leakage current is three to five orders smaller for Ta₂O₅ transistors than SiO₂ transistors     

非晶硅发射区双极晶体管的低温特性

本文研究了非晶硅发射区双极晶体管的低温特性，得出了如下结论：低温下电流增益随基区杂质浓度的上升而下降，不同于常规同质结双极晶体管的情况，集电极电流则随基区杂质浓度的上升而上升。这些结果将为低温双极晶体管的设计提供理论依据。     

Subthreshold conduction in silicon-on-sapphire transistors

The subthreshold conduction in silicon-on-sapphire MOS transistors has been studied both theoretically and experimentally. A simple model to describe the subthreshold conduction current for both thick films and thin films is derived in terms of charges in the silicon and charges at the silicon-silicon dioxide and silicon-sapphire interfaces. The model has been extended to cover short-channel transistors by application of charge conservation under the channel region. It is shown that the subthreshold conduction current for a SOS-MOS transistor has a form similar to that found in bulk transistors, but with modification of the terms due to the finite silicon film thickness and the unique geometry of the SOS-MOS transistor. The general form of the model has been confirmed by measurement of the subthreshold current on several hundred SOS-MOS transistors of different geometries manufactured by various companies.     

A four-quadrant current multiplier/divider cell with four transistors

We propose a four quadrant six transistor current multiplier cell based on the translinear principle. The cell is further modified by using resistive feedback to remove two PNP transistors hence reducing the total transistor count to four NPN transistors only. This not only eliminates the problem of mismatch between the two transistor types but allows the cell to operate both as a current multiplier/divider depending on the resistive feedback ratio. The modified cell can also multiply mixed current/voltage signals and operates equally well with NMOS transistors instead of bipolar ones. Experimental results using discrete transistors confirming the correct operation of the cell are provided.     

Low frequency noise in complementary npn and pnp polysilicon emitter bipolar junction transistors

Low frequency noise characteristics of high voltage, high performance complementary polysilicon emitter bipolar transistors are described. The influence of the base biasing resistance, emitter geometry and temperature on the noise spectra are discussed. The npn transistors studied exhibited 1/f and shot noise, but the pnp transistors are characterized by significant generation–recombination noise contributions to the total noise. For both types of transistors, the measured output noise is determined primarily by the noise sources in the polysilicon–monosilicon interface. The level of the 1/f noise is proportional to the square of the base current for both npn and pnp transistors. The contribution of the 1/f noise in the collector current is also estimated. The area dependence of 1/f noise in both types of transistors as well as other npn bipolar transistors are presented.     

Bipolar junction transistors fabricated in silicon-on-sapphire

The effects of processing temperature on collector leakage current in bipolar junction transistors (BJTs) fabricated in silicon-on-sapphire (SOS) were examined. At low process temperatures (850 degrees C) a reduction of five orders of magnitude in the collector leakage current was observed. Excellent I-V characteristics were obtained on both NPN and PNP transistors fabricated at lower temperatures. Measured DC current gain beta for the NPN devices was 30, and that of the PNP devices was 40. Additionally, current mode logic (CML) circuits fabricated using these transistors exhibited well behaved DC switching characteristics.<>     

Direct Monitoring of RF Overstress in High-Power Transistors and Amplifiers

Light emission from power transistors at a compression level in the range of 2–3 dB has been imaged using a microscope-mounted camera. Results show that the emitted light intensity distribution across the transistor is highly nonuniform and depends on the load impedance, direct current, and RF conditions. The light intensity correlates with a negative gate current, which is a result of the RF-induced impact ionization in the transistors. The nonuniformity in the light intensity is attributed to the RF-induced voltage overstress in the transistors. The observed light emission may be used as a direct and contactless monitor of the RF-induced overstress in transistors and power amplifiers.      

Effect of rapid epitaxy in in situ phosphorus-doped polysiliconemitter on current-gain of bipolar transistors

The effect of rapid solid-phase epitaxy (SPE) on the current gain of in situ phosphorus-doped polysilicon-emitter (IDP) transistors has been evaluated, IDP technology is used to produce very-high-speed small-emitter bipolar transistors, which have very high current gain due to their hetero-emitter-like characteristics. The IDP film is deposited on a clean poly/mono-silicon surface, followed by rapid thermal annealing (RTA). The poly/mono interface was analyzed and the lattice image was observed by high-resolution transmission electron microscopy (TEM). The majority of the IDP transistors had poly/mono-silicon interfacial hetero-emitter-like characteristics and thus had high current gain. The remaining transistors, however, did not exhibit hetero-emitter-like characteristics due to SPE and thus the current gain was reduced. These results are well explained using an interfacial residual-stress model: rapid epitaxy occurs when the amorphous silicon film is annealed by RTA, which eliminates the interfacial residual stress and in turn the hetero-emitter-like characteristics     

多晶硅有晶体管直流特性研究

研究了砷注入多晶硅发射极晶体管的直流特性,并与采用常规平面工艺制作的晶体管性能的进行比较。结果表明多晶硅发射极晶体管具有较高的发射效率,高的电流能力,改善了ＥＢ击穿和ＣＢ击穿,电流增益依赖于淀积多晶硅前的表面处理条件。     

半导体功率器件结温的实时测量和在线测量

克服了器件在大电流测试时温度系数测不准的难题,帮助国际标准完善了实时测量和在线测量结温的方法,即在加热的同时,不改变加热状况的情况下,直接把加热电流当作测量电流,借助于校准曲线从而测量出晶体管的结温.     

High-gain SOI polysilicon emitter transistors

The authors report the first high-gain polysilicon emitter bipolar transistors fabricated on zone-melting-recrystallized (ZMR) silicon-on-insulator (SOI) material. Current gains as high as 230 were obtained. Polysilicon emitter bipolar transistors made on bulk silicon wafers with identical and simultaneous heat treatments show significant differences in emitter resistance and DC characteristics as compared with SOI bipolar transistors. Post-metal anneal improves the current gain and base current ideality at low base-emitter voltages for both types of wafers     

发射极镇流电阻对In_(0.49)Ga_(0 .51)P/GaAs HBT特性的影响

在发射极加一个镇流电阻可以解决在多个HBT并联时,常常出现电流坍塌的问题.研究了发射极镇流电阻对In0.49Ga0.51P/GaAs HBT直流及高频特性的影响,并对实验现象进行了理论分析.     

Design tradeoffs for improved V/sub CE(sat/) versus ICof bipolar transistors under forced gain conditions

Based on the quasi-saturation analysis of bipolar transistors and using numerical simulation, it is shown in this paper that the quasi-saturation performance of transistors under forced gain conditions can be improved by increasing the base-Gummel number if the emitter diffusion is also simultaneously altered to keep the active region current gain h_FEO constant. It is further shown that for a given h_FEO, if the ratio of h_FEO to the forced current gain β_f is below 10, the quasi-saturation performance of the transistors will be poor compared to those with h_FEO/β_f⩾10. Design curves obtained using numerical simulation are also presented to choose the quasi-saturation current limit of the transistors as a function of breakdown voltage and for different reach-through collector structures     

Increased drain saturation current in ultra-thinsilicon-on-insulator (SOI) MOS transistors

Based on substrate-charge considerations, an increased drain saturation current for MOS transistors in ultrathin silicon-on-insulator (SOI) films is predicted, compared to similar transistors in bulk or thick SOI films. For typical parameters of 200-A gate oxide with a channel doping of 4×10¹⁶ cm^-3, the drain saturation current in ultrathin SOI transistors is predicted to be ~40% larger than that of bulk structures. An increase of ~30% is seen in measurements made on devices in 1000-A SOI films     

DC analysis of multiple collector and multiple emitter transistors in integrated structures

A generalized set of equations has been developed for the multiple collector and multiple emitter transistors. These equations are applicable to the lateral transistors, SCR's, and the T/SUP 2/L coupling transistors. The analysis shows how a nonuniform base layer (double-epitaxial structure) can increase the alpha of the lateral transistor and decrease the current drain to the substrate and decrease the current drain to the substrate. The analysis also shows that in a T/SUP 2/L gate the inverse alpha is nearly equal to the cross-coupling current ratio, and can be reduced by increasing the number of inputs.     

Robustness of SiC JFET in Short-Circuit Modes

This letter presents first destructive results showing the robustness of SiC JFET transistors from SiCED in current limitation regime or short-circuit operation. Crystal temperature during failure was estimated after different electrical characterizations and using appropriate models of saturation current. This letter shows the exceptional robustness of SiC JFET transistors in current limitation mode compared to Si devices (MOSFETS and IGBTs).