基于单片机的大容量静态存储器接口设计

为解决采集系统中大量数据存储及数据传输问题,对数据采集系统中基于单片机大容量静态存储器的应用进行了刨析。闪速存储器采用Atmel公司的AT29C040,对系统的总体设计思想及闪速存储器的特点做了阐述。给出了基于8位单片机进行4Mb高速存储器扩展的具体接口电路及其驱动程序。该系统具有在掉电情况下保存数据的功能,且具有存储数据容量大,体积小,功耗低,数据保存安全可靠等特点,适合于便携式流动性环境下的数据采集系统。     

浅析闪速存储器接口的类型与应用

本文主要对闪速存储器(闪存)的接口类型和应用进行浅析。通过对闪速存储器的NOR型和NAND型所涉及到的各种接口分类、接口应用的时序和传输方式的比较,进一步的阐明了闪速存储器接口的特性和应用的趋势。     

闪速存储器 市场竞风流

闪速存储器自问世以来即成为众所关注的焦点.乐观者预言,它将成为从磁盘驱动器到EPROM(可擦可编程只读存储器)所有存储器的替代品;怀疑论者则告诫说,闪速技术将如昙花一现,与磁泡存储器同样薄命.从目前来看,两种观点都未成真,除了适当的应用领域之外,闪速存储器由于价格太高,尚未能把磁盘驱动器和EPROM拉下马,取而代之.另一方面,闪速存储器的要求爆发增长,以及厂商的大     

闪速存储器AT29C×××及其在高速处理系统中的应用

文章以ＡＴ２９Ｃ２５６为例，详细介绍了Ａｔｍｅｌ公司闪速存储器的结构、特点、性能及使用方法。针对闪速存储器的特性，结合作者的使用经验，给出了两种ＣＰＵ接口方法，并对闪速存储器的可靠编程和延长使用寿命等问题提出了相应的解决方法。     

闪速存储器AT29C×××及其在高速处理系统中的应用

文章以ＡＴ２９Ｃ２５６为例，详细介绍了Ａｔｍｅｌ公司闪速存储器的结构、特点、性能及使用方法。针对闪速存储器的特性，结合作者的使用经验，给出了两种ＣＰＵ接口方法，并对闪速存储器的可靠编程和延长使用寿命等问题提出了相应的解决方法。     

闪速存储器在2000年将摧毁EPROM市场

几年来,分析家一直在预测E-PROM行将消亡.自从闪速存储器几年前成为一种前途广阔的非易失存储器选用产品以来,EPROM一直在受到挑战.在蜂窝电话、调制解调器、BIOS存储器和其他无数嵌入式系统等大批量应用装置需求的不断推动下,EPROM还是顽强地生存下来.但是,在1995年,闪速存储器的发展势如破竹,因而已使EPROM发展停滞不前.当前的预测表明,闪速存储器的使用量已大于EPROM.现在看来,到2000年,EPROM将逐渐消声匿迹,这已成定局.甚至一些特定的专业应用领域也将从EPROM转向闪速存储器和EEPROM等替代器件.     

提高闪速存储器写入速度的方法

写入速度慢是闪速存储器应用中的一个主要问题 ,文章在阐述其写操作的工作原理的基础上 ,提出了提高闪速存储器写入速度的几种可行的解决方案 ,并从理论上估算了采用这些方案后的写入速度的提高情况。     

市场纵横

市场纵横世界闪速存储器冲上前沿随着闪速存储器向着便携电话和个人手持系统等通信、声频信号解码器等消费类电子产品以及工业、交通等部门应用的扩大，需求急速增长。据Ｓｈａｒｐ、Ｉｎｔｅｌ等公司的预测，世界闪速存储器市场规模将从１９９５年的１９亿美元增长到１９...     

单片机硬件、软件及其应用讲座(4)——第三讲 PIC16F873硬件系统(下)

<正> 程序存储器和堆栈 PIC16F873具有一个13位宽的程序计数器PC,它所产生的13位地址最大可寻址的存储器空间为8K×14,地址编码的最大范围为0000H～1FFFH。但是,PIC16F873只配置了4K× 14的闪速程序存储器 (它不仅可以在电路 板上直接进行电写入     

非易失性存储器在二十一世纪的问题,挑战和发展趋向

引言 本世纪末,存储器市场的预计表明,存储器将占集成电路总数的二分之一。 当然,这个市场的主要部分是被DRAM所占有,但与此同时,非易失性存储器(NVM)显得越来越重要,这样,它们将占总市场的11％。在非易失性存储器市场中,闪速存储器预计占60％以上的份额。事实上,闪速存储器对整个非易失性存储器市场来讲将     

A 1-Mb 2-Tr/b nonvolatile CAM based on flash memory technologies

This paper describes the circuit technologies and the experimental results for a 1 Mb flash CAM, a content addressable memory LSI based on flash memory technologies. Each memory cell in the flash CAM consists of a pair of flash memory cell transistors. Additionally, four new circuit technologies have been developed: a small-size search sense amplifier; a highly parallel search management circuit; a high-speed priority encoder; and word line/bit line redundancy circuits for higher production yields. A cell size of 10.34 μm² and a die size of 42.9 mm² have been achieved with 0.8 μm design rules. Read access time and search access time are 115 ns and 135 ns, respectively, with a 5 V supply voltage. Power dissipation in 3.3 MHz operations is 210 mW in read and 140 mW in search access     

Design of a sense circuit for low-voltage flash memories

A new sense circuit directly sensing the bitline voltage is proposed for low-voltage flash memories. A simple reference voltage generation method and a dataline switching method with matching of the stray capacitance between the dataline pairs are also proposed. A design method for the bitline clamp load transistors is described, taking bitline charging speed and process margins into account. The sense circuit was implemented in a 32-Mb flash memory fabricated with a 0.25-μm flash memory process and successfully operated at a low voltage of 1.5 V     

TMS320VC5509应用flash存储数据的接口电路设计与编程

简要介绍了DSP芯片TMS320VC5509的主要特点,指出了TMS320VC5509在使用flash存储器AM29LV800存储数据的应用中,在电路接口设计、数据空间寻址、寄存器初始化设置及DSP对flash的写或擦除操作的检测等方面应该注意的一些问题.提出了DSP工作在较高的时钟频率时通过适当延时来正确访问AM29LV800的解决方案,并给出了主要的编程范例.在实践中证明了方案的有效性.     

Novel Co-Design of NAND Flash Memory and NAND Flash Controller Circuits for Sub-30 nm Low-Power High-Speed Solid-State Drives (SSD)

As the cell size of the NAND flash memory has been scaled down by 40%–50% per year and the memory capacity has been doubling every year, a solid-state drive (SSD) that uses NAND as mass storage for personal computers and enterprise servers is attracting much attention. To realize a low-power high-speed SSD, the co-design of NAND flash memory and NAND controller circuits is essential. In this paper, three new circuit technologies, the selective bit-line precharge scheme, the advanced source-line program, and the intelligent interleaving, are proposed. In the selective bit-line precharge scheme, an unnecessary bit-line precharge is removed during the verify-read and consequently the current consumption decreases by 23%. In the advanced source-line program scheme, a hierarchical source-line structure is adopted. The load capacitance during the program pulse is reduced by 90% without a die size overhead. As a result, the current consumption is reduced by 48%. Finally, with the intelligent interleaving, a current peak is suppressed and a high-speed parallel write operation of the NAND flash memories is achieved. By using these three technologies, both the NAND flash memory and the NAND controller circuits are best optimized. At the sub-30 nm generation, the current consumption of the NAND flash memory decreases by 60% and the SSD speed improves by 150% without a cost penalty or circuit noise.      

A PWM analog memory programming circuit for floating-gate MOSFETswith 75-μs programming time and 11-bit updating resolution

This paper describes a programming circuit for analog memory using pulsewidth modulation (PWM) signals and the circuit performance obtained from measurements using a floating-gate EEPROM device. This programming circuit attains both high programming speed and high precision. We fabricated the programming circuit using standard 0.6-μm CMOS technology and constructed an analog memory using the programming circuit and a floating-gate MOSFET. The measurement results indicate that the analog memory attains a programming time of 75 μs, an updating resolution of 11 bit, and a memory setting precision of 6.5 bit. This programming circuit can be used for intelligent information processing hardware such as self-learning VLSI neural networks as well as multilevel flash memory     

高速大容量固态存储系统的设计

大容量存储系统是高速数据采集和其他应用中非常重要的一个组成部分,主要包括存储器控制和数据存储。本文通过使用FPGA(现场可编程门阵列)成功地实现了数据采集过程中相对低速的Flash存储器对高速和超高速实时数据的存储。FPGA既可作为高速输入数据传输到Flash中间的缓存,又可实现对存储器的读写、擦除等操作时序的控制。该设计已在应用电路中得到了验证。文章最后给出了所测电路板在逻辑分析仪上观察的数据和仿真的部分结果。     

Flash memory cells-an overview

The aim of this paper is to give a thorough overview of flash memory cells. Basic operations and charge-injection mechanisms that are most commonly used in actual flash memory cells are reviewed to provide an understanding of the underlying physics and principles in order to appreciate the large number of device structures, processing technologies, and circuit designs presented in the literature. New cell structures and architectural solutions have been surveyed to highlight the evolution of the flash memory technology, oriented to both reducing cell size and upgrading product functions. The subject is of extreme interest: new concepts involving new materials, structures, principles, or applications are being continuously introduced. The worldwide semiconductor memory market seems ready to accept many new applications in fields that are not specific to traditional nonvolatile memories     

A dual-page programming scheme for high-speed multigigabit-scaleNAND flash memories

To realize a low-cost and high-speed programming NAND flash memory, a new programming scheme, a “dual-page programming scheme,” has been proposed. This architecture drastically increases the program throughput without circuit area overhead. In the proposed scheme, two memory cells are programmed at the same time using only one page buffer. Therefore, the page size, i.e., the number of memory cells programmed simultaneously, is doubled and the program speed is improved. As the number of page buffers required in the proposed scheme is the same as that in the conventional one, there is no circuit area increase. This novel operation is made possible by using a bitline as a dynamic latch to temporarily store the program data. As a result, the programming is accelerated by 73% in a 1-Gb generation and 62% in a 4-Gb generation, 18.2-MB/s 1-Gb or 30.7-MB/s 4-Gb NAND flash memory can be realized with this new architecture     

Quick address detection of anomalous memory cells in a flash memorytest structure

A novel scheme for quick address detection of anomalous memory cells having the highest and lowest threshold voltages in a flash memory test structure is described. A test structure with a large memory cell array has been developed to evaluate reliability of flash memory cells before fabrication of a new generation of flash memory devices. In this test structure, each terminal branch of a tree-structured column selector is connected to each bitline of the array. And a simple threshold voltage distribution monitor circuit (VTDM) which we have already proposed is connected to the other end of the bitlines. A proposed Multi-Address Scanning Scheme (MASS) is performed by the tree-structured column selector with monitoring the output of VTDM. The detection time has been reduced to 1.12% in the case of 2048 columns. This novel scheme is suitable for performing reliability tests, such as program/erase endurance test and data retention test     

A quick intelligent page-programming architecture and a shieldedbitline sensing method for 3 V-only NAND flash memory

This paper describes a quick intelligent page-programming architecture with a newly introduced intelligent verify circuit for 3 V-only NAND flash memories. The new verify circuit, which is composed of only two transistors, results in a simple intelligent program algorithm for 3 V-only operation and a reduction of the program time to 56%. This paper also describes a shielded bitline sensing method to reduce a bitline-bitline capacitive coupling noise from 700 mV to 35 mV. The large 700 mV noise without the shielded bitline architecture is mainly caused by the NAND-type cell array structure. A 3 V-only experimental NAND flash memory, developed in a 0.7-μm NAND flash memory process technology, demonstrates that the programmed threshold voltages are controlled between 0.4 V and 1.8 V by the new verify circuit. The shielded bitline sensing method realizes a 2.5-μs random access time with a 2.7-V power supply. The page-programming is completed after the 40-μs program and 2.8-μs verify read cycle is iterated 4 times. The block-erasing time is 10 ms