TiN/TaN 厚度变化对nMOSCAP栅叠层有效功函数的影响

We evaluated the TiN/TaN/TiA1 triple-layer to modulate the effective work function （EWF） of a metal gate stack for the n-type metal-oxide-semiconductor （NMOS） devices application by varying the TiN/TaN thickness. In this paper, the effective work function of EWF ranges from 4.22 to 4.56 eV with different thicknesses of TiN and TaN. The thinner TiN and/or thinner in situ TaN capping, the closer to conduction band of silicon the EWF is, which is appropriate for 2-D planar NMOS. Mid-gap work function behavior is observed with thicker TiN, thicker in situ TaN capping, indicating a strong potential candidate of metal gate material for replacement gate processed three-dimensional devices such as FIN shaped field effect transistors. The physical understandings of the sensitivity of EWF to TiN and TaN thickness are proposed. The thicker TiN prevents the A1 diffusion then induces the EWF to shift to mid-gap. However, the TaN plays a different role in effective work function tuning from TiN, due to the Ta-O dipoles formed at the interface between the metal gate and the high-k layer.     

通过多次淀积多次退火与Ti吸氧技术相结合来改善后栅工艺中高k金属栅的性能

本文的原子层淀积（ALD） HfO2薄膜采用新颖的多次淀积多次退火（MDMA）技术进行制备,并在有Ti吸氧层和没有Ti吸氧层两种情况下分别进行性能研究。 与传统的一次淀积一次退火相比,采用多次淀积多次退火后的器件漏电明显减小,同时,等效氧化层厚度（EOT）也被Ti吸氧层有效控制。器件性能的提升与淀积和退火次数密切相关（在保持总介质层厚度相同的情况下）。透射电子显微镜（TEM）和能量色散X射线光谱（EDX）分析表明,氧同时注入高k（HK）薄膜和中间层（IL）很可能是导致器件性能提升的主要原因。因此在后栅工艺中MDMA技术是一种改善栅极特性的有效方法。     

超薄EOT高K金属栅结构中串联电阻效应对瞬时击穿特性的影响

本文研究了超薄EOT高K金属栅MOS电容结构的瞬时击穿特性。由于串联电阻效应的影响,MOS电容的瞬时击穿特性的面积依赖关系与理论推导不符。器件中的串联电阻可以通过对IV特性的FN拟合得到。在本文的器件结构中,经验证得到串联电阻主要是由于电极的不对称性引起的扩展电阻。本文提出一种采用串联模型对击穿分布特性进行修正的方法。修正后的瞬时击穿特性与面积的依赖关系符合泊松面积归一规律,这说明对于超薄EOT的高K金属栅结构,瞬时击穿的机制与时变击穿的机制相同,都是由缺陷产生过程导致的击穿过程。     

Thickness optimization of the TiN metal gate with polysilicon-capping layer on Hf-based high-k dielectric

An optimal thickness of the metal nitride (TiN) film capped by polysilicon for the MOSFET gate electrode application is investigated. Interface trap density, which depends on the TiN film thickness and transistor channel length is suggested to be controlled by mechanical stress of the metal layer after full transistor processing including high temperature annealing. Thinner TiN gate electrode was found to have lower interface trap density. Thicker TiN, however, showed better barrier properties for impurity diffusion from the polysilicon-capping layer. We found that 10 nm is the optimum thickness of the ALD TiN layer for minimizing charge trapping and adequate blocking of boron penetration.     

化学浴法生成金属/锗间含碳层对费米能级钉扎的释放

使用化学浴的方法在金属/锗结构中插入一层含碳层,可以使得肖特基势垒高度得到调整。使用十二稀、十四稀、十六烯和十八烯在锗衬底上进行化学浴可以生成超薄含碳层,该含碳层可以阻挡金属中的自由电子波函数穿透至锗中。金属致带隙状态得到抑制,费米能级钉扎得以释放,所形成结构的肖特基势垒高度为0.17eV。这一新方法较传统方法极大低降低了工艺复杂度,并且得到了很好的结果。     

BE-SONOS flash memory along with metal gate and high-k dielectrics in tunnel barrier and its impact on charge retention dynamics

We investigate the effect of a high-k dielectric in the tunnel layer to improve the erase speed-retention trade-off. Here, the proposed stack in the tunnel layer is AlLaO₃/HfAlO/SiO₂. These proposed materials possess low valence band offset with high permittivity to improve both the erase speed and retention time in barrier engineered silicon-oxide-nitride-oxide-silicon(BE-SONOS). In the proposed structure HfAlO and AlLaO₃ replace Si₃N₄ and the top SiO₂ layer in a conventional oxide/nitride/oxide(ONO) tunnel stack. Due to the lower conduction band offset(CBO) and high permittivity of the proposed material in the tunnel layer, it offers better program/erase(P/E) speed and retention time. In this work the gate length is also scaled down from 220 to 55 nm to observe the effect of high-k materials while scaling, for the same equivalent oxide thickness(EOT). We found that the scaling down of the gate length has a negligible impact on the memory window of the devices. Hence, various investigated tunnel oxide stacks possess a good memory window with a charge retained up to 87.4%(at room temperature) after a period of ten years. We also examine the use of a metal gate instead of a polysilicon gate, which shows improved P/E speed and retention time.     

Electrical characterization of high-k gate dielectrics fabricated using plasma oxidation and post-deposition annealing of a Hf/SiO2/Si structure

High permittivity (high-k) gate dielectrics were fabricated using the plasma oxidation of Hf metal/SiO₂/Si followed by the post-deposition annealing (PDA), which induced a solid-phase reaction between HfO_x and SiO₂. The oxidation time and PDA temperature affected the equivalent oxide thickness (EOT) and the leakage current density of the high-k dielectric films. The interfacial structure of the high-k dielectric film/Si was transformed from HfO_x/SiO₂/Si to HfSi_xO_y/Si after the PDA, which led to a reduction in EOT to 1.15 nm due to a decrease in the thickness of SiO₂. These high-k dielectric film structures were investigated by X-ray photoelectron spectroscopy. The leakage current density of high-k dielectric film was approximately four orders of magnitude lower than that of SiO₂.     

Deposition characteristics of Ti−Si−N films reactively sputtered from various targets in a N2/Ar gas mixture

The deposition characteristics of Ti−Si−N films obtained by using RF reactive sputtering of various targets in N₂/Ar gas mixtures have been investigated. The dependence of film growth rate and stoichiometry on both the Ti/Si ratio of the target and the N₂ flow rate were found to be due to the different intridation rates of Ti and Si, resulting in, different sputter yields of titanium and silicon nitrides. XPS results showed that an increase in nitrogen content of the Ti−Si−N films leads to the formation of amorphous Si₃N₄ bonding, which produces an in crease in resistivity. Lowering the Si content in the deposited Ti−Si−N films favors the formation of crystalline TiN, even at low N₂ flow rates, and leads to a lower resistivity. A film growth mechanism, expressed in terms of the nitrogen surface coverage on the target, was proposed.