Organic thin film transistors with a SiO2/SiNx/SiO2 composite insulator layer

We have investigated a SiO₂/SiN_x/SiO₂ composite insulation layer structured gate dielectric for an organic thin film transistor（OTFT） with the purpose of improving the performance of the SiO₂ gate insulator. The SiO₂/SiN_x/SiO₂ composite insulation layer was prepared by magnetron sputtering.Compared with the same thickness of a SiO₂ insulation layer device,the SiO₂/SiN_x/SiO₂ composite insulation layer is an effective method of fabricating OTFT with improved electric characteristics and decreased leakage current.Electrical parameters such as carrier mobility by field effect measurement have been calculated.The performances of different insulating layer devices have been studied,and the results demonstrate that when the insulation layer thickness increases,the off-state current decreases.     

Dry etching of poly-Si/TaN/HfSiON gate stack for advanced complementary metal-oxide-semiconductor devices

A novel dry etching process of a poly-Si/TaN/HfSiON gate stack for advanced complementary metal-oxide-semiconductor（CMOS） devices is investigated.Our strategy to process a poly-Si/TaN/HfSiON gate stack is that each layer of gate stack is selectively etched with a vertical profile.First,a three-step plasma etching process is developed to get a vertical poly-Si profile and a reliable etch-stop on a TaN metal gate.Then different BCl₃-based plasmas are applied to etch the TaN metal gate and find that BCl₃/Cl₂/O₂/Ar plasma is a suitable choice to get a vertical TaN profile.Moreover,considering that Cl₂ almost has no selectivity to Si substrate, BCl₃/Ar plasma is applied to etch HfSiON dielectric to improve the selectivity to Si substrate after the TaN metal gate is vertically etched off by the optimized BCl₃/Cl₂/O₂/Ar plasma.Finally,we have succeeded in etching a poly-Si/TaN/HfSiON stack with a vertical profile and almost no Si loss utilizing these new etching technologies.     

Material properties and effective work function of reactive sputtered TaN gate electrodes

The resistivity,crystalline structure and effective work function（EWF） of reactive sputtered TaN has been investigated.As-deposited TaN films have an fcc structure.After post-metal annealing（PMA） at 900℃,the TaN films deposited with a N₂ flow rate greater than 6.5 sccm keep their fee structure,while the films deposited with a N₂ flow rate lower than 6.25 seem exhibit a microstructure change.The flatband voltages of gate stacks with TaN films as gate electrodes on SiO₂ and HfO₂ are also measured.It is concluded that a dipole is formed at the dielectric-TaN interface and its contribution to the EWF of TaN changes with the Ta/N ratio in TaN,the underneath dielectric layer and the PMA conditions.     

介质前后双重臭氧处理实现锗/氧化铪间界面钝化

The physical and electrical properties of a Ge/GeO₂/HfO₂/Al gate stack are investigated.A thin interfacial GeO₂ layer（ 1 nm） is formed between Ge and HfO₂ by dual ozone treatments,which passivates the Ge/high-k interface.Capacitors on p-type Ge substrates show very promising capacitance-voltage（C-V） characteristics by using in situ pre-gate ozone passivation and ozone ambient annealing after high-k deposition,indicating efficient passivation of the Ge/HfO₂ interface.It is shown that the mid-gap interface state density at the Ge/GeO₂ interface is 6.4×10¹¹ cm^-2·eV^-1.In addition,the gate leakage current density of the Ge/GeO₂/HfO₂/Al gate stack passivated by the dual ozone treatments is reduced by about three orders of magnitude compared to that of a Ge/HfO₂/Al gate stack without interface passivation.     

Influence of growth conditions of oxide on electrical properties of AlGaN/GaN metal–insulator–semiconductor transistors

AlGaN/GaN metal–insulator–semiconductor high-electron-mobility transistors(MIS-HEMTs) on a silicon substrate were fabricated with silicon oxide as a gate dielectric by sputtering deposition and electron-beam(EB) evaporation. It was found that the oxide deposition method and conditions have great influences on the electrical properties of HEMTs. The low sputtering temperature or oxygen introduction at higher temperature results in a positive equivalent charge density at the oxide/AlGaN interface(Nequ), which induces a negative shift of threshold voltage and an increase in both sheet electron density(ns) and drain current density(ID). Contrarily, EB deposition makes a negative Nequ, resulting in reduced ns and ID. Besides, the maximum transconductance(gm-max) decreases and the off-state gate current density(I_G-off) increases for oxides at lower sputtering temperature compared with that at higher temperature, possibly due to a more serious sputter-induced damage and much larger Nequ at lower sputtering temperature. At high sputtering temperature, I_G-off decreases by two orders of magnitude compared to that without oxygen, which indicates that oxygen introduction and partial pressure depression of argon decreases the sputter-induced damage significantly. I_G-off for EB-evaporated samples is lower by orders of magnitude than that of sputtered ones, possibly attributed to the lower damage of EB evaporation to the barrier layer surface.     

Source-field-plated Ga2O3 MOSFET with a breakdown voltage of 550 V

Ga_2O_3 metal–oxide–semiconductor field-effect transistors(MOSFETs) with high-breakdown characteristics were fabricated on a homoepitaxial n-typed β-Ga_2O_3 film, which was grown by metal organic chemical vapor deposition(MOCVD) on an Fedoped semi-insulating(010) Ga_2O_3 substrate. The structure consisted of a 400 nm unintentionally doped(UID) Ga_2O_3 buffer layer and an 80 nm Si-doped channel layer. A high k HfO_2 gate dielectric film formed by atomic layer deposition was employed to reduce the gate leakage. Moreover, a source-connected field plate was introduced to enhance the breakdown characteristics. The drain saturation current density of the fabricated device reached 101 mA/mm at V_gs of 3 V. The off-state current was as low as 7.1 ×10^-11 A/mm, and the drain current I_ON/I_OFF ratio reached 10~9. The transistors exhibited three-terminal off-state breakdown voltages of 450 and 550 V, corresponding to gate-to-drain spacing of 4 and 8 μm, respectively.     

Gate current modeling and optimal design of nanoscale non-overlapped gate to source/drain MOSFET

A novel nanoscale MOSFET with a source/drain-to-gate non-overlapped and high-k spacer structure has been demonstrated to reduce the gate leakage current for the first time.The gate leakage behaviour of the novel MOSFET structure has been investigated with the help of a compact analytical model and Sentaurus simulation. A fringing gate electric field through the dielectric spacer induces an inversion layer in the non-overlap region to act as an extended S/D(source/drain) region.It is found that an optimal source/drain-to-gate non-overlapped and high-A:spacer structure has reduced the gate leakage current to a great extent as compared to those of an overlapped structure.Further,the proposed structure had improved off current,subthreshold slope and drain induced barrier lowering(DIBL) characteristics.It is concluded that this structure solves the problem of high leakage current without introducing extra series resistance.     

基于氟等离子体表面处理技术的AlGaN/GaN HEMT器件栅正向泄漏电流研究

The gate forward leakage current in AlGaN/GaN high electron mobility transistors(HEMTs) is investigated. It is shown that the current which originated from the forward biased Schottky-gate contributed to the gate forward leakage current.Therefore,a fluorine-plasma surface treatment is presented to induce the negative ions into the AlGaN layer which results in a higher metal-semiconductor barrier.Consequently,the gate forward leakage current shrinks.Experimental results confirm that the gate forward leakage current is decreased by one order magnitude lower than that of HEMT device without plasma treatment.In addition,the DC characteristics of the HEMT device with plasma treatment have been studied.     

并五苯钝化层增强C60有机场效应晶体管性能的研究

We investigated the properties of C₆₀-based organic field-enect transistors（OFETs）（?） a pentacene passivation layer inserted between the C₆₀ active layer and the gate dielectric.After modification of the pentacene passivation layer,the performance of the devices was considerably improved compared to C₆₀-based OFETs with only a PMMA dielectric.The peak field-effect mobility was up to 1.01 cm²/（V·s） and the on/off ratio shifted to 10⁴.This result indicates that using a pentacene passivation layer is an effective way to improve the performance of N-type OFETs.     

Cylindrical gate all around Schottky barrier MOSFET with insulated shallow extensions at source/drain for removal of ambipolarity: a novel approach

In this paper TCAD-based simulation of a novel insulated shallow extension (ISE) cylindrical gate all around (CGAA) Schottky barrier (SB) MOSFET has been reported,to eliminate the suicidal ambipolar behavior (bias-dependent OFF state leakage current) of conventional SB-CGAA MOSFET by blocking the metal-induced gap states as well as unwanted charge sharing between source/channel and drain/channel regions.This novel structure offers low barrier height at the source and offers high ON-state current.The ION/IoFF of ISE-CGAA-SB-MOS-FET increases by 1177 times and offers steeper subthreshold slope (～60 mV/decade).However a little reduction in peak cut off frequency is observed and to further improve the cut-off frequency dual metal gate architecture has been employed and a comparative assessment of single metal gate,dual metal gate,single metal gate with ISE,and dual metal gate with ISE has been presented.The improved performance of Schottky barrier CGAA MOSFET by the incorporation of ISE makes it an attractive candidate for CMOS digital circuit design.The numerical simulation is performed using the ATLAS-3D device simulator.     

Integration of HfxTayN metal gate with SiO2 and HfOxNy gate dielectrics for MOS device applications

Interaction of Hf_xTa_yN metal gate with SiO₂ and HfO_xN_y gate dielectrics has been extensively studied. Metal-oxide-semiconductor (MOS) device formed with SiO₂ gate dielectric and Hf_xTa_yN metal gate shows satisfactory thermal stability. Time-of-flight secondary ion mass spectroscopy (TOF-SIMS) analysis results show that the diffusion depths of Hf and Ta are less significant in SiO₂ gate dielectric than that in HfO_xN_y. Compared to HfO_xN_y gate dielectric, SiO₂ shows better electrical properties, such as leakage current, hysteresis, interface trap density and stress-induced flat-band voltage shift. With an increase in post metallization annealing (PMA) temperature, the electrical characteristics of the MOS device with SiO₂ gate dielectric remain almost unchanged, indicating its superior thermal and electrical stability.     

Electrical characterization of high-k gate dielectrics fabricated using plasma oxidation and post-deposition annealing of a Hf/SiO2/Si structure

High permittivity (high-k) gate dielectrics were fabricated using the plasma oxidation of Hf metal/SiO₂/Si followed by the post-deposition annealing (PDA), which induced a solid-phase reaction between HfO_x and SiO₂. The oxidation time and PDA temperature affected the equivalent oxide thickness (EOT) and the leakage current density of the high-k dielectric films. The interfacial structure of the high-k dielectric film/Si was transformed from HfO_x/SiO₂/Si to HfSi_xO_y/Si after the PDA, which led to a reduction in EOT to 1.15 nm due to a decrease in the thickness of SiO₂. These high-k dielectric film structures were investigated by X-ray photoelectron spectroscopy. The leakage current density of high-k dielectric film was approximately four orders of magnitude lower than that of SiO₂.     

The effect of oxygen in Ru gate electrode on effective work function of Ru/HfO2 stack structure

Effective work function (φ_m,eff) values of Ru gate electrode on SiO₂ and HfO₂ MOS capacitors were carefully examined and discussed from the viewpoint of an effect of oxygen incorporation in Ru gate electrode on φ_m,eff. Annealing at 400 °C in the reduction (3%H₂) and the oxidation (1%O₂) ambient resulted in similar changes in the φ_m,eff of Ru/HfO₂/SiO₂ and Ru/SiO₂ MOS capacitors. Furthermore, the Ru gate MOS capacitor after annealing in the oxidation condition have shown almost the same φ_m,eff value to that of RuO₂ gate MOS capacitors. The oxygen concentration in the Ru/HfO₂ interface after annealing in oxidizing atmosphere is approximately one order of magnitude higher than that after annealing in reducing atmosphere as confirmed by secondary ion mass spectroscopy analysis. Furthermore, the higher oxygen concentration at the Ru/dielectric interface leads to the higher φ_m,eff value, regardless of SiO₂ or HfO₂ dielectrics. This indicates that φ_m,eff of Ru gate MOS capacitor is dominantly determined by the oxygen concentration at the Ru/dielectric layer interface rather than the dipoles originated from the oxygen vacancy in HfO₂.     

Gate leakage properties of MOS devices with tri-layer high-k gate dielectric

Gate leakage of deep-submicron MOSFET with stack high-k dielectrics as gate insulator is studied by building a model of tunneling current. Validity of the model is checked when it is used for MOSFET with SiO₂ and high-k dielectric material as gate dielectrics, respectively, and simulated results exhibit good agreement with experimental data. The model is successfully used for a tri-layer gate-dielectric structure of HfON/HfO₂/HfSiON with a U-shape nitrogen profile and a like-Si/SiO₂ interface, which is proposed to solve the problems of boron diffusion into channel region and high interface-state density between Si and high-k dielectric. By using the model, the optimum structural parameters of the tri-layer dielectric can be determined. For example, for an equivalent oxide thickness of 2.0 nm, the tri-layer gate-dielectric MOS capacitor with 0.3-nm HfON, 0.5-nm HfO₂ and 1.2-nm HfSiON exhibits the lowest gate leakage.     

Silicon nanowire NVM cell using high-k dielectric charge storage layer

Si nanowire (SiNW) channel non-volatile memory (NVM) cells were fabricated by a “self-alignment” process. First, a layer of thermal SiO₂ was grown on a silicon wafer by dry oxidation, and the SiNWs were then grown by chemical vapor deposition in pre-defined locations. This was followed by depositing the gate dielectric, which almost surrounds the nanowire and consists of three stacked layers: SiO₂ blocking layer, HfO₂ charge-storing layer and a thin tunneling oxide layer. Source/drain and gate electrodes were formed by photolithography and lift-off, and the devices were electrically tested. As expected from this fabrication process and the enhanced electrostatic control of the “surrounding” gate, excellent cell characteristics were obtained.     

Influence of the SiO2 layer thickness on the degradation of HfO2/SiO2 stacks subjected to static and dynamic stress conditions

The substitution of the SiO₂ gate oxide in MOS devices by a material with a high-k dielectric constant is being deeply studied nowadays to solve the problem of the leakage currents that appear with the progressive scaling of SiO₂ thickness. To improve the quality of the high-k/Si interface a very thin SiO₂ film is grown between both materials. In this work, HfO₂/SiO₂ stacks with different SiO₂ thickness were subjected to different types of stress (static and dynamic) to analyze the effect of this interfacial layer of SiO₂ in the degradation of the stack. The results show that the dielectric degradation depends on the stress applied and that the thickness of the SiO₂ interfacial layer influences the advanced stages of the stack degradation.     

Improved low frequency noise characteristics of sub-micron MOSFETs with TaSiN/TiN gate on ALD HfO2 dielectric

Low frequency noise measurements were performed on n- and p-channel MOSFETs with TaSiN and TiN metal gates, respectively, deposited on ALD HfO₂ gate dielectric. Lower normalized current noise power spectral density is reported for these devices in comparison to poly-Si/HfO₂ devices and that yielded one order lower magnitude for extracted average effective dielectric trap density. In addition, the noise levels in PMOS devices were found to be higher than NMOSFETs and the dielectric trap distribution less dense in the upper mid-gap than the lower mid-gap region. The screened carrier scattering coefficient extracted from the noise measurements was approximately the same for metal and poly-Si high-k stacks but higher than that for the poly-Si SiO₂ system, implying higher Coulomb scattering effects. It is believed that the elimination of dopant penetration seen in poly-Si system and low thermal budgets for metal gate deposition helped lower the noise magnitude and yielded better mobility and effective trap density values.     

Monte carlo study of mobility in Si devices with -based oxides

HfO₂-based high-κ dielectrics are among the most likely candidates to replace SiO₂ and the currently favoured oxinitride in the next generation of MOSFETs. High-κ materials allow the use of a thicker gate dielectric, maintaining the gate capacitance with reduced gate leakage. However, they lead to a fundamental mobility degradation due to the coupling of carriers to surface soft (low-energy) optical phonons. Comparing the vertical field dependence of the mobility for HfO₂ and SiO₂, the severe degradation in mobility in the presence of high-κ becomes evident. The introduction of a SiO₂ interfacial layer between the channel and the HfO₂ mitigates this degradation, by increasing the effective distance between the carriers and the SO phonons, thus decreasing the interaction strength, this does though lead to an increase in the equivalent oxide thickness (EOT) of the gate dielectric. The material of choice for the first commercial introduction of high-κ gate stacks is Hafnium Silicate (Si_xHf_1-xO₂). This alloy stands up better to the processing challenges and as a result suffers less from dielectric fluctuations. We show that as the fraction of Hf increases within the alloy, the inversion layer mobility is shown to decrease due to the corresponding decrease in the energy of the surface optical phonons and increase in the dielectric constant of the oxide.     

Towards barrier height modulation in HfO2/TiN by oxygen scavenging - Dielectric defects or metal induced gap states?

The band alignment between a dielectric and a metal gate is crucial as it controls the MOSFET threshold voltage as well as the leakage in metal-insulator-metal (MIM) structure. In the ideal Schottky-Mott model the barrier height should be controlled only by the workfunction and the electron affinity of the materials considered. However, this seems the case only for few insulating materials other than SiO₂ (i.e., Fermi level pinning).The most popular explanation invokes metal-induced gap states (MIGS), where electron states from the bulk of a metal tails into the insulator. The MIGS hypothesis explains a rather large series of experimental results and, importantly, predicts that the MI barrier height will mostly be controlled by the energy distribution of electron states in the bulk of the contacting metal and dielectric. In this paper, we analyze the band alignment of contacting metal (TiN) and dielectric (HfO₂) by using internal photoemission. It will be shown that defects in the dielectric rather than MIGS control the barrier height.