Effects of output harmonic termination on PAE and output power of AlGaN/GaN HEMT power amplifier

The authors experimentally investigate and discuss the effects of output harmonic termination on power added efficiency (PAE) and output power of an AlGaN/GaN high electron mobility transistor (HEMT) power amplifier (PA). The AlGaN/GaN HEMT PA with gate periphery of 1 mm was built and tested at L-band. Large-signal measurements and comparisons of the PAE and output power were carried out at different DC bias conditions from 50% of saturated drain current (I/sub dss/) to 1% of Id., for the PA with and without output harmonic termination. For class-AB operation at 25% of I/sub dss/, an increase of about 10% in peak PAE and 1 dBm in output power were observed in saturated output power range. Improvements of up to 9% in PAE and 1.2 dBm in output power were achieved over the measured DC bias conditions provided the output harmonics are properly terminated.     

S波段高效F类/逆F类GaN HEMT功率放大器设计

为了解决F类和逆F类（F-1类）功率放大器设计过程中受晶体管寄生参数影响,导致功放效率低以及输出匹配电路结构复杂的问题,提出了一种新型的输出匹配电路结构.首先,在直流偏置线中加入谐波调谐功能,避免单独设计谐波控制电路;其次,为满足F类和F-1类功放在器件本征漏极端所需的阻抗状态,匹配寄生参数呈现的封装端谐波阻抗,采用一段L型传输线结构代替传统的L-C集总元件寄生补偿方法;最后,由两段串联的传输线实现最优基波阻抗与50 Ω负载间的匹配.为验证方法的有效性,采用CGH40010氮化镓高电子迁移率晶体管（Gallium nitride high electron mobility transistor,GaN HEMT）器件,设计并加工了两款工作在2.4 GHz的F类和F-1类功放.测试结果显示:F类功放的峰值功率附加效率（power added efficiency,PAE）为75.5%,饱和输出功率为40.8 dBm;F-1类功放的峰值PAE为77.6%,饱和输出功率为40.3 dBm.该方法降低了电路复杂度和设计难度,可以较容易地补偿晶体管寄生参数,功放在高频工作时的效率得到提升,为利用GaN HEMT器件设计高效功放提供了一种可行的方案.     

A novel full-wave rectifier/sinusoidal frequency doubler topology based on CFOAs

In this paper, a high-efficiency class-F power amplifier (PA) is designed using integration between a low voltage p-HEMT transistor and a miniaturized microstrip suppressing cell. It results in nth harmonic suppression and high power added efficiency (PAE) under low radio frequency (RF) input powers. The simulation is performed based on harmonic balance analysis. The proposed power amplifier is fabricated, and measurements results validated the simulations. The proposed power amplifier operates at 1.8 GHz with 100 MHz bandwidth and an average PAE of 71.1%, with very low drain voltage of 2 V. At fundamental frequency of 1.8 GHz, the maximum measured PAE is 73.5% at about 12 dBm RF input power. The maximum output power and gain are 23.4 and 17.5 dBm in RF input power ranges of 0–12 dBm, respectively. The fabricated class-F PA with such characteristics can be used for power amplifications in wireless transmitters such as 4G (4th generation)-LTE (long term evolution) communication systems.     

用于无线通信的SiGe异质结双极型晶体管AB类功率放大器

报道了一种性能良好的SiGe功率放大器,具有用于无线通信的前景.在B类模式下工作时,输出功率可以达到30dBm.在AB类模式下,电源电压为4V工作时,1dB压缩点输出功率(P1dB)为24dBm,输出功率三阶交截点(TOI)为39dBm.最大的功率附加效率(PAE)和在1dB压缩点的功率附加效率分别达到34%和25%.处理CDMA信号时的邻道功率抑制超过42dBc,符合IS95标准.     

Design of broadband class-F power amplifier for multiband LTE handsets applications

A broadband class-F power amplifier for multiband LTE handsets applications is developed across 2.3-2.7 GHz. The power amplifier maintains constant fundamental impedance at the output matching circuit which is operating for broadband. The nearly zero of second harmonic impedance and nearly infinity of third harmonic impedance are found for highly efficient class-F PA. The harmonic control circuits are immersed into the broadband output matching for fundamental frequency. For demonstration, the PA is implemented in InGaP/GaAs HBT process, and tested across the frequency range of 2.3-2.7 GHz using a long-term evolution signal. The presented PA delivers good performance of high efficiency and high linearity, which shows that the broadband class-F PA supports the multiband LTE handsets applications.     

用于无线通信的SiGe异质结双极型晶体管AB类功率放大器

报道了一种性能良好的SiGe功率放大器,具有用于无线通信的前景.在B类模式下工作时,输出功率可以达到30dBm.在AB类模式下,电源电压为4V工作时,1dB压缩点输出功率(P1dB)为24dBm,输出功率三阶交截点(TOI)为39dBm.最大的功率附加效率(PAE)和在1dB压缩点的功率附加效率分别达到34%和25%.处理CDMA信号时的邻道功率抑制超过42dBc,符合IS95标准.     

A modified class-F power amplifier with miniaturized harmonic control circuit

In this paper, a modified class-F power-amplifier (PA) for GSM applications is designed, simulated and tested. In this design, novel symmetrical meandered lines compact microstrip resonant cell (SMLCMRC), is proposed as a new harmonics control circuit (HCC), which resulted in size compression, power added efficiency (PAE) enhancement, power gain improvement, and better linearization in the PA. In this work both of the conventional class-F amplifier and proposed amplifier with SMLCMRC is designed at 1.8 GHz. The measurements show that the proposed PA with SMLCMRC has 72.54% maximum PAE, 17.13 dB gain and the 1 dB compression point (P1dB) is about 35.1 dBm. These results show, 16.5% improvement in PAE, 1.33 dB increment in gain and 1.1 dB improvement in linearity operating range of proposed amplifier compared to the conventional PA.     

Design of a highly PAE class-F power amplifier using front coupled tapered compact microstrip resonant cell

This article presents the design and implementation of a class-F power amplifier (PA) with a low voltage pHEMT, using a novel Front Coupled Tapered Compact Microstrip Resonant Cell (FCTCMRC) for obtaining a high-efficiency performance. The FCTCMRC is used as a harmonic control circuit, which is short and open circuit for the second and third harmonics, respectively. The required dc-supply voltage is low due to application of a low-voltage pHEMT in the circuit implementation. Therefore, the class-F power amplifier is designed with a high power added efficiency (PAE) and compact circuit size. To verify the method, the designed class-F PA is fabricated using a pHEMT at 1.1 GHz. The proposed class-F power amplifier using the FCTCMRC has obtained 86%PAE under 10 dBm input power, which achieves 16% improvement, also, the circuit size including the harmonic control circuit and output matching is decreased about 25%, all in comparison with the designed PA using the conventional CMRC. The measurement results of the fabricated power amplifier are in good agreement with the simulation results, which verifies the proposed design methodology.     

基于低通滤波匹配网络的双频功率放大器设计

提出了一种基于低通滤波匹配网络的高效率并发双频功率放大器设计方法.将连续F类与连续逆F类功放模式相结合,在保证效率的前提下拓展了阻抗设计空间,同时在谐波范围内引入多个传输零点,完成低通滤波匹配网络的设计,对谐波进行抑制.为验证设计方法的合理性,设计制造了一款工作于1.6 GHz与2.4 GHz且带宽超过200 MHz的...     

应用于S频段的宽带高谐波抑制的F类功率放大器的设计

采用InGaP/GaAs HBT工艺设计了一个适用于S频段的宽带F类功率放大器,管芯大小为3×3×0.82mm3。为了同时实现高谐波抑制和宽带,在宽带匹配电路中使用了谐波陷波器。在1.8~2.5 GHz范围内,该匹配网络的输入阻抗约为一个常电阻,二次谐波阻抗约为零而三次谐波阻抗接近无穷大,因此提高了功率放大器的效率。输入测试信号为连续波,测试结果表明该功率放大器在1dB压缩点下的输出功率约为34dBm,PAE约为57%,2到4次谐波分量功率均小于-53dBc。     

A +31.5 dBm CMOS RF Doherty Power Amplifier for Wireless Communications

A fully differential Doherty power amplifier (PA) is implemented in a 0.13-mum CMOS technology. The prototype achieves a maximum output power of +31.5 dBm with a peak power-added efficiency (PAE) of 36% (39% drain efficiency) with a GMSK modulated signal. The PAE is kept above 18% over a 10 dB range of output power. With a GSM/EDGE input signal, the measured peak output power while still meeting the GSM/EDGE mask and error vector magnitude (EVM) requirements is +25dBm with a peak PAE of 13% (PAE is 6% at 12 dB back-off). Instead of using a bulky lambda/4 transmission line, a passive impedance inverter is implemented as a compact lumped-element network. All circuit components are fully integrated on a single CMOS die except for an off-chip capacitor for output matching and baluns. The die size is 2.8times3.2mm² including all pads and bypass capacitors     

A multimode,power-adjustable transmitter for UHF mobile RFID reader

Aiming at the expansive application of RFID technology, design considerations are expatiated to a highly-integrated, multimode, power-adjustable transmitter in mobile UHF RFID reader with CMOS process. The transmitter consists of digital, baseband and RF sections, including an up-conversion mixer and a gain-variable power amplifier (PA). Multiple data modes can be generated in digital section. The direct-conversion RF section is proposed to minimize the off-chip components and provide a low-cost, highly efficient solution. The highlight of the paper is the PA can achieve a maximum output power of 26 dBm and maintain a power-added efficiency (PAE) higher than 40% over the 18–26 dBm power range. Feasibility of the transmitter is validated by ADS simulator.     

High efficiency, wide dynamic range variable gain and poweramplifier MMICs for wideband CDMA handsets

A linearized variable gain amplifier (VGA) and a two-stage power amplifier (PA) MMIC were developed for 1.95-GHz wideband CDMA (W-CDMA) handsets application. A complete PA block with power control ability was obtained by cascading the VGA with the PA. The linearized VGA consists of a predistorter (PD) integrated with a conventional VGA, performing dual function for achieving high linearity power control, as well as reducing output distortion level of the following PA. With the use of predistortion, the P_out and power added efficiency (PAE) of the PA block improved from 27.5 dBm and 39.8% to 28.5 dBm and 44.8%, respectively, measured at -35 dBc adjacent channel leakage power ratio (ACPR). Under power control operation, the control range of the PA block increased from 23.6 dB to 31.2 db, and ACPR reduction of over 10 dB was achieved with the use of linearized VGA     

A Watt-Level Stacked-FET Linear Power Amplifier in Silicon-on-Insulator CMOS

A single-stage stacked field-effect transistor (FET) linear power amplifier (PA) is demonstrated using 0.28-$mu$ m 2.5-V standard I/O FETs in a 0.13- $mu$m silicon-on-insulator (SOI) CMOS technology. To overcome the low breakdown voltage limit of MOSFETs, a stacked-FET structure is employed, where four transistors are connected in series so that their output voltage swings are added in phase. With a 6.5-V supply, the measured PA achieves a small-signal gain of 14.6 dB, a saturated output power of 32.4 dBm, and a maximum power-added efficiency (PAE) of 47% at 1.9 GHz. Using a reverse-link IS-95 code division multiple access modulated signal, the PA shows an average output power of up to 28.7 dBm with a PAE of 41.2% while meeting the adjacent channel power ratio requirement. Using an uplink wideband code division multiple access modulated signal, the PA shows an average output power of up to 29.4 dBm with a PAE of 41.4% while meeting the adjacent channel leakage ratio requirement. The stacked-FET PA is designed to withstand up to 9 V of supply voltage before reaching its breakdown limit. This is the first reported stacked-FET linear PA in submicrometer SOI CMOS technology that delivers watt-level output power in the gigahertz frequency range with efficiency and linearity performance comparable to those of GaAs-based PAs.      

Bandwidth enhancement of an inverse class-F power amplifier based on LDMOS devices

In this article, we report the design of an inverse class-F power amplifier for L-band transmit/receive module based on LDMOS (laterally diffused metal oxide semiconductor) transistors. The objective was to obtain high power efficiency over a wide band. Measurements showed a minimum of 61% power added efficiency (PAE) and 10?W output power with a gain of 14?dB over a bandwidth of 200?MHz. Average measured performances are, respectively, 11.4?W (±1.4?W) output power and 62.8% (±1.8%) PAE; 64.5% maximum PAE associated with 12.7?W output power has been reached. These results are, to our knowledge, the highest reported combination of power efficiency and bandwidth.     

High-Efficiency Class-F GaN HEMT Amplifier With Simple Parasitic-Compensation Circuit

This letter presents a highly efficient class-F power amplifier (PA) using a GaN high electron mobility transistor, which is designed at WCDMA band of 2.14 GHz. The simple and effective compensation circuit consisting of a series capacitor and a shunt inductor is used to compensate for the internal parasitic components of the packaged transistor. Also, the composite right/left-handed transmission lines are used as the harmonic tuner of the class-F PA. From the measured results for a continuous wave, the drain efficiency and power-added efficiency of 75.4% and 70.9% with a gain of 12.2 dB are achieved at an output power of 40.2 dBm.     

High Efficiency RF Power Amplifier Designed With Harmonic Real-Time Active Load-Pull

In this work, a high efficiency p-HEMT radio frequency power amplifier (PA) is designed using a new multiharmonic real-time active load-pull using the large signal network analyzer. This technique synthesizes a large set of instantaneous load mismatches to quickly find the optimal harmonic impedances, so as to achieve high PA efficiency in a shortened design cycle. At 2 GHz a demo power amplifier implemented with a p-HEMT demonstrated a power added efficiency (PAE) of 68.5% for 18.0 dBm output power, while achieving a maximum PAE of 75% below the 1 dB compression point for 18.6 dBm output power.     

A 0.4–2.3 GHz broadband power amplifier extended continuous class-F design technology

A 0.4–2.3 GHz broadband power amplifier (PA) extended continuous class-F design technology is proposed in this paper. Traditional continuous class-F PA performs in high-efficiency only in one octave bandwidth. With the increasing development of wireless communication, the PA is in demand to cover the mainstream communication standards’ working frequencies from 0.4 GHz to 2.2 GHz. In order to achieve this objective, the bandwidths of class-F and continuous class-F PA are analysed and discussed by Fourier series. Also, two criteria, which could reduce the continuous class-F PA’s implementation complexity, are presented and explained to investigate the overlapping area of the transistor’s current and voltage waveforms. The proposed PA design technology is based on the continuous class-F design method and divides the bandwidth into two parts: the first part covers the bandwidth from 1.3 GHz to 2.3 GHz, where the impedances are designed by the continuous class-F method; the other part covers the bandwidth from 0.4 GHz to 1.3 GHz, where the impedance to guarantee PA to be in high-efficiency over this bandwidth is selected and controlled. The improved particle swarm optimisation is employed for realising the multi-impedances of output and input network. A PA based on a commercial 10 W GaN high electron mobility transistor is designed and fabricated to verify the proposed design method. The simulation and measurement results show that the proposed PA could deliver 40–76% power added efficiency and more than 11 dB power gain with more than 40 dBm output power over the bandwidth from 0.4–2.3 GHz.     

A 20 dBm Linear RF Power Amplifier Using Stacked Silicon-on-Sapphire MOSFETs

In this letter, a fully integrated 20-dBm RF power amplifier (PA) is presented using 0.25-mum-gate silicon-on-sapphire metal-oxide-semiconductor field-effect transistors (MOSFETs). To overcome the low breakdown voltage limit of MOSFETs, a stacked FET structure is employed, where transistors are connected in series so that each output voltage swing is added in phase. By using triple-stacked FETs, the optimum load impedance for a 20-dBm PA increases to 50Omega, which is nine times higher than that of parallel FET topology for the same output power. Measurement of a single-stage linear PA shows small-signal gain of 17.1 dB and saturated output power of 21.0dBm with power added efficiency (PAE) of 44.0% at 1.88 GHz. With an IS-95 code division multiple access modulated signal, the PA shows an average output power of 16.3 dBm and PAE of 18.7% with adjacent channel power ratio below -42dBc     

60 G Hz 11 dBm CMOS功率放大器设计

近年来60 GHz附近的一个连续频段可以自由使用,这为短距离的无线个域网等高速率传输的应用提供了条件.设计了一个工作在60 GHz的CMOS功率放大器.采用台积电0.13μmRF-CMOS工艺设计制造,芯片面积为0.35mm × 0.4 mm,最大线性输出功率为11 dBm,增益为9.7 dB,漏极增加效率(η_(PAE))为9.1%.达到应用在通信距离为10 m的无线个域网(WPAN)射频电路中的要求.设计中采用了厚栅氧化层工艺器件和Load-Pull方法设计最优化输出阻抗z_(opt),以提高输出功率.该方法能较大提高CMOS功率放大器的输出功率,可以应用到各种CMOS功率放大器设计中.