Process and device characterization for a 30-GHz fT submicrometer double poly-Si bipolar technology using BF2-implanted base with rapid thermal process

Process and device parameters are characterized in detail for a 30-GHz f_T submicrometer double poly-Si bipolar technology using a BF₂-implanted base with a rapid thermal annealing (RTA) process. Temperature ramping during the emitter poly-Si film deposition process minimizes interfacial oxide film growth. An emitter RTA process at 1050°C for 30 s is required to achieve an acceptable emitter-base junction leakage current with an emitter resistance of 6.7×10^-7 Ω-cm², while achieving an emitter junction depth of 50 nm with a base width of 82 nm. The primary transistor parameters and the tradeoffs between cutoff frequency and collector-to-emitter breakdown voltage are characterized as functions of base implant dose, pedestal collector implant dose, link-base implant dose, and epitaxial-layer thickness. Transistor geometry dependences of device characteristics are also studied. Based on the characterization results for poly-Si resistors, boron-doped p-type poly-Si resistors show significantly better performance in temperature coefficient and linearity than arsenic-doped n-type poly-Si resistors     

Fluorine effects in n-p-n double-diffused polysilicon emitterbipolar transistors

We demonstrate that fluorine incorporation in the polysilicon emitter of n-p-n double-diffused bipolar transistors during BF₂ implantation at a dose of 1×10¹⁵ cm^-2 significantly alters the device electrical characteristics. In particular, tunneling emitter/base currents are observed at both forward and reverse voltages, due to excessive base dopant concentration at the junction. Fluorine-enhanced interfacial oxide break-up and epitaxial realignment of the poly-Si emitter are shown to be responsible for these results     

I-V Characteristics of oxygen-doped Si epitaxial film (OXSEF)/Si heterojunctions

We have fabricated oxygen-doped Si epitaxial film (OX-SEF)/Si heterodiodes to examine device capabilities of the new wide-gap material, OXSEF. Various locations of the p-n junction with respect to the OXSEF/Si interface are achieved by changing the annealing time for arsenic diffusion from the implanted poly-Si layer on top of the OXSEF. When the p-n junction is located at the heterointerface, the diode n-value is 1.4-1.5 after H2annealing. This can be reduced to 1.1-1.2 by pushing the p-n junction into a Si substrate of about 600 Å.     

A new MoSi2/Thin poly-Si gate process technology without dielectric degradation of a gate oxide

The dielectric degradation phenomena in gate oxides of MoSi²/thin n⁺poly-Si (<100 nm) gate structure which appeared after high-temperature annealing have been analyzed in detail. Analyses included obtaining the correlation between gate oxide dielectric characteristics and various factors like phosphorus concentration in poly-Si, native oxide on poly-Si, sheet resistance of MoSi², and the SEM or TEM observations of textures of MoSi², poly-Si, and gate oxide. From analyses, it was concluded that the local reaction of molybdenum silicide with poly-Si under the presence of a barrier, like the thick native oxide on poly-Si formed before MoSi²deposition, results in the damage to a gate oxide through a thin poly-Si layer during annealing. Based upon analytical results, a new MoSi²/thin poly-Si gate process without dielectric degradation has been developed, in which the direct MoSi²deposition on undoped poly-Si to suppress the native oxide growth and phosphorus implantation into MoSi²were introduced. The process provided a good dielectric strength of a gate oxide even to the device with a poly-Si layer as thin as 50 nm, an easy dry etching without undercutting of poly-Si, and stable device characteristics and reliabilities compatible to a conventional poly-Si gate process.     

A new simple and reliable method to form a textured Si surface forthe fabrication of a tunnel oxide film

In this work, a textured Si surface was formed with a new simple and reliable method for tunnel oxide fabrication. First, a thin poly-Si layer (12 nm thick) was deposited on Si surface and a 30-nm thick dry oxide film was then grown in O₂ ambient. This oxide film was served as a sacrificial oxide. The poly-Si film and Si substrate were both oxidized during thermal oxidization. After stripping this sacrificial oxide, a textured Si surface was obtained. Tunnel oxide grown on this textured Si surface has asymmetrical J-E characteristics, less interface states generation and better reliability (larger Q_bd ) as compared to those of normal oxide     

大注入下多晶硅发射极晶体管特性的一维模拟

利用Yih－FenyChyan等的PET大注入模型，并考虑了发射极串联电阻RTE和多晶硅／硅界面氧化层延迟时间τox对器件特性的影响，编制了程序。结合实例模拟了在大注入下具有发射区、基区指数掺杂分布的PET的电流增益和频率特性（fT人和fmax）。模拟结果表明，RCA器件（发射区的多晶硅／硅界面氧化层厚度δ=1．4um）的β值高于HF器件（δ=0），但HF器件的fTmax值高于RCA器件。     

Negative gate bias instability in polycrystalline silicon TFT's

Degradation of the device characteristics of poly-Si TFT's are seen following negative gate bias stress at elevated temperatures. The degradation has two components, One component is the trapping of holes in the gate oxide; this is a similar phenomenon to the so called `negative bias instability' seen in mono-Si MOSFETs. The other component is state formation and removal in the poly-Si bulk, or at the poly-Si-SiO₂ interface, and this is similar to that seen in αSi:H TFT's. The states formed are not the same as those produced by hot carrier stressing     

A new model of gate capacitance as a simple tool to extract MOSparameters

This paper tackles the difficult task to extract MOS parameters by a new model of the gate capacitance that takes into account both poly-Si depletion and charge quantization and includes temperature effects. A new fast and iterative procedure, based on this simplified self-consistent model, will be presented to estimate simultaneously the main MOS system parameters (oxide thickness, substrate, and poly-Si doping) and oxide field, surface potentials at the Si/SiO₂ and at the poly-Si/SiO₂ interfaces. Its effectiveness will be demonstrated by comparing oxide field and oxide thickness to those extracted by other methods proposed in the literature. Moreover, these methods are critically reviewed and we suggest improvements to reduce their errors. The agreement between CV simulation and experimental data is good without the need of any free parameter to improve the fitting quality for several gate and substrate materials combinations. Finally, a simple law to estimate substrate and poly-Si doping in n⁺/n ⁺ MOS capacitors from CV curves is proposed     

Suppression of stress-induced leakage current after Fowler-Nordheimstressing by deuterium pyrogenic oxidation and deuterated poly-Sideposition

Reports on the effect of deuterium incorporation into gate oxide on stress-induced leakage current (SILC) under Fowler-Nordheim (F-N) electron injection. Deuterium atoms were introduced during the growth of the gate oxide by deuterium pyrogenic oxidation. A deuterated poly-Si film was also utilized as a gate electrode. The deuterated poly-Si gate electrode was deposited by deuterated monosilane (SiD₄) gas, as a substitute for hydrogenated monosilane (SiH₄) gas. The properties of the deuterated oxide were compared with those of deuterium-annealed oxide, i.e., the conventional method for deuterium incorporation into gate oxide. As a result, it was found that SILC after both polarities of F-N stressing was clearly suppressed by the use of both the deuterium pyrogenic oxide and the deuterated poly-Si gate. Experimental results for the depth profiles and thermal desorption characteristics of introduced-deuterium atoms, compared with the case of the deuterium annealing, indicated that both the deuterium incorporation not only into the Si/SiO₂ interface but also into bulk-SiO ₂ and the more stable chemical bonding of deuterium atoms are realized by deuterium pyrogenic oxidation     

Suppression of the boron penetration induced Si/SiO2interface degradation by using a stacked-amorphous-silicon film as thegate structure for pMOSFET

The authors report that the boron penetration through the thin gate oxide into the Si substrate does not only cause a large threshold voltage shift but also induces a large degradation in the Si/SiO₂ interface. An atomically flat Si/SiO₂ interface can be easily obtained by using a stacked-amorphous-silicon (SAS) film as the gate structure for p⁺ poly-Si gate MOS devices even with the annealing temperature as high as 1000°C     

High-current small-parasitic-capacitance MOSFET on a poly-Siinterlayered (PSI:Ψ) SOI wafer

A new type of silicon-on insulator (SOI) structure has been fabricated by using direct bonding technology to bury multilayered films consisting of poly-Si and SiO₂. A device with an ideal epitaxial channel structure was fabricated using a conventional MOS process on this novel multilayered SOI (100-nm SOI/10-nm SiO₂/poly-Si/500-nm SiO₂) wafer. In this device, the highly concentrated p⁺ poly-Si just beneath the nMOS channel region acts as a punchthrough stopper, and the buried thin backgate oxide under the SOI layer acts as an impurity diffusion barrier, keeping the impurity concentration in the SOI film at its original low level. The device fabricated was an ultrathin SOI MOSFET capable of operating at a current 1.5 times that of conventional hundred-nm devices at low voltages     

Experimental characterization of the diode-type polysilicon loadsfor CMOS SRAM

Experimental characterization of the diode-type n⁺-p-n ⁺ poly-Si loads for SRAM applications demonstrates that the resistance of the structure and its response to the bit-line voltages are dominated by such properties of the parasitic thin-film transistor associated with this device as fixed positive charge and `gate' oxide thickness. Topographical effects observed in this study are interpreted in terms of the thickness variation of a dielectric overlaying the poly-Si feature and the fixed positive charges present in this dielectric in the vicinity of the poly-Si surface     

A comprehensive study of suppression of boron penetration byamorphous-Si gate in P+-gate PMOS devices

This paper presents a comprehensive study of the impact of the silicon gate structure on the suppression of boron penetration in p⁺-gate devices. The characteristics and reliability for different gate structures (poly-Si, α-Si, poly-Si/poly-Si, poly-Si/α-Si, α-Si/poly-Si, and α-Si/α-Si) in p ⁺ polygate PMOS devices are investigated in detail. The suppression of boron penetration by the nitrided gate oxide is also discussed. The comparison is based on flatband voltage shift as well as the value of charge to breakdown. Results show that the effect of boron diffusion through the thin gate oxide in p⁺ polygate PMOS devices can be significantly suppressed by employing the as-deposited amorphous silicon gate. Stacked structures can also be employed to suppress boron penetration at the expense of higher polygate resistance. The single layer as-deposited amorphous silicon is a suitable silicon gate material in the p⁺-gate PMOS device for future dual-gate CMOS process. In addition, by employing a long time annealing at 600°C prior to p⁺-gate ion implantation and activation, further improvements in suppression of boron penetration, polygate resistance, and gate oxide reliability can be achieved for the as-deposited amorphous-Si gate. Modifying the silicon gate structure instead of the gate dielectrics is an effective approach to suppress the boron penetration effect     

A Novel Blocking Technology for Improving the Short-Channel Effects in Polycrystalline Silicon TFT Devices

An original blocking technology is proposed for improving the short-channel characteristics of polycrystalline silicon thin-film transistors (poly-Si TFTs). In particular, two types of modified devices called poly-Si TFT with block oxide and poly-Si on partial insulator (POPI)-TFT are designed for the first time in this field to enhance device performance. The proposed TFT structures can significantly reduce short-channel effects when compared with a thick source/drain (S/D) poly-Si TFT (i.e., the fully depleted TFT). In addition, an ultrathin (UT) S/D structure (UT-TFT) is designed to verify that the block oxide TFT devices do achieve improved performance without needing the thin active layers and ultrashallow junction depth. Also, the POPI-TFT is found to reduce the thermal instability through its natural body-tied scheme.     

Capacitance analysis of devices with electrically floating regions

Operation mechanisms of devices with electrically floating regions have been analyzed by device simulations. An insulator has been modeled as a wide-gap semiconductor and the device simulation has been carried out in the whole region including insulator and floating regions. By using this approach, we have evaluated electrical properties of the capacitances used to represent such devices; i.e., the capacitance of interconnect structures with metal-fill and the drain capacitance of an advanced SOI–MOSFET with an electrically floating interlayer.

When one-fourth of an insulating area between parallel interconnect-lines is occupied by a squared fill, the capacitance between the lines was found to increase by three-fourths, over the value for a parallel plate capacitance without dummy fills. Also, the drain capacitance of an advanced SOI–MOSFET structure, i.e., a Si/oxide/poly-Si/oxide/Si-substrate, was analyzed. When the doping concentration of the electrically floating poly-Si interlayer is not so high, the interlayer is partially depleted and a depletion capacitor is formed. The floating potential varies non-linearly with the applied bias and is smaller than the bias. The total capacitance of a multi-oxide-layered SOI–MOSFET structure is much lower than the MOS capacitance estimated from the oxide thickness. Floating elements have great advantages in terms of decreasing capacitance values.     

A super self-aligned selectively grown SiGe base (SSSB) bipolartransistor fabricated by cold-wall type UHV/CVD technology

A novel selective epitaxial growth (SEG) technology for fabricating the intrinsic SiGe-base layer of a double poly-Si self-aligned bipolar transistor has been developed. Selectively grown Si and SiGe-alloy layers were obtained by using Si₂H₆+GeH₄+Cl₂+B₂ H₆ gas system using cold-wall ultra-high vacuum (UHV)/CVD. We have optimized the growth conditions so that Si or SiGe grows selectively against Si₃N₄ both on single crystalline Si and on poly-Si of a structure consisting of a poly-Si layer overhanging the single crystalline Si substrate. The selective growth is maintained until the growth from the bottom Si and the top poly-Si coalesce. This selective growth permits a novel emitter-base self-aligned transistor which we call a super self-aligned selectively grown SiGe base (SSSB) HBT     

Highly reliable SiO2/Si3N4 stackeddielectric on rapid-thermal-nitrided rugged polysilicon for high-densityDRAM's

Experimental results are presented demonstrating that by using rapid thermal nitridation (RTN) of rugged poly-Si surface prior to Si ₃N₄ deposition, the quality and reliability of reoxidized Si₃N₄ dielectric (ON dielectric with an effective oxide thickness of about 35 Å) can be significantly improved over ON films on rugged poly-Si without RTN treatment. These improvements include significantly reduced defect-related dielectric breakdown, 10³ × increase in TDDB lifetime, lower leakage current, and suppressed electron-hole trapping and capacitance loss during stress     

n+/p+ Gate Bulk FinFETs With Locally Separated Channel Structure for Sub-50-nm DRAM Cell Transistors

We proposed a new p⁺/n⁺ poly-Si gate bulk fin-type field-effect transistor that has two channel fins separated locally by a shallow trench filled with oxide or p⁺ polygate. Key device characteristics were investigated by changing the n⁺ poly-Si gate length La, the material filling the trench, and the width and length of the trench at a given gate length L_g. It was shown that the trench filled with p⁺ poly-Si gate should not be contacted with the source/drain diffusion region to achieve an excellent I_on/I_off (> 1010) that is suitable for sub-50-nm dynamic random access memory cell transistors. Based on the aforementioned device structure, we designed reasonable Ls/Lg and channel fin width W_cfin at given L_g 's of 30, 40, and 50 nm.     

Si hetero-bipolar transistor with a fluorine-doped SiC emitter anda thin, highly doped epitaxial base

The effect of fluorine doping on SiC/Si heterojunction bipolar transistors (HBTs) is studied. The film properties of the fluorine-doped SiC and device characteristics of an HBT using the SiC emitter and a 50-nm-thick, highly doped epitaxial base (10¹⁹/cm³) are presented. The current gain is improved from 15 to 80 by doping with fluorine. The current gain is four times larger than that of a conventional poly-Si emitter homo-transistor with the same base structure. In spite of the very thin base, the Early voltage is over 100 V. Forward-bias tunneling current was hardly seen at the emitter-base junction. The fluorine appears to terminate the dangling bonds. The results show the possibility of fabricating transistors with a very thin, highly doped base     

Performance Improvement of Ultralow Temperature Polycrystalline Silicon TFT on Plastic Substrate by Plasma Oxidation of Polycrystalline Si Surface

The thin-film transistor (TFT) performances were enhanced and stabilized by the plasma oxidation of the polycrystalline Si surface prior to the plasma enhanced atomic layer deposition of an Al₂O₃ gate dielectric film. The authors attribute this improvement to the formation of a high-quality oxide interface layer between the gate dielectric film and the poly-Si film. The interface oxide has a predominant effect on the TFT's characteristics and is regulated by the plasma oxidation temperature and the gap distance between the electrode and polycrystalline Si surface