Overall Wafer Effectiveness (OWE): A novel industry standard for semiconductor ecosystem as a whole

As semiconductor industry reached nanotechnology generation and consumer electronics era, the competition is no longer among individual semiconductor companies. Indeed, the collaborations among horizontally specialized value providers are critical for the success of the companies as well as the whole ecosystem. This paper aims to propose a novel index, i.e., Overall Wafer Effectiveness (OWE), to measure wafer productivity and drive various improvement directions for semiconductor ecosystem as a whole. Furthermore, the proposed OWE can be easily extended to incorporate additional attributes such as mask-field-utilization, throughput, and yield for effective management. We conducted a number of case studies in real settings. The results have shown that OWE can be employed as a semiconductor industry standard to drive collaborative efforts among IC designers, equipment vendors, and manufacturers in the ecosystem to enhance total wafer effectiveness. This paper concludes with discussions on value propositions of proposed OWE indices and future research directions.     

Defective wafer detection using a denoising autoencoder for semiconductor manufacturing processes

Defective wafer detection is essential to avoid loss of yield due to process abnormalities in semiconductor manufacturing. For most complex processes in semiconductor manufacturing, various sensors are installed on equipment to capture process information and equipment conditions, including pressure, gas flow, temperature, and power. Because defective wafers are rare in current practice, supervised learning methods usually perform poorly as there are not enough defective wafers for fault detection (FD). The existing methods of anomaly detection often rely on linear excursion detection, such as principal component analysis (PCA), k-nearest neighbor (kNN) classifier, or manual inspection of equipment sensor data. However, conventional methods of observing equipment sensor readings directly often cannot identify the critical features or statistics for detection of defective wafers. To bridge the gap between research-based knowledge and semiconductor practice, this paper proposes an anomaly detection method that uses a denoise autoencoder (DAE) to learn a main representation of normal wafers from equipment sensor readings and serve as the one-class classification model. Typically, the maximum reconstruction error (MaxRE) is used as a threshold to differentiate between normal and defective wafers. However, the threshold by MaxRE usually yields a high false positive rate of normal wafers due to the outliers in an imbalanced data set. To resolve this difficulty, the Hampel identifier, a robust method of outlier detection, is adopted to determine a new threshold for detecting defective wafers, called MaxRE without outlier (MaxREwoo). The proposed method is illustrated using an empirical study based on the real data of a wafer fabrication. Based on the experimental results, the proposed DAE shows great promise as a viable solution for on-line FD in semiconductor manufacturing.     

Multiple-objective scheduling and real-time dispatching for the semiconductor manufacturing system

Implementing efficient scheduling and dispatching policies is a critical means to gain competitiveness for modern semiconductor manufacturing systems. In contemporary global market, a successful semiconductor manufacturer has to excel in multiple performance indices, consequently qualified scheduling approaches should provide efficient and holistic management of wafer products, information and manufacturing resources and make adaptive decisions based on real-time processing status to reach an overall optimized system performance. To cope with this challenge, a timed extended object-oriented Petri nets (EOPNs) based multiple-objective scheduling and real-time dispatching approach is proposed in this paper. Four performance objectives pursued by semiconductor manufacturers are integrated into a priority-ranking algorithm that serves as the initial scheduling guidance, and then all wafer lots will be dynamically dispatched by the hybrid real-time dispatching control system. A set of simulation experiments validate the proposed multiple-objective scheduling and real-time dispatching algorithm may achieve satisfactory performances.     

Long-term tool elimination planning for a wafer fab

Wafer manufacturers must make decisions regarding tool elimination due to changes caused by demand, product mixes, and overseas fab capacity expansion. Such a problem is raised by leading semiconductor manufacturers in Taiwan. This paper is aimed at developing a sound mechanism for tool portfolio elimination based on determining which equipment can be pruned. In the proposed mechanism, product mix, wafer output, capital expenditure, tool utilization, protective capacity, and cycle time are taken into the overall evaluation. This paper develops an integer programming model to avoid trial-and-error and to obtain the optimal solution. Compared to the current industry approach, the results show that the proposed mechanism can effectively identify the correct tools for elimination with a large capital savings and little cycle time impact.     

Defect spatial pattern recognition using a hybrid SOM–SVM approach in semiconductor manufacturing

As manufacturing geometries continue to shrink and circuit performance increases, fast fault detection and semiconductor yield improvement is of increasing concern. Circuits must be controlled to reduce parametric yield loss, and the resulting circuits tested to guarantee that they meet specifications. In this paper, a hybrid approach that integrates the Self-Organizing Map and Support Vector Machine for wafer bin map classification is proposed. The log odds ratio test is employed as a spatial clustering measurement preprocessor to distinguish between the systematic and random wafer bin map distribution. After the smoothing step is performed on the wafer bin map, features such as co-occurrence matrix and moment invariants are extracted. The wafer bin maps are then clustered with the Self-Organizing Map using the aforementioned features. The Support Vector Machine is then applied to classify the wafer bin maps to identify the manufacturing defects. The proposed method can transform a large number of wafer bin maps into a small group of specific failure patterns and thus shorten the time and scope for troubleshooting to yield improvement. Real data on over 3000 wafers were applied to the proposed approach. The experimental results show that our approach can obtain over 90% classification accuracy and outperform back-propagation neural network.     

A novel approach to hedge and compensate the critical dimension variation of the developed-and-etched circuit patterns for yield enhancement in semiconductor manufacturing

Linewidth control is critical for yield enhancement in semiconductor manufacturing. As wafer fabrication reaching nano-technology nodes, existing approaches on advanced equipment control and advanced process control (AEC/APC) for variation control of individual processes are increasingly difficult to achieve desired process control due to shrinking process windows. This study aims to propose a novel approach to determine tool affinity to hedge the variation between the photolithography for pattern development and the etching process to effectively reduce the etching bias caused by tool misalignment. In particular, the proposed approach integrates a feed-forward run-to-run (R2R) controller and the proposed mini-max regret tool dispatching rules in light of the tool characteristics of the photolithography and etching processes. To validate the proposed approach, an empirical study was conducted in a leading semiconductor company in Taiwan and the results showed practical viability of the approach.     

Optimizing class-constrained wafer-to-order allocation in semiconductor back-end production

This paper studies the problem of allocating semiconductor wafers to customer orders with the objective of minimizing the overallocation prior to assembly. It is an important problem for back-end semiconductor manufacturing as overallocation may have severe impact on operational performance due to excess inventory and unnecessarily occupied manufacturing equipment. In practice, a wafer can contain dies from several different die classes, making the wafer-allocation problem more challenging. As a novel contribution of this work, we explicitly consider the existence of multiple die classes on a wafer in the wafer-allocation problem. An integer linear programming formulation of the class-constrained wafer allocation problem is provided. The formulation is further extended to be more flexible by allowing the dies from different classes on the same wafer to be allocated to distinct customer orders. A real-world case study from the back-end assembly and test facility of a semiconductor manufacturer is presented. Experiments with real-world data show that the proposed method significantly reduces the overallocation performance in current practice and allows planners to quantify the value of flexibility in wafer allocation.     

Integrated maintenance and operations decision making with imperfect degradation state observations

In highly flexible and integrated manufacturing systems, such as semiconductor fabs, strong interactions between the equipment condition, operations executed on the various machines and the outgoing product quality necessitate integrated decision making in the domains of maintenance scheduling and production operations. Furthermore, in highly complex manufacturing equipment, the underlying condition is not directly observable and can only be inferred probabilistically from the available sensor readings. In order to deal with interactions between maintenance and production operations in Flexible Manufacturing Systems (FMSs) in which equipment conditions are not perfectly observable, we propose in this paper a decision-making method based on a Partially Observable Markov Decision Processes (POMDP's), yielding an integrated policy in the realms of maintenance scheduling and production sequencing. Optimization was pursued using a metaheuristic method that used the results of discrete-event simulations of the underlying manufacturing system. The new approach is demonstrated in simulations of a generic semiconductor manufacturing cluster tool. The results showed that, regardless of uncertainties in the knowledge of actual equipment conditions, jointly making maintenance and production sequencing decisions consistently outperforms the current practice of making these decisions separately.     

A combined dispatching criteria approach to scheduling semiconductor manufacturing systems

The scheduling problem of semiconductor manufacturing systems has multiple responses of interest. The objective is to simultaneously optimize these different responses or to find the best-compromised solution. Most previous research in the area of semiconductor manufacturing systems has focused on optimizing a single performance measure. Dabbas and Fowler proposed a modified dispatching approach that combines multiple dispatching criteria into a single rule with the objective of simultaneously optimizing multiple objectives. In this paper, we validate their proposed approach using two different fab models at different levels of complexity: a hypothetical six stage-five machines Mini-Fab model and a full scale wafer fab model adapted from an actual Motorola wafer fab. We also discuss the actual implementation of the proposed dispatching algorithm into a scheduler for daily operation at a Motorola wafer fabrication facility. Results show an average 20% improvement for all responses when using the proposed dispatching approach.     

A data-driven two-stage maintenance framework for degradation prediction in semiconductor manufacturing industries

To reduce the production costs and breakdown risks in industrial manufacturing systems, condition-based maintenance has been actively pursued for prediction of equipment degradation and optimization of maintenance schedules. In this paper, a two-stage maintenance framework using data-driven techniques under two training types will be developed to predict the degradation status in industrial applications. The proposed framework consists of three main blocks, namely, Primary Maintenance Block (PMB), Secondary Maintenance Block (SMB), and degradation status determination block. As the popular methods with deterministic training, back-propagation Neural Network (NN) and evolvable NN are employed in PMB for the degradation prediction. Another two data-driven methods with probabilistic training, namely, restricted Boltzmann machine and deep belief network are applied in SMB as the backup of PMB to model non-stationary processes with the complicated underlying characteristics. Finally, the multiple regression forecasting is adopted in both blocks to check prediction accuracies. The effectiveness of our proposed two-stage maintenance framework is testified with extensive computation and experimental studies on an industrial case of the wafer fabrication plant in semiconductor manufactories, achieving up to 74.1% in testing accuracies for equipment degradation prediction.     

Optimization of Wafer Exposure Patterns Using a Two-Dimensional Cutting Algorithm

The semiconductor industry plays an integral role in Taiwan's manufacturing sector. Although defect reduction has received considerable attention to improve the yield rate, the problem of optimizing wafer exposure patterns has seldom been addressed. This study formulates the wafer exposure-patterning problem into a cutting and packing problem by adopting an innovative approach. We developed a two-dimensional cutting algorithm to maximize the number of dies that can be produced from a wafer to increase the gross die yield. The proposed algorithm is successfully implemented in a wafer fabrication factory. Experimental results validate the effectiveness of the proposed algorithm.     

Raising the hit rate for wafer fabrication by a simple constructive heuristic

The rate of on-time delivery, namely hit rate, is a very significant performance measurement index for semiconductor wafer fabrication. This study proposes an efficient simple constructive heuristic (SCH), called slack multiplied uncompleted ratio (SMUR), for raising the hit rate in wafer fabs. Effectiveness of the proposed SMUR heuristic is verified by conducting simulation experiments based on a well known model from the relevant literature. The results indicate that the proposed SMUR heuristic is a state-of-the-art SCH for the current problem by comparing the obtained results to the best available SCHs in the relevant literature. Since the proposed SMUR heuristic is easy to implement and decreases the computational burden, this study successfully develops a practical approach which will hopefully encourage practitioners to apply it to real world problems.     

Optimal Integrated Schedule of Entire Process of Dual-blade Multi-cluster Tools From Start-up to Close-down

Multi-cluster tools are widely used in majority of wafer fabrication processes in semiconductor industry. Smaller lot production, thinner circuit width in wafers, larger wafer size, and maintenance have resulted in a large quantity of their start-up and close-down transient periods. Yet, most of existing efforts have been concentrated on scheduling their steady states. Different from such efforts, this work schedules their transient and steady-state periods subject to wafer residency constraints. It gives the schedulability conditions for the steady-state scheduling of dual-blade robotic multi-cluster tools and a corresponding algorithm for finding an optimal schedule. Based on the robot synchronization conditions, a linear program is proposed to figure out an optimal schedule for a start-up period, which ensures a tool to enter the desired optimal steady state. Another linear program is proposed to find an optimal schedule for a close-down period that evolves from the steady state period. Finally, industrial cases are presented to illustrate how the provided method outperforms the existing approach in terms of system throughput improvement.      

一种基于动态平衡树的在线索引快速构建方法

倒排索引的构建可以通过离线方式高效地完成,但是仅当整个数据集索引完毕后方可提供检索服务.在线索引可以在构建倒排索引的同时提供检索服务,新加入的文档即刻可供检索.提出了一种基于动态平衡树的在线索引更新策略,利用动态平衡树控制索引合并过程,使索引合并总是在大小相近的子索引之间进行,以减少索引合并代价,同时可以调节索引和检索之间的性能平衡.该方法提供了一个基于合并的在线索引更新框架,与已有方法相比具有更好的通用性、更高的性能和更好的规模可扩展性.在由4000万张网页构成的270 GB Web数据集上运行的实验表明,该方法在实际系统中是高效的,将索引更新的性能提高了92.28%,而检索性能仅下降4.79%,大幅度降低了在线索引构建的代价.     

Wafer defect pattern recognition by multi-class support vector machines by using a novel defect cluster index

Wafer yield is an important index of efficiency in integrated circuit (IC) production. The number and cluster intensity of wafer defects are two key determinants of wafer yield. As wafer sizes increase, the defect cluster phenomenon becomes more apparent. Cluster indices currently used to describe this phenomenon have major limitations. Causes of process variation can sometimes be identified by analyzing wafer defect patterns. However, human recognition of defect patterns can be time-consuming and inaccurate. This study presents a novel recognition system using multi-class support vector machines with a new defect cluster index to efficiently and accurately recognize wafer defect patterns. A simulated case demonstrates the effectiveness of the proposed model.     

两阶段设备维护策略选择的灰靶决策模型

针对设备的最佳维护策略选择问题,首先提出6种设备运维目标,同时给出两阶段设备运维策略选择的加权智能灰靶决策模型的架构图以及建模算法流程;然后采用德尔菲调查法与层次分析法相结合确定不同目标的权重.结合某半导体面板制造企业的设备运行现场实际数据,对于成本型目标和适中型目标,分别采用相应的效果测度函数计算出设备在不同运行状态下的一致效果测度矩阵以及综合效果测度矩阵.通过运用两阶段设备维护的灰靶决策模型,最终得到设备不同状态下的最佳维护策略.所提出方法对正确选择半导体面板设备维护策略、提高设备运维效率、降低维护成本具有实际指导意义.     

A new intelligent SOFM-based sampling plan for advanced process control

Sample measurement inspecting for a process parameter is a necessity in semiconductor manufacturing because of the prohibitive amount of time involved in 100% inspection while maintaining sensitivity to all types of defects and abnormality. In current industrial practice, sample measurement locations are chosen approximately evenly across the wafer, in order to have all regions of the wafer equally well represented, but they are not adequate if process-related defective chips are distributed with spatial pattern within the wafer.In this paper, we propose the methodology for generating effective measurement sampling plan for process parameter by applying the Self-Organizing Feature Map (SOFM) network, unsupervised learning neural network, to wafer bin map data within a certain time period. The sampling plan specifies which chips within the wafer need to be inspected, and how many chips within the wafer need to be inspected for a good sensitivity of 100% wafer coverage and defect detection. We finally illustrate the effectiveness of our proposed sampling plan using actual semiconductor fab data.     

Development of Wafer Warehouse Management System for Semiconductor Manufacturing Foundry Supply Chain

Efficiency of supply chains management mostly depends on the process coordination and information integration between the supply chain companies.The well-known integrated circuit design houses,the wafer fabrication industries, and the integrated circuit packaging/testing business has together formed a contiguous supply chain from materials to system in Taiwan during the past decades.Logistic management of the wafer hence becomes the key linkage in the semiconductor foundry supply chain.The objective of this paper is to develop the wafer warehouse management system for global wafer logistics.Current operations for wafer logistics management are firstly reviewed. The system requirements are analyzed by the model-driven business transformation approach.The business operation model and the platform-independent solution architecture for the wafer logistics management are constructed.A prototype information system is also developed for validation.Results of this research can improve the effectiveness and efficiency in wafer logistics management for the semiconductor foundry supply chain.     

Multi-objective real-time dispatching for integrated delivery in a Fab using GA based simulation optimization

In a wafer fabrication Fab, the “integrated delivery”, which integrates the automated material handling system (AMHS) with processing tools to automate the material flow, is difficult to implement due to the system complexity and uncertainty. The previous dispatching studies in semiconductor manufacturing have mainly focused on the tool dispatching. Few studies have been done for analyzing combinatorial dispatching rules including lot dispatching, batch dispatching and automated guided vehicle (AGV) dispatching. To handle this problem, a GA (genetic algorithm) based simulation optimization methodology, which consists of the on-line scheduler and the off-line scheduler, is presented in this paper. The on-line scheduler is used to monitor and implement optimal combinatorial dispatching rules to the semiconductor wafer fabrication system. The off-line scheduler is employed to search for optimal combinatorial dispatching rules. In this study, the response surface methodology is adopted to optimize the GA parameters. Finally, an experimental bay of wafer fabrication Fab is constructed and numerical experiments show that the proposed approach can significantly improve the performance of the “integrated delivery system” compared with the traditional single dispatching rule approach.     

A new strategy for defect inspection by the virtual inspection in semiconductor wafer fabrication

The defect of process equipments is a major factor that impairs the yields in the mass production of semiconductor wafer fabrication and it is a main supervision means to use high-resolution defect inspection tools to detect and monitor the defect damage. Due to the high investment costs of these inspection tools and the resulting decrease in the throughput, how to improve the sampling rate is an important issue for the associated inspection strategy. This paper proposes a new concept and implementation of virtual inspection (VI) to enhance the detection and monitoring of defect in semiconductor production process. The underlying theory of the VI concept is that the state variables identifications (SVIDs) of process equipments can reflect the process quality effectively and loyally. The approach of VI is to combine the application of the fault detection and classification (FDC), and the defect library and the re-engineering of inspection procedure to reach the full-scope of strategic objective. VI enables the defect monitoring to enter a new era by promoting the monitoring level of defect inspection from the previous lot-sampling basis to the wafer-sampling level, and hence upgrades the sampling strategy from random-sampling to full and right-sampling. In this study, various typical defect cases are utilized to illustrate how to create VI models and verify the reliability of the proposed approach. Furthermore, a feasible architecture of the VI implementation for mass production in semiconductor factory is presented in the paper.