An 8.8-ns 54×54-bit multiplier with high speed redundantbinary architecture

A high speed redundant binary (RB) architecture, which is optimized for the fast CMOS parallel multiplier, is developed. This architecture enables one to convert a pair of partial products in normal binary (NB) form to one RE number with no additional circuit. We improved the RB adder (RBA) circuit so that it can make a fast addition of the RB partial products. We also simplified the converter circuit that converts the final RE number into the corresponding NE number. The carry propagation path of the converter circuit is carried out with only multiplexer circuits. A 54×54-bit multiplier is designed with this architecture. It is fabricated by 0.5 μm CMOS with triple level metal technology. The active area size is 3.0×3.08 mm² and the number of transistors is 78,800. This is the smallest number for all 54×54-bit multipliers ever reported. Under the condition of 3.3 V supply voltage, the chip achieves 8.8 ns multiplication time. The power dissipation of 540 mW is estimated for the operating frequency of 100 MHz. These are, so far, the fastest speed and the lowest power for 54×54-bit multipliers with 0.5-μm CMOS     

A 4.4 ns CMOS 54×54-b multiplier using pass-transistormultiplexer

A 54×54-b multiplier using pass-transistor multiplexers has been fabricated by 0.25 μm CMOS technology. To enhance the speed performance, a new 4-2 compressor and a carry lookahead adder (CLA), both featuring pass-transistor multiplexers, have been developed. The new circuits have a speed advantage over conventional CMOS circuits because the number of critical-path gate stages is minimized due to the high logic functionality of pass-transistor multiplexers. The active size of the 54×54-b multiplier is 3.77×3.41 mm. The multiplication time is 4.4 ns at a 3.5-V power supply     

A 10 ns 54×54 b parallel structured full array multiplierwith 0.5 μm CMOS technology

A 54 b×54 b multiplier fabricated in a double-metal 0.5 μm CMOS technology is described. The 54 b×54 b full array is adopted to complete multiplication within one latency. A 10 ns multiplication time is achieved by optimizing both the propagation time of the part consisting of 4-2 compressors and the propagation time of the final adder part. The n-channel pass-transistor circuit and the p-channel load circuit are used at the critical blocks to improve the multiplication speed. This multiplier is intended to be applied to double-precision floating-point data processing based on the IEEE standard up to clock range of 100 MHz     

A 4.1-ns compact 54×54-b multiplier utilizing sign-selectBooth encoders

A 54×54-b multiplier with only 60 K transistors has been fabricated by 0.25-μm CMOS technology. To reduce the total transistor count, we have developed two new approaches: sign-select Booth encoding and 48-transistor 4-2 compressor circuits both implemented with pass transistor logic. The sign-select Booth algorithm simplifies the Booth selector circuit and enables us to reduce the transistor count by 45% as compared with that of the conventional one. The new compressor reduces the count by 20% without speed degradation. By using these new circuits, the total transistor count of the multiplier is reduced by 24%. The active size of the 54×54-b multiplier is 1.04×1.27 mm and the multiplication time is 4.1 ns at a 2.5-V power supply     

Low-Power Constant-Coefficient Multiplier Generator

Constant-coefficient multipliers are used in many DSP cores. A new low-power constant multiplier, with detailed design procedure, is presented. By using canonical sign-digit (CSD) number system, and introducing new simplification techniques and identities, the multiplier features a new algorithm to reduce logic depth for the Wallace-tree implementation. The method also reduces area and complexity.A generator written in C++ is used to generate technology-independent VHDL code of the constant multiplier for different input specifications. Synthesis results indicate the new design has smaller area and less power consumption while offering similar speed performance when compared with other multipliers.     

A multiplexer-based architecture for high-density, low-power gatearrays

This paper presents a novel architecture that provides higher density and lower power dissipation than conventional basecells. The layout of transistors in this small basecell allows the efficient construction of multiplexers with minimal use of programmable layers. The multiplexer can be used to create any 2 input and some 3 input functions in one basecell. Internal fanout, rather than typical output load, defines the size of driver and multiplexer transistors, which can be independently tailored for the desired speed/area/power target. This basecell, which is well suited for implementing datapath elements, has been used to create a 16×16-b multiplier operating at 50 MHz in 314500 μm² in 0.6 μm technology     

A 54×54-b regularly structured tree multiplier

A 54-b×54-b parallel multiplier was implemented in 0.88-μm CMOS using the new, regularly structured tree (RST) design approach. The circuit is basically a Wallace tree, but the tree and the set of partial-product-bit generators are combined into a recurring block which generates seven partial-product bits and compresses them to a pair of bits for the sum and carry signals. This block is used repeatedly to construct an RST block in which even wiring among blocks included in wire shifters is designed as recurring units. By using recurring wire shifters, the authors can expand the level of repeated blocks to cover the entire adder tree, which simplifies the complicated Wallace tree wiring scheme. In addition, to design time savings, layout density is increased by 70% to 6400 transistors/mm², and the multiplication time is decreased by 30% to 13 ns     

Self-timed divider based on RSD number system

The authors propose a divider structure that combines a novel self timed ring structure and a carry-propagation-free division algorithm. The self-timed ring structure enables the divider to compute at a speed comparable to that of previously designed dividers with less silicon area. By exploiting the carry-propagation-free division algorithm, an even better performance can be achieved. The authors designed a layout of 54 b divider using 1.2 μm CMOS technology and measured the area and speed. A speed of 135 ns per worst case division was obtained on 5.7 mm² of silicon area     

基于改进的混合压缩结构的Wallace树设计

文章针对典型的32位浮点乘法器,对Booth算法产生的部分积重新分组,采用CSA和4-2压缩器的混合电路结构,对传统的Wallace树型乘法器进行改进,并提出一种高速的树型乘法器阵列结构。该结构与传统的Wallace树型相比,具有更小的延时、更规整的布局布线,使其更易于VLSI实现。     

A 15-ns 32×32-b CMOS multiplier with an improved parallelstructure

A high-speed 32×32-b parallel multiplier with an improved parallel structure using 0.8-μm CMOS triple-level-metal technology is discussed. A unit adder, a 4-2 compressor, enhances the parallelism of the multiplier array. A 25% reduction in the propagation delay time is achieved by using the compressor. The multiplier contains 27704 transistors with a 2.68-×2.71-mm² die area. The multiplication time is 15 ns at 5 V with a power dissipation of 277 mW at 10-MHz operation. The triple-level-metal interconnection technology reduces the multiplier layout area. Compared with double-level-metal technology, a 27% chip size reduction is achieved     

67×67位乘法器的改进四阶Booth算法实现

针对67×67位乘法器,提出并实现新型的设计方法.先提出改进的四阶Booth算法,对乘数编码,以减少部分积的数目,提高压缩速度和减少面积,再研究优化和分配方法,对部分积和进位信号以及一个134位的补偿向量进行优化分配,并对部分积压缩,最后研究K-S加法器的改进方法,求和以实现134位乘积.采用TSMC的0.18 μm工艺库,Synopsys的Design compiler工具和Altera的Quautus4.2工具分析结果表明,基于本文方法实现的电路比DesignWare自带的乘法器实现的电路相比,性能总体占优.     

Optical fiber drawing method with gas flow controlling system

A method for reducing the diameter variation of optical fibers during fiber drawing is described. The method is based on the control of gas flow and drawing speed. Rapid fluctuations in diameter are suppressed by adjusting the gas flow rate, and slower ones are controlled by changing the drawing speed. The efficiency of this method has been tested by applying stepwise disturbance of ±63% in preform feeding speed. Fluctuations of fiber diameter are controlled within ±1 μm despite the forced disturbance. By applying this method to high-speed drawing (30 m/min), a high-tensile-strength fiber, with diameter fluctuations within ±1 μm and transmission losses near the 0.85-μm wavelength region of approximately 3 dB/km, is achieved     

Small area versus narrow line width effects on the C49 to C54transformation of TiSi2

Polycrystalline silicon (poly) structures of equal area and varying line width were subjected to a standard self-aligned TiS₂ process. The poly lines had widths of 0.4, 0.5, 1.0, and 2.0 μm and the total contiguous silicided area ranged from 7 to over 2500 μm₂. On all large area structures (silicided area >100 μm₂) our findings were consistent with the well-known narrow line width effect; i.e., the kinetics of transformation were adversely affected as the line width decreased, but with a sufficiently high thermal budget complete transformation to the C54 phase was possible. However, on structures with silicided area less than 100 μm ₂, a small area effect was observed in addition to the narrow line width effect. A percentage of small area lines remained entirely in the C49 phase (because of an apparent absence of C₅₄ nucleation sites) regardless of the thermal budget. This percentage increased with decreasing silicided area but was independent of the line width. Only the small area lines that did transform to the C54 phase exhibited the narrow line width effect. Therefore, for the range of line widths studied, the narrow line width mechanism and the small area mechanism were distinct     

High speed multiplier using Nikhilam Sutra algorithm of Vedic mathematics

This article presents the design of a new high-speed multiplier architecture using Nikhilam Sutra of Vedic mathematics. The proposed multiplier architecture finds out the compliment of the large operand from its nearest base to perform the multiplication. The multiplication of two large operands is reduced to the multiplication of their compliments and addition. It is more efficient when the magnitudes of both operands are more than half of their maximum values. The carry save adder in the multiplier architecture increases the speed of addition of partial products. The multiplier circuit is synthesised and simulated using Xilinx ISE 10.1 software and implemented on Spartan 2 FPGA device XC2S30-5pq208. The output parameters such as propagation delay and device utilisation are calculated from synthesis results. The performance evaluation results in terms of speed and device utilisation are compared with earlier multiplier architecture. The proposed design has speed improvements compared to multiplier architecture presented in the literature.     

Compact low voltage four quadrant CMOS current multiplier

A new compact low voltage four quadrant current mode CMOS multiplier is presented. Post layout simulation in a CMOS 0.5 μm technology shows a linearity error lower than 0.9% for signal swings up to ±50 μA. The circuit operates at a supply of ±1.5 V, has a static power dissipation of 0.6 mW and a 1 dB bandwidth of 33 MHz     

一种32位高速浮点乘法器设计

文章介绍一种32位浮点乘法器软IP的设计,其部分积缩减部分采用修正Booth算法,部分积加法采用4-2压缩树结构,最终carry、sum形式部分积采用进位选择加法器完成,乘法器可以进行32位浮点数或24位定点数的乘法运算。采用VerilogHDLRTL级描述,采用SMIC0.18μm工艺库进行综合,门级仿真结果表明乘法器延时小于4.05ns。     

A carry-free 54b×54b multiplier using equivalent bitconversion algorithm

An equivalent bit conversion algorithm (EBCA) is proposed to eliminate the need for final carry propagation in the redundant binary (RB) to normal binary (NB) conversion step for RB multiplication. The multiplication process helps with the carry-free conversion step by eliminating certain combinations of RB product. When the EBCA is applied, conventional power-consuming carry-propagating adders are replaced by simple, minimum-sized carry-free converters, and the entire multiplication process can be made free of carry propagation from input to output. The method employed in this work reduces 40% of the total power and 30% of the total multiplication time in the final adder stage of traditional multipliers. The prototype fabricated in 0.35-μm CMOS demonstrates that the 54 b×54 b multiplier consumes only 53.4 mW at 3.3 V for 74-MHz operation     

基于Booth\CSD混合编码的模 乘法器的设计

在余数系统的设计中,模加法器和模乘法器的设计处于核心地位,尤其是模乘法器的性能,是衡量余数系统系能的主要标志之一。文中先推导出Booth编码下的模 乘法器设计的算法,然后针对Booth编码模乘法器设计中译码电路复杂的问题,提出了一种基于Booth/ CSD混合编码的模乘法器设计方法,基于Booth/CSD编码的模乘法器部分积的位宽相对传统的Booth编码乘法器而言,减少了50%;经试验证明,与传统的基-Booth编码的模乘法器相比这种混合编码的模乘法器的速度提高了5%,面积减少24.7%。     

High performance CMOS current comparator

A new high-speed CMOS current comparator is described. By changing the buffer of an existing comparator from class B to class AB operation, voltage swings are reduced, resulting in greater speed for small input currents. Simulation results employing a 1.6μm CMOS technology show the response time to a 0.1μA input current to be 11ns and the power dissipation to be 1.4mW, resulting in a five times improvement in speed/power ratio over existing high-speed current comparators     

一种规整高效的缩1码模2^n＋1乘法器的VLSI设计

针对目前缩1码模2n＋1乘法器的优缺点,设计出一个有效的缩1码模2n＋1乘法器。该模乘法器是由改进的基-4 Booth编码模块、规整的缩1码进位保留加法器树以及缩1码模加法器构成,部分积的个数减少到n/2＋2个,具有统一的编码电路,简单的校正项生成电路,较快的计算速度,尤其是能够处理操作数和结果为0的情况,实现了操作数的全输入。比较结果表明,该模乘法器在同类型模乘法器中以最少的面积获得了更快的速度。