共查询到18条相似文献,搜索用时 109 毫秒
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对H.264协议的变换编码和量化进行了理论分析,给出了具体实现过程,论证了这种变换和量化方式的特点、有效性及应用前景。 相似文献
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H.26L中变换编码和量化的原理与分析 总被引:9,自引:0,他引:9
H.26L标准是ITU-T正在制定的新的图像压缩标准。H.26L在 H.263的基础上,对4×4像素大小的块上进行残差的变换编码,且使用了一种整数变换方法,以达到更好的压缩效果。本文分析了H.26L中整数变换编码,并且将这种新的变换编码与H.263所使用的8×8点DCT变换编码进行比较分析,得出这种编码的优点,证实其能达到更高效的压缩能力。然后分析了H.26L中与变换编码相关的量化过程,指出其与变换编码通过相互结合,使H.26L编码标准相对于以前的编码标准更加实用和有效。 相似文献
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根据H.264/AVC的变换量化原理,在FPGA上设计并实现了整数变换及量化部分。首先采用层次化、模块化的思想,将系统划分为多个功能模块,降低了硬件实现的复杂度,对DCT算法进行了优化,并对量化模块采用了流水线操作,最后设计全部采用Verilog硬件描述语言实现,并用Modelsim进行功能仿真,同时实验结果通过在Xilinx公司Vertex2P系列的XC2VP30 FPGA上验证。仿真及综合结果表明,与优化之前相比,系统所需时钟周期减少了29个,最大时钟频率可达到135.498MHz,为H.264标准的硬件实现提供了参考。 相似文献
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反量化、反变换(IQIT)是H.264解码过程中的重要环节之一文中根据H.264规范,设计了一种节省资源的IQIT模块.通过对其中矩阵运算单元进行多次复用,大大降低了对资源的占用,并通过FPGA进行了验证.该设计结构能够满足低功耗、便携式解码设备要求. 相似文献
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针对高清电视应用,实现了面向H.264主层面CABAC解码模块输出之后的宏块残差的顺序调整、反变换和反量化操作。借助高效组织的SRAM,本设计有效地连接了残差调序和反变换反量化两个部分,硬件资源得以充分利用,较好地解决了残差调序的时间瓶颈。同时,根据帧内帧间预测情况下亮度和色度的反变换反量化的算法,通过适当变换,采用同一块电路实现了所有情况下的操作。 相似文献
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下一代视频标准H.264中的图象的变换和量化 总被引:1,自引:1,他引:1
H.264是ITU—T和ISO共同制定的下一代视频标准。简单介绍了下一代视频压缩标准—H.264,并对H.264标准中变换和量化过程加以具体解释,最后通过例子来演示变换和量化的过程。 相似文献
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提出了一种适用于H.264/AVC解码器功能完整的反变换反量化IP核的设计.设计中采用同一处理单元完成三种不同的反变换,反变换反量化的每个步骤采用独立的门控时钟控制,逻辑复用和门控时钟降低了功耗.实现结果表明本设计满足1080i高清码流的实时解码要求. 相似文献
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Juan A. Michell José M. Solana Gustavo A. Ruiz 《Signal Processing: Image Communication》2011,26(2):93-104
In July 2004, a new amendment called Fidelity Range Extensions (FRExt) was added to the H.264/AVC as a standardization initiative motivated by the rapidly growing demands when coding higher-fidelity video material. One improvement present in the FRExt is the inclusion of a new 8×8 integer transform that only makes use of additions and shifters to avoid mismatches between encoders and decoders. This paper presents a processor with pipeline architecture for real-time implementation of the complete process for the 8×8 Transform Coding in H.264: forward 8×8 integer transform, quantization and scaling, re-scaling, inverse 8×8 integer transform and reconstruction of the image block. This architecture has been conceived with the aim of achieving a high operation frequency and high throughput without increasing the hardware complexity. In order to achieve an efficient implementation, hardware solutions have been developed for the different circuit modules. 8×8 forward and inverse transforms are calculated using the separability property with architecture more suitable for pipeline schemes made up of two 1D processors and a transpose register array. New expressions for forward quantization and scaling are presented allowing efficient hardware implementation by avoiding the sign conversion. The inverse quantization has also been optimized in terms of hardware complexity by minimizing the involved arithmetic operations. Furthermore, an exhaustive analysis in the dynamic range of the datapath is made to fix the optimum bus widths with the aim of reducing the size of the circuit while avoiding overflow. Finally, the critical paths of the various computing units have been carefully analyzed and balanced using a pipeline scheme in order to maximize the operation frequency without introducing an excessive latency. A prototype with the proposed architecture has been synthesized in a 130 nm HCMOS technology process, which achieves a maximum speed of 330 MHz with a throughput of 2640 Mpixels/s. 相似文献
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利用变换域信息快速实现H.264帧内预测编码的新算法 总被引:1,自引:0,他引:1
新的视频编码标准H.264中采用了帧内预测技术,能够极大地减少空间冗余性,从而进一步提高了对帧内宏块编码的效率,但同时也增大了帧内编码的计算时间。为了减少帧内编码时间和编码延迟,该文提出了一种能够快速实现帧内预测编码的新算法。该文算法先利用变换域的信息得到图像纹理的方向,只在最可能的几个模式中进行模式选择,从而降低了运算量。对不同的视频序列测试的结果表明,使用本算法后帧内编码时间可以减少70%左右,同时保持相近的图像压缩质量和码率水平。对于一些实时性要求苛刻的视频压缩应用,采用该文的快速算法会比较有效。 相似文献
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This paper deals with the process of Transformation and Quantization that is carried out on each inter-predicted residual
block in a video encoding process and their reduced complexity hardware implementation. H.264/AVC utilizes 4 × 4 integer transform,
which is derived from the 4 × 4 DCT. We propose, a reduced complexity algorithm and a pipelined structure for the Core forward
integer transform module. A multiplier-less architecture is realized with less number of shifts and adds compared to existing
works. The corresponding inverse transform is exactly reversible. Each of the transformed coefficients is quantized by a scalar
quantizer. The quantization step size can be varied from macroblock to macroblock. The proposed unified pipelined architecture
outperforms many recent implementations in terms of gate count and is capable of processing a 4 × 4 residual block in 4 clock
cycles.
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Reeba KorahEmail: |