支持智能能源管理让ZigBee更环保

自2004年发布第一个规范以来,ZigBee标准现在已经发展成熟到能够获得全世界认可的地步,并开始在市场上发挥举足轻重的作用.ZigBee提供了一个高性价比、基于多种标准的无线网络解决方案,该方案支持以低数据速率,低功耗网络通信为重点的技术.     

Modeling of multilevel converters

In this paper, the imbricated cells multilevel converters are studied and modeled from a control viewpoint. These converters make use of several switches connected in a series, which allows using switches with reduced voltage ratings; these low voltage switches have lower conduction losses and can switch at higher frequency. In addition to this feature common to all converters using series connected switches, the control signals of multilevel converters can be phase shifted to increase the apparent switching frequency and improve the dynamic performances of the whole converter. It is shown that a multilevel inverter leg, composed of p pairs of switches and p-1 capacitors, forms a multivariable nonlinear system that cannot be properly modeled by standard methods such as state-space averaging. The transient behavior of this system depends on the current harmonics and their phase shift with the different control signals. A specific model is detailed, studied, and used to illustrate the properties of these converters. In particular, the natural balancing of the voltage across the switches is demonstrated and the time constants involved in this process are determined     

Simple topologies of PWM AC-AC converters

This letter proposes a new family of simple topologies of PWM AC-AC converters with minimal switches. With extension from the basic DC-DC converters, a series of AC-AC converters such as buck, boost, buck-boost, Cuk, and isolated converters are obtained. By PWM duty ratio control, they become a "solid-state transformer" with a continuously variable turns ratio. All the proposed AC-AC converters in this paper employ only two switches. Compared to the existing circuits that use six switches or more, they can reduce cost and improve reliability. The operating principle and control method of the proposed topologies are presented. Analysis and simulation results are given using the Cuk AC-AC converter as an example. The analysis can be easily extended to other converters of the proposed family.     

Practical charge-transfer amplifier design architectures for low-power flash A/D converters

Two improved charge-transfer amplifiers (CTAs), used as zero-static-bias comparator preamplifiers in flash analog-digital converters, are proposed. The first improvement eliminates the capacitive coupling at the amplifier input, reducing area and input capacitance. The second eliminates the need for a common-mode output reference voltage by deriving the common-mode output from a switched average of the power supplies. In the latter, nearly a full-scale input range is achieved while preserving the low-power low offset characteristics of earlier CTAs. Voltage comparator devices were constructed in 0.6-/spl mu/m double-poly, triple-metal CMOS to test the prototype CTA architectures. Input common-mode range and offset performance consistent with simulation data is demonstrated with a 10X reduction in input capacitance. Measured dynamic power dissipation on the order of 3-6 /spl mu/W/MSPS is observed. The experimental CTA preamplifiers occupy roughly 0.015 mm/sup 2/.     

Output voltage distortion characterization in multilevel PWM converters

One of the main features to consider in the development of new pulsewidth modulations (PWM) for multilevel converters is the high-frequency output-voltage distortion. In this letter, a novel per-switching-cycle figure, the harmonic distortion of order n for switching cycle k(HD/sub n,k/), is introduced to quantitatively characterize the output three-phase voltage harmonic distortion of multilevel converters around all the integer multiples of the switching frequency. This figure allows for the decomposing of the modulation design problem within an output voltage fundamental cycle into an independent set of smaller problems for every switching cycle. The expression of HD/sub n,k/ as a function of the switching states' duty-ratio is presented for the three-level three-phase neutral-point-clamped voltage source inverter and it can be easily obtained for any other multilevel converter. From the evaluation of HD/sub n,k/ over 1/6th of the output-voltage fundamental-period the value of HD/sub n/ is obtained, providing a measure of the output voltage distortion in a fundamental period. This information is obtained at a lower computational cost than conventional fast Fourier transform (FFT) analysis. The accuracy of the HD/sub n/ distortion predictions is verified by comparing it to FFT-based results obtained from simulation and experiments. The expression to compute the total harmonic distortion (THD) as a function of HD/sub n/ is also derived.     

Considering the alternatives in low-power design

The authors discuss employing alternative number systems to reduce power dissipation in portable devices and high-performance systems. They focus on two alternative number systems that are quite different from the conventional linear number representations, namely the logarithmic number system (LNS) and the residue number system (RNS). Both have recently attracted the interest of researchers for their low-power properties. The authors address aspects of the conventional arithmetic representations, the impact of logarithmic arithmetic on power dissipation, and discuss the low-power aspects of residue arithmetic     

Harmonic optimization of multilevel converters using genetic algorithms

In this letter, a genetic algorithm (GA) optimization technique is applied to determine the switching angles for a cascaded multilevel inverter which eliminates specified higher order harmonics while maintaining the required fundamental voltage. This technique can be applied to multilevel inverters with any number of levels. As an example, in this paper a seven-level inverter is considered, and the optimum switching angles are calculated offline to eliminate the fifth and seventh harmonics. These angles are then used in an experimental setup to validate the results.     

CMOS charge-transfer preamplifier for offset-fluctuationcancellation in low-power A/D converters

We have developed a low-power, high-accuracy comparator composed of a dynamic latch and a CMOS charge transfer preamplifier (CT preamplifier). The CT preamplifier amplifies the input signal with no static power dissipation, and the operation is almost insensitive to the device parameter fluctuations. The low-power and high-accuracy comparator has been realized by combining the CT preamplifier with a dynamic latch circuit. The fluctuation in the offset voltage of a dynamic latch is reduced by a factor of the preamplifier gain. A 4-bit flash A/D converter circuit has been designed and fabricated by 0.6-μm CMOS process. Low differential nonlinearity of less than ±4 mV has been verified by the measurements on test circuits, showing 8-bit resolution capability. Very low power operation at 4.3 μW per MS/s per comparator has also been achieved     

Technology for the design of low-power circuits

Operation of integrated circuits at micropower levels requires transistors with adequate current gain at collector currents of 1 /spl mu/A and less and resistors of the order of 1 M/spl Omega/ within reasonable areas. Factors affecting current gain at low currents are discussed and design criteria presented that optimize gain at low collector current. A benefit of micropower operation is low-current noise. Factors tending to optimize noise performance are discussed. In order to obtain voltage gain at low collector current, high values of load resistance are required. Both passive and active loads suitable for incorporation in micropower integrated circuits are discussed.     

嵌入式系统中微控制器低功耗设计的实现

文章介绍了微控制器中的新的低功耗技术--深度睡眠模式,同时也介绍了产生功率消耗的因素,讨论如何配置微控制器以在嵌入式系统中实现超低功耗的设计。     

Process-insensitive low-power design of switched-capacitor integrators

A generalized analytical technique is developed to design power optimized switched-capacitor integrators taking process variations into account. It is shown that the performance of a robustly designed power optimum switched-capacitor integrator is a monotonic function of the slew rate and the transconductance of the amplifier. The framework provides an analytical solution for fabrication foundry independent analog design and therefore eliminates the need for Monte Carlo simulations to estimate the effect of the worst-case performance variations. With this analytical approach, it is possible to migrate the design to technologies with smaller feature sizes while obtaining monotonic improvement in the performance. The validity of the proposed analytical model for the design of robust switched-capacitor integrators is demonstrated through transistor-level SPICE simulations using BSIM3v3 models.     

低功耗水下探测器设计

水下探测器是海洋环境监测的重要设备,为解决传统水下无人探测器续航能力弱等问题,设计了一种新型的低功耗水下探测器。其采用新型集成式传感器,降低了传感器电路的功耗;具备多功能扩展接口,可搭载其它传感器或推进装置;搭载的能量采集模块用来获取探测器周边环境能量,可提高探测器的续航能力;主控电路采用了低功耗设计,可对不同传感器及功能模块进行单独控制,精准调控电路系统的功耗,优化供电逻辑,大大提高探测器的集成度和续航能力。     

STATCOM based on multimodules of multilevel converters undermultiple regulation feedback control

This paper describes a STATCOM based on diode-damped multilevel power converters. The current rating is increased by parallel connections of multiple power converter modules. The gate-turn-off thyristor (GTO) switching angles of the fundamental switching strategy are exploited in the design to accomplish three objectives: (1) low total harmonic distortion (THD) in voltages and currents; (2) equal sharing of the currents in the individual modules; and (3) direct control of AC voltage magnitude. Three proportional-integral (PI) feedback loops are employed for the purposes of: (1) regulating the total DC voltages and ensuring the quadrature relationship of the AC currents and voltages; (2) regulating the reactive power drawn by the STATCOM; and (3) equalizing the DC capacitor voltages in all the levels     

Instruction buffering for nested loops in low-power design

Several loop-buffering techniques were proposed for reducing power consumption of embedded processors. Although the schemes are effective in reducing power, they work for unnested loops (or the inner-most loop in nested loops) only. In this paper, we propose a stack-based controller which can handle sequential loops being nested in a loop of all styles and the if-then-else construct inside of a loop. Our experiments by power estimator Wattch show that the reduction in energy consumption using our technique is up to 36% improvement of the design without buffering technique and has 25% more improvement when compared to the results which handle inner-most loop only at the fetch and decode stages.     

Power loss-oriented evaluation of high voltage IGBTs and multilevel converters in transformerless traction applications

The low-frequency line transformer in todays ac rail vehicles suffers from poor efficiency and a substantial weight. Future traction drives may operate directly from the mains without this transformer. A feasible concept for a transformerless drive system consists of series connected medium voltage converters applying modern high-voltage insulated gate bipolar transistors (HV-IGBTs). In a first design step, the switching characteristics and losses of 6.5-kV IGBTs are compared to 3.3-kV and 4.5-kV IGBTs which are already commercially used in traction applications. Based on the considered HV-IGBTs, the properties of multilevel converters are analyzed and their applicability to the transformerless system is evaluated. The paper focusses on a loss analysis of the converters. Reliability aspects and harmonic spectra are briefly discussed. Taking these design aspects into account, the three-level neutral point clamped converter turns out to be a reasonable solution to realize line and motor converter modules in a transformerless traction system.     

Optimum harmonic reduction with a wide range of modulation indexes for multilevel converters

This paper proposes a novel modulation technique to be applied to multilevel voltage-source converters suitable for high-voltage power supplies and flexible AC transmission system devices. The proposed technique can generate output stepped waveforms with a wide range of modulation indexes and minimized total voltage harmonic distortion. The main power devices switch only once per cycle, as is suitable for high-power applications. In addition to meeting the minimum turn-on and turn-off time requirements for high-power semiconductor switches, the proposed technique excludes from the synthesized waveform any pulses that are either too narrow or too wide. By using a systematic method, only the polarities and the number of levels need to be determined for different modulation levels. To verify the theory and the simulation results, a cascaded converter-based hardware prototype, including an 8-b microcontroller as well as modularized power stage and gate driver circuits, is implemented. Experimental results indicate that the proposed technique is effective for the reduction of harmonics in multilevel converters, and both the theoretical and simulation results are well validated.     

A low-power ASIC design for cell search in the W-CDMA system

This paper presents a low-power ASIC design for cell search in the wideband code-division multiple-access (W-CDMA) system. A low-complexity algorithm that is able to work satisfactorily under the effect of large frequency and clock errors is designed first. Then, a set of low-power measures are employed in the design of hardware architecture and circuits. Finally, through power analysis, critical blocks are identified and redesigned so as to further reduce the power consumption. The final design shows that the power is reduced by 51% from the original design of 133.6 mW to 65.49 mW, and its core area is also reduced by 31.9% from 3.4/spl times/3.4 mm/sup 2/ to 2.8/spl times/2.8 mm/sup 2/. The design is implemented and verified in a 3.3-V 0.35-/spl mu/m CMOS technology with clock rate 15.36 MHz.     

新型半静态低功耗D触发器设计

本文从简化触发器内部锁存器结构以降低功耗的要求出发，提出了一种新型的半静态D触发器设计。PSPICE模拟表明，新设计逻辑功能正确。与以往一些设计相比，新设计在功耗和速度上获得显著改进。     

The design of sigma-delta modulation analog-to-digital converters

The author examines the practical design criteria for implementing oversampled analog/digital converters based on second-order sigma-delta (ΣΔ) modulation. Behavioral models that include representation of various circuit impairments are established for each of the functional building blocks comprising a second-order Σ2gD modulator. Extensive simulations based on these models are then used to establish the major design criteria for each of the building blocks. As an example, these criteria are applied to the design of a modulator that has been integrated in a 3-μm CMOS technology. An experimental prototype operates from a single 5-V supply, dissipates 12 mW, occupies an area of 0.77 mm², and has achieved a measured dynamic range of 89 dB     

The design and implementation of a low-power clock-poweredmicroprocessor

We describe the design and implementation of a 16-bit clock-powered microprocessor that dissipates only 2.9 mW at 15.8 MHz based on laboratory measurements. Clock-powered logic (CPL) has been developed as a new approach for designing and building low-power VLSI systems that exploit the benefits of supply-voltage-scaled static CMOS and energy-recovery CMOS techniques. In CPL, the clock signals are a source of ac power for the other large on-chip capacitive loads. Clock amplitude and waveform shape combine to reduce power. By exploiting energy recovery and an energy-conserving clock driver, it is possible to build ultra-low-power CMOS processors with this approach. We compare the CPL approach with a conventional, fully dissipative approach for a processor with a similar ISA and VLSI architecture which was designed using the same set of VLSI CAD tools. The simulation results indicate that the CPL microprocessor would dissipate 40% less power than the conventional design