1.8 V–3 GHz CMOS limiting amplifier with efficient frequency compensation

A compact robust CMOS limiting amplifier (LA) for high data traffic optical links is presented in this work. The core considers two different blocks. First, four common-source inverter amplifiers are included, which optimize the gain-bandwidth product of the structure. And second, two additional compensation stages are placed strategically between the gain stages alleviating the pernicious load effect. These stages develop two different compensation techniques simultaneously thus increasing the bandwidth. The proposed design consumes 113 mW with a single 1.8 V supply. It achieves a cut-off frequency up to 3 GHz and provides a gain of 21 dB. The circuit is packaged in a QFN24 and mounted on a commercial FR4 PCB.     

A calibrated direct conversion front-end transmitter with resonant matching techniques for mobile WiMAX/WiBro applications

A direct conversion front-end transmitter with the properties of high linearity and high single sideband rejection ratio is described in this paper. The transmitter employs two resonant matching techniques to improve its operating bandwidth. The first resonant circuit design is applied at the inter-stage of the LO input buffer in order to achieve a wideband frequency response which ranges from dc to 6 GHz. The second resonant circuit is applied at the power amplifier (PA) driver output stage to increase the matching bandwidth and meet both the Worldwide Interoperability for Microwave Access (WiMAX) and Wireless Broadband (WiBro) applications simultaneously. In addition, the sideband signal and carrier leakage of this transmitter are further minimized by a proposed calibration circuit design to achieve the error vector magnitude (EVM) specifications. The measured single sideband performance with calibration mechanism demonstrates approximately 15 dB improvement on sideband and carrier suppression. The rejected sideband and carrier signals can be up to 55.19 and 56.31 dBc, respectively. The measured dynamic gain range of the transmitter is 53 dB in 1-dB step with a maximum relative gain error lower than 0.4 dB. The transmitter delivers +0.766 dBm output power with EVM of −34.687 dB for the orthogonal frequency division multiple access (OFDMA) 64QAM-3/4 modulated signals. The measured constellation is minimized to be <1.5% with output power from −2.3 to −36.2 dBm.     

Design of variable gain low noise amplifier using feedback circuit with memory circuits for 5.2 GHz band

This paper presents a novel adaptive gain control method for Low Noise Amplifiers (LNAs) at the 5.2 GHz band using a feedback circuit, and operating in the baseband signal frequency. A uniform step variable gain can be implemented using a two-stage LNA based on the cascade topology. The feedback circuit consists of seven functional blocks, each of which has been designed for minimum power consumption. The storage circuit in the feedback circuit is used to store the previous signal magnitude, thus avoiding unnecessary power consumption in the LNA. We simulated the performances of LNA in terms of the gain, IIP3, Noise Figure (NF), stability, and power consumption. The adaptive front-end LNA with the feedback circuit can achieve a variable gain from 11.39 dB to 22.74 dB with excellent noise performance even at a high gain mode. The DC power of the proposed variable gain LNA consumes 5.68–6.75 mW under a 1.8 V supply voltage.     

Area-efficient CMOS transimpedance amplifier for optical receivers

In this letter, a broadband area-efficient transimpedance amplifier (TIA) for optical receivers is designed using a standard 0.18 μm CMOS technology. A new shunt–shunt peaking technique is used at the input transimpedance stage, which is followed by a gain stage and a capacitive degeneration stage. The amplifier achieves a wide bandwidth with only one inductor; hence a smaller silicon area is maintained. The proposed TIA has a measured transimpedance gain of 50 dB Ohm and a −3 dB bandwidth of 6.5 GHz for 0.25 pF input photodiode capacitance. It consumes DC power of 14 mW from a 1.8 V supply voltage and occupies only 0.09 mm² silicon area.     

60 GHz amplifier employing slow-wave transmission lines in 65-nm CMOS

A three-stage V-band amplifier implemented in 65-nm baseline CMOS technology is presented in this paper. Slow-wave coplanar waveguides are used for matching and interconnects to study the benefits of using this line type in amplifier design. Measured power gain, noise figure and 1 dB output compression point at 60 GHz are 13 dB, 6.3 dB and +4 dBm, respectively. The amplifier has 19.6 GHz of 3 dB bandwidth, thus covering entirely the unlicensed band around 60 GHz. The performance is achieved with a 1.2 V supply and 45 mA DC current consumption.     

A 0.5-V 90-dB SNDR 102 dB-SFDR audio-band continuous-time delta–sigma modulator

A 0.5-V high performance continuous-time one-bit delta–sigma modulator is reported for audio applications. High performance under this ultra-low supply is achieved by a feed-forward modulator architecture for reduced integrator swing, a special switched-capacitor-resistor feedback for less sensitivity to jitter noise, and a fast-settling fully differential amplifier. The synthesized modulator also has a high thermal-noise-limited SNR of 91 dB over a 20 kHz bandwidth. The 0.5-V fully-differential gate-input amplifier employs an adaptive common-mode feedback frequency compensation circuit, which leads to a robust modulator performance against process, supply voltage and temperature variations. Fabricated in a standard 0.13 μm CMOS process, the modulator achieves a spurious-free dynamic range (SFDR) of 101.9 dB and a signal-to-noise plus distortion ratio (SNDR) of 90 dB (A-weighted) over a 20-kHz signal bandwidth, with the latter being very close to the thermal noise limit. The modulator operates over a supply range from 0.4 to 0.75 V and a temperature range from −20 to 90°C.     

Design issues of a low power wideband frequency doubler implementation in 0.18 μm CMOS

This paper presents design issues of a wideband, low power implementation of a frequency doubler (FD) in a commercial 0.18 μm CMOS process. The FD consists of two identical unbalanced source-coupled pairs with different width-to-length (W/L) ratios, whose inputs are connected in parallel and its output is taken single-ended. Amplitude and phase mismatch at the differential input are considered and it is shown that there is minimal effect on the output amplitude of the 2nd harmonic for a 5 dB difference in input amplitude and a 45° difference in phase. Under matched conditions, the implemented frequency doubler can be operated at a supply voltage as low as 1 V, which corresponded to a power consumption of less than 1 mW, has a 3 dB output bandwidth of 4 GHz and a conversion gain of 2.5 dB. At a supply voltage of 1.2 V, the frequency doubler consumed 1.32 mW, has a 3 dB output bandwidth of 3 GHz and a conversion gain of 5 dB. The phase niose degradation is 6 dB in both cases.     

A linear ultra wide band low noise amplifier using pre-distortion technique

This paper presents an Ultra Wide-Band (UWB) high linear low noise amplifier. The linearity of Common Gate (CG) structure is improved based on pre-distortion technique. An auxiliary transistor is used at the input to sink the nonlinear terms of source current, resulting linearity improvement. Furthermore, an inductor is used in the gate of the main amplifying transistor, which efficiently improves gain, input matching and noise performance at higher frequencies. Detailed mathematical analysis show the effectiveness of both linearity improvement and bandwidth extension techniques. Post-layout simulation results of the proposed LNA in TSMC 0.18 µm RF-CMOS process show a gain of 13.7 dB with −3 dB bandwidth of 0.8–10.4 GHz and minimum noise figure (NF) of 3 dB. Input Third Intercept Point (IIP3) of 10.3–13 dBm is achieved which shows 8 dB improvement compared to conventional common gate structure. The core circuit occupies an area of 0.19 mm² including bond pads, while consuming 4 mA from a 1.8-V supply.     

A novel ±0.5 V,high current drive,and rail to rail current operational amplifier

A current operational amplifier (COA) with very high current drive capability is presented in this paper. The principle of operation of this unique structure is discussed, its most important formulas are derived and its outstanding performance is verified by HSPICE simulation in TSMC 0.18 μm CMOS, BSIM3, and Level49 technology. Owing to the elaborately arranged components, the proposed circuit demonstrates very high frequency bandwidth, extremely high CMRR, high output impedance, and true rail to rail output voltage swing range while operating at very low power supply of ±0.5 V. The interesting results such as current drive capability of ±1 mA, high output impedance of 5 GΩ, wide gain bandwidth of 220 MHz, extremely high output voltage swing of ±0.45 V, which interestingly provides the highest yet reported output voltage compliance for current mode building blocks implemented by regular CMOS technology, low static power consumption of 159 μW, and very high CMRR of 155 dB is achieved utilizing standard CMOS technology. Full process, voltage, and temperature variation analysis of the circuit is also investigated in order to approve the well robustness of the structure. The transient stepwise and sinusoidal response analysis is also done to verify the proposed COA stability.     

Parametric Simulation and Optimization of Cold-test Properties for a 220 GHz Broadband Folded Waveguide Traveling-wave Tube

Characterized with full-metal structure, high output power and broad bandwidth, microfabricated folded waveguide is considered as a robust slow-wave structure for millimeter wave traveling-wave tubes. In this paper, cold-test (without considering the real electron beam) properties were studied and optimized by 3D simulation on slow-wave structure, for designing a 220 GHz folded waveguide traveling-wave tube. The parametric analysis on cold-test properties, i.e., phase velocity, beam-wave interaction impedance and cold circuit attenuation, were conducted in half-period circuit with high frequency structure simulator, assisted by analytical model and equivalent circuit model. Through detailed parametric analyses, interference between specified structural parameters is found on determining beam-wave interaction impedance. A discretized matrix optimization for interaction impedance was effectively carried out to overcome the interference. A range of structural parameters with optimized interaction impedance distributions were obtained. Based on the optimized results, a broadband folded waveguide with cold pass-band of about 80 GHz, flat phase velocity dispersion and fairly high interaction impedance was designed for a 220 GHz central frequency traveling-wave tube. A three-dB bandwidth of 20.5 GHz and a maximum gain of 21.2 dB were predicted by small signal analysis for a 28 mm-long lossy circuit.     

A 24-dB Ku-band low-power linearized 90-nm amplifier with a built-in output buffer

In this paper, we present a 90-nm high gain (24 dB) linearized CMOS amplifier suitable for applications requiring high degree of port isolation in the K_u-band (13.2–15.4 GHz). The two-stage design is composed of a low-noise common-gate stage and a gain-boosting cascode block with an integrated output buffer for measurement. Optimization of input stage and load-port buffer parameters improves the front-end's linear coverage, port return-loss, and overall gain without burdening its power demand and noise contribution. With low gate bias voltages (0.65–1.2 V) and an active current source, <?10 dB port reflection loss and 3.25–3.41 dB NF are achieved over the bandwidth. The input reflection loss of the overall amplifier lies between ?35 and ?10 dB and the circuit demonstrates a peak forward gain of 24 dB at 14.2 GHz. The output buffer improves the amplifier's forward gain by ～9 dB and pushes down the minimum output return loss to ?22.5 dB while raising the front-end NF by only 0.05 dB. The effect of layout parasites is considered in detail in the 90-nm process models for accurate RF analysis. Monte Carlo simulation predicts 9% and 8% variation in gain and noise figures resulting from a 10% mismatch in process. The K_u-band amplifier including the buffer block consumes 7.69 mA from a 1.2-V supply. The proposed circuit techniques achieve superior small signal gain, GHz-per-milliwatt, and range of linearity when compared with simulated results of reported microwave amplifiers.     

A low supply voltage SiGe LNA for ultra-wideband frontends

A low-power low-noise amplifier (LNA) for ultra-wideband (UWB) radio systems is presented. The microwave monolithic integrated circuit (MMIC) has been fabricated using a commercial 0.25-/spl mu/m silicon-germanium (SiGe) bipolar CMOS (BiCMOS) technology. The amplifier uses peaking and feedback techniques to optimize its gain, bandwidth and impedance matching. It operates from 3.4 to 6.9GHz, which corresponds with the low end of the available UWB radio spectrum. The LNA has a peak gain of 10dB and a noise figure less than 5dB over the entire bandwidth. The circuit consumes only 3.5mW using a 1-V supply voltage. A figure of merit (FoM) for LNAs considering bandwidth, gain, noise, power consumption, and technology is proposed. The realized LNA circuit is compared with other recently published low-power LNA designs and shows the highest reported FoM.     

Asymmetric and symmetric modified bow-tie slotted circular patch antennas for circular polarization

Modern communication systems employ wideband antennas with circular polarization (CP) radiation. In this work, asymmetric modified bow-tie (ABT) and symmetric modified bow-tie (SBT) slotted circularly polarized single-point probe-fed circular patch antennas with dimensions of 40 mm × 40 mm for wideband applications are proposed. A 10 dB RL bandwidth of 350 MHz with CP, 3 dB axial ratio (AR) bandwidth of 100 MHz, peak gain of 4.9 dBic, and 10 dB RL bandwidth of 530 MHz with CP, 3 dB AR bandwidth of 140 MHz, peak gain of 5 dBic are obtained for ABT and SBT slotted circular patch antennas, respectively. The proposed SBT slotted patch is scaled up and down to 50 mm × 50 mm and 30 mm × 30 mm, respectively. The proposed scaled-up version offers 10 dB RL and 3 dB AR bandwidths of 340 MHz and 80 MHz, with a peak gain of 5 dBic. The scaled-down version offers 10 dB RL and 3 dB AR bandwidths of 710 MHz and 180 MHz, with a peak gain of 5.25 dBic. These prototypes are suitable to work in IEEE 802.11a WLAN, ISM, and IEEE 802.11ac applications. The measured and simulated results are then discussed and compared.     

Low noise accelerometer microsystem with highly configurable capacitive interface

This paper presents a low noise accelerometer microsystem with a highly configurable capacitive interface circuit. A programmable capacitive readout circuit is designed to minimize the offset and gain error due to the parasitic capacitance mismatch and the process variations. The interface circuit is implemented in a 0.5 μm 2P3M CMOS technology with EEPROM. The interface circuit and MEMS sensing element are integrated in a single package, and consist the accelerometer microsystem. The supply voltage and supply current of the system are 5 V and 1.17 mA, respectively. The input range and gain are 2.5 V and 0.5 V/g, respectively. The max–min gain error and max–min offset error after calibration was measured to be 1.2% FSO and 3.3% FSO, respectively. The signal to noise ratio (SNR) and noise equivalent resolution (NER) are measured to be 93.1 dB and 110.6 μg/√Hz, respectively, when a 40 Hz, 5 g sinusoidal input acceleration is applied.     

Design and Simulation of a Ka-Band TE<Subscript>11</Subscript> Mode Gyro-Traveling-Wave Amplifier

The design of a Ka-band gyrotron traveling wave amplifier with high power and wide bandwidth is presented in detail. The amplifier operates in the TE11 circular mode at the fundamental cyclotron harmonic. The distributed loss technique is adopted in the interaction circuit which guarantees the amplifier zero-drive stability. The effects of the parameters such as input power, driver frequency and magnetic field on the performance of the gyro-TWT are discussed. The simulation results show that the gain and the 3dB bandwidth of the designed Ka-band gyro-TWT are about 56.0dB and 1.8 GHz ,respectively. The peak output power and the corresponding electronic efficiency are about 100 kW and 23.8% respectively with the voltage 70 kV and the current 6A at the velocity ratio 1.0.     

2～20GHz分布式单片放大器设计

介绍了一种采用0.15μm GaAs PHEMT工艺设计加工的2～20 GHz宽带单片放大器,为了提高电路的整体增益和带宽,在设计电路时采用两级级联分布式结构。此种电路结构不仅能够增加整体电路的增益和带宽,还可以提高电路的反向隔离,获得更低的噪声系数。利用Agilent ADS仿真设计软件对整体电路的原理图和版图进行仿真优化设计。后期电路在中国电子科技集团公司第十三研究所砷化镓工艺线上加工完成。电路性能指标:在2～20 GHz工作频率范围内,小信号增益>13.5 dB;输入输出回波损耗<-9 dB;噪声系数<4.0 dB;P-1>13 dBm。放大器的工作电压5 V,功耗400 mW,芯片面积为3.00 mm×1.6 mm。     

一种具有温度补偿的宽带CMOS可变增益放大器

设计实现了一个具有温度补偿的宽带CMOS可变增益放大器,该可变增益放大器的核心电路由三级基于改进型Cherry-Hooper结构的可变增益单元级联而成,并通过一种温度系数增强的且可编程的偏置电路和增益控制电路对可变增益放大器的增益进行温度补偿。采用中芯国际0.13μm CMOS工艺流片,测试结果表明可变增益放大器的可变增益范围为-13～27dB,经过温度补偿后,在相同增益控制电压下其增益在0～75°C温度范围内的变化范围不超过3dB。可变增益放大器的3dB带宽为0.8～3GHz,输入1dB压缩点为-50～-21dBm,在1.2V电压下,功耗为21.6mW。     

Efficient biasing circuit strategies for inductorless wideband low noise amplifiers with feedback

This paper presents a comparative study among different biasing circuits of inductorless low-area Low Noise Amplifier (LNAs) with feedback. This study intends to determine the most suitable biasing circuit to achieve the best LNA performance for wideband applications. The main performance metrics are analyzed and a comparison is carried out based on electrical simulations. To this purpose, two different CMOS technology processes are considered: 130 nm and 90 nm. In both cases, the supply voltage is 1.2 V. The best LNA designed in 130 nm achieves a bandwidth of 2.94 GHz with a flat voltage gain (A_v) of 16.5 dB and a power consumption of 3.2 mW. The same LNA topology designed in 90 nm technology has a bandwidth of 11.2 GHz, featuring a voltage gain of 16.6 dB and consuming 1.9 mW. Both LNAs are input-impedance matched and have a noise figure below 2.4 dB measured at 2.4 GHz. As a case study, the layout of the best-performance LNA circuit has been implemented in a 130 nm technology, achieving an area of 0.012 mm², which is near the size of a pad or an inductor. It is demonstrated that the bandwidth of this circuit can be notably increased by simply adding a small inductance in the feedback path.¹     

An LP/CBP reconfigurable analog baseband circuit for software-defined radio receivers in 65 nm CMOS

A low pass (LP) and complex band pass (CBP) reconfigurable analog baseband circuit for software-defined radio (SDR) receivers is presented. It achieves 1–15 MHz LP bandwidth, 2–8 MHz CBP bandwidth and 0–36 dB gain range with 1 dB step. Nulling-resistor Miller feed-forward (NRMFF) differential-mode compensation, passive left half-plane (LHP) zero common-mode compensation and Quasi-Floating Gate (QFG) technique are proposed to improve the high frequency performance and driving capability of the embedded fully differential operational amplifier (Op-Amp). The analog baseband circuit has been implemented in 65 nm CMOS. It achieves 15.2 dB m/27.1 dB m IB/OB-IIP3, −2 dB m IP1dB and 71 dB m IIP2 while consuming 3.6–9.1 mW from a 1.2 V power supply and 0.75 mm² chip area.     

High-drive CMOS current amplifier

A high-performance current amplifier is proposed which is based on a folded-cascode transresistance amplifier and a low-distortion class AB current output stage. The loop gain of the transresistance amplifier exhibits a gain bandwidth product of 10 MHz and a DC gain as high as 100 dB which allows accurate closed-loop operations to be achieved. Despite the intrinsic low-linearity performance of current amplifiers with respect to their voltage amplifier counterpart, the proposed circuit provides an output current of 7 mA with a total harmonic distortion (THD) better than -55 dB while requiring only 200 μA of quiescent current for the output transistors. The circuit was fabricated in a 1.2 μm CMOS process, uses a 5 V power supply, and dissipates 4 mW