A 470 μA direct readout circuit for electret and MEMS digital microphones

A direct readout circuit configurable for electret or MEMS digital microphones is presented. The circuit includes a transducer buffer, a programmable preamplifier, a ΣΔ modulator, a bandgap reference, a clock detection circuit, and a stability recovery system. The prototype achieves a signal-to-noise-and distortion of 63 dB A-weighted at 1 Pa sound level with a consumption of 470 μA at 1.8 V supply voltage. The active area is 0.72 mm² in a 0.25 μm CMOS process with MIM capacitor option.     

On the design of feed-forward ΣΔ interface for MEMS based accelerometers

High order ???? interface is popular for high resolution micro-electro-mechanical systems. Previous researches are mainly about the coefficients of the multiple feedback electromechanical ???? modulators. In the work presented here, a systematic design method for the feed forward ???? interfaces is proposed. Simulations show that utilizing the proposed method, feed forward and the optimized multiple feedback electromechanical sigma-delta modulators have almost the same SQNRs when a compensator pole is added to the feed forward structure. However, the feed forward structures have many advantages, so the proposed method is a promising alternative method for the multiple feedback structure.     

Highly configurable capacitive interface circuit for tri‐axial MEMS microaccelerometer

A highly configurable capacitive interface circuit with on‐chip calibration capability for tri‐axial microaccelerometer is presented. The capacitive interface circuit is designed to be programmable, and can reduce the output errors due to the parasitic capacitance variations and process variations. The capacitive sensing chain adopts the chopper stabilisation, and includes the front‐end charge amplifier with three 10‐bit programmable capacitor arrays, 9‐bit digital‐to‐analogue converter and 10‐bit programmable gain amplifier. The calibration coefficients are stored to the on‐chip erasable programmable read only memory. The outputs from the three‐channel capacitive sensing chain are converted to digital signal by the integrated 14‐bit algorithmic analogue‐to‐digital converter. After calibrating the 48 samples, all the samples meet the desired specification range. Before the calibration, the errors of the average values of the output offset and gain were +47.1% and ?85.9%, respectively. After the calibration, however, the errors of the average values of the output offset and gain are reduced to be 0.3% and 0.5%, respectively. The resolutions for x/y‐axis and z‐axis are measured to be 326 and 728?µg, respectively.     

A 540-μW digital pre-amplifier with 88-dB dynamic range for electret microphones

We design a digital pre-amplifier which can be directly connected to an electret microphone. The amplifier can convert analog signals into digital signals, has a wide voltage swing and low power consumption, as is required in portable applications. Measurement results show that the dynamic range of the digital pre-amplifier reaches 88 dB, the equivalent input referred noise is 5 μVrms, the typical power consumption is 540 μW, and in standby mode the current does not exceed 10 μA. Compared with an analog microphone, an electret microphone with digital pre-amplifier offers a better SNR, higher integration, lower power consumption, and higher immunity to system noise.     

A 540-μW digital pre-amplifier with 88-dB dynamic range for electret microphones

We design a digital pre-amplifier which can be directly connected to an electret microphone.The amplifier can convert analog signals into digital signals,has a wide voltage swing and low power consumption,as is required in portable applications.Measurement results show that the dynamic range of the digital pre-amplifier reaches 88dB,the equivalent input referred noise is 5μVrms,the typical power consumption is 540μW,and in standby mode the current does not exceed 10μA.Compared with an analog microphone,an e...     

An A/D interface based on ΣΔ modulator for thermal vacuum sensor ASICs

A new Σ Δ modulator architecture for thermal vacuum sensor ASICs is proposed. The micro-hotplate thermal vacuum sensor fabricated by surface-micromachining technology can detect the gas pressure from 1 to 10⁵ Pa. The amplified differential output voltage signal of the sensor feeds to the Σ Δ modulator to be converted into digital domain. The presented Σ Δ modulator makes use of a feed-forward path to suppress the harmonic distortions and attain high linearity. Compared with other feed-forward architectures presented before, the circuit complexity, chip area and power dissipation of the proposed architecture are significantly decreased. The correlated double sampling technique is introduced in the 1st integrator to reduce the flicker noise. The measurement results demonstrate that the modulator achieves an SNDR of 79.7 dB and a DR of 80 dB over a bandwidth of 7.8 kHz at a sampling rate of 4 MHz. The circuit has been fabricated in a 0.5 μ m 2P3M standard CMOS technology. It occupies an area of 5 mm² and dissipates 9 mW from a single 3 V power supply. The performance of the modulator meets the requirements of the considered application.     

A 5th-order ΣΔ modulator with combination of op-Amp and CBSC circuit for ADSL applications

In this letter, a 5th-Order single-loop low distortion Sigma–Delta Modulator (SDM) is implemented with the combination of the comparator-based switched-capacitor (CBSC)-based and op-amp-based techniques for asymmetric digital subscriber line (ADSL) applications. This structure, which uses integrator (CBSC-based) and IIR filter (op-amp-based) concurrently, has relatively fewer feed-forward paths and modulator coefficients for sensitivity reduction to mismatch. To lower the power consumption of the modulator, the integrators are implemented with CBSC, the IIR filter block is implemented by single OTA, and a passive adder is used to realize the adder at the input of the 5-bit quantizer. The design purpose is minimizing the power consumption while the dynamic performance maintains high. As shown in the simulation result, for a 2-MHz signal bandwidth, the modulator achieves a dynamic range (DR) of 86.5 dB and a peak signal-to-noise and distortion ratio (SNDR) of 85 dB with an oversampling ratio of 8. In addition it consumes 18.75 mW from a 1.8-V power supply at 32 MS/s, which obtains a figure of merit of 1.6e−3.     

A 70-MHz Continuous-Time CMOS Band-Pass ΣΔ Modulator for GSM Receivers

A 70-MHz continuous-time CMOS band-pass modulator for GSM receivers is presented. Impulse-invariant-transformation is used to transform a discrete-time loop-filter transfer function into continuous-time. The continuous-time loop-filter is implemented using a transconductor-capacitor (G _m -C) filter. A latched-type comparator and a true-single-phase-clock (TSPC) D flip-flop are used as the quantizer of the modulator. Implemented in a MOSIS HP 0.5-m CMOS technology, the chip area is 857 m × 420 m, and the total power consumption is 39 mW. At a supply voltage of 2.5 V, the maximum SNDR is measured to be 42 dB, which corresponds to a resolution of 7 bits.     

A sigma–delta interface ASIC for force-feedback micromachined capacitive accelerometer

A single-loop fourth-order sigma?Cdelta (????) interface circuit for micromachined accelerometer is presented in this study. Two additional electronic integrators are cascaded with the micromachine sensing element to form a fourth-order loop filter to eliminate quantization noise. A precise model for the overall system is set up based on nonlinear model of 1-bit quantizer. Three main noise sources affecting the overall system resolution of a ???? accelerometer: mechanical noise, electronic noise and quantization noise are analyzed in more detail. A switched-capacitor charge integrator and correlated double sampling are applied to reduce input-referred electronic noise. The ASIC is fabricated in 0.5???m two-metal two-poly n-well CMOS process, and test results show that the noise density floors of the open-loop and closed-loop modes are 12 and 80???g/Hz^1/2, respectively, the sensitivity is 1.25?V/g, the full measurement range can be achieved from ?2 to +2?g, and the power dissipation is 40?mW.     

1.1 V Low-Power ΣΔ Modulator for 14-bit, 16 KHz A/D Conversion Using a New Low-Voltage Class-AB Op-amp

This paper presents the implementation of a second order modulator for a 1.1 V supply voltage. A new class-AB CMOS operational amplifier has been designed in order to achieve high-resolution under very-low-voltage operation. The modulator has been implemented using a 0.35 m CMOS technology with 0.65 V transistor threshold voltage. Experimental results show 14 bits of resolution over 16 kHz nyquist rate with an oversampling ratio of 160.Fernando Muñoz Chavero was born in El Saucejo, Sevilla, Spain. He received the Telecommunications Engineering and Ph.D. degrees from the University of Seville, Seville, Spain, in 1998 and 2002, respectively. Since 1997, he has been with the Department of Electronic Engineering, School of Engineering, University of Seville, where he has been an Associate Professor (1999). His research interests are related to low-voltage low-power analog circuit design, A/D and D/A conversion, and analog and mixed signal processing.Alfredo Pérez Vega-Leal was born in Seville, Spain. He received the Telecommunications Engineering and Ph.D. degrees from the University of Seville, Seville, Spain, in 1998 and 2003, respectively. Since 1995, he has been with the Department of Electronic Engineering, School of Engineering, University of Seville, as research student and became an Associate Professor in 1999. His research interests are related to low-voltage low-power analog circuit design, A/D and D/A conversion.Ramón González Carvajal was born in Seville, Spain. He received the Electrical Engineering and Ph.D. degrees from the University of Seville, Seville, Spain, in 1995 and 1999, respectively. Since 1996, he has been with the Department of Electronic Engineering, School of Engineering, University of Seville, where he has been an Associate Professor (1996), and Professor (2002). He has published more than 100 papers in International Journals and Conferences. His research interests are related to low-voltage low-power analog circuit design, A/D and D/A conversion, and analog and mixed signal processing.Antonio Torralba was born in Seville, Spain. He received the electrical engineering and Ph.D. degrees from the University of Seville, Seville, Spain, in 1983 and 1985, respectively. Since 1983, he has been with the Department of Electronic Engineering, School of Engineering, University of Seville, where he has been an Assistant professor, Associate Professor (1987), and Professor (1996). He has published 30 papers in journals and more than 80 papers in conferences. His research interests are in the design and modeling of low-voltage analog circuits, analog and mixed-signal design, analog to digital conversion, and electronic circuits and systems with application to control and communication.Jonathan Noel Tombs was born in Oxford, UK. He received the Electrical Engineering and Ph.D. degrees from Oxford University, UK, in 1987 and 1991, respectively. Since 1993, he has been with the Department of Electronic Engineering, School of Engineering, University of Seville, where he has been an Associate Professor (1997), and Professor (2002). He has published more than 50 papers in International Journals and Conferences. His research interests are related to Digital Design and system verification with VHDL, low-voltage low-power analog circuit design, A/D and D/A conversion and analog and mixed signal processing.Jaime Ramírez-Angulo is currently Klipsch Distinguished Professor, IEEE fellow and Director of the Mixed-Signal VLSI lab at the Klipsch School of Electrical and Computer Engineering, New Mexico State University (Las Cruces, New Mexico), USA. He received a degree in Communications and Electronic Engineering (Professional degree), a M.S.E.E. from the National Polytechnic Institute in Mexico City and a Dr.-Ing. degree form the University of Stuttgart in Stuttgart, Germany in 1974, 1976 and 1982 respectively. He was professor at the National Institute for Astrophysics Optics and Electronics (INAOE) and at Texas A&M University. His research is related to various aspects of design and test of analog and mixed-signal Very Large Scale Integrated Circuits.     

A feed-forward AGC circuit with 48 dB-gain range, 1.2 μs minimum settling time for WiMAX receiver

The IEEE 802.16 standard uses orthogonal frequency division multiplexing (OFDM) to allow high data rates in WiMAX environment. The stringent settling-time constraints of OFDM signals make conventional closed-loop feedback AGC impractical for WiMAX applications. This paper presents a novel fast-settling feed-forward automatic gain control (AGC) circuit designed for WiMAX receivers. The proposed AGC uses a switched coarse gain-setting followed by a continuous fine gain-setting to accelerate locking speed. The coarse gain-setting is performed without peak detection (PD) and the fine gain-setting is carried out by a one-step method both for shortened settling time. The chip is fabricated in 0.13 μm CMOS technology. The measurement results verify that the 48 dB AGC converges to the desired level within 1.2 μs minimum settling time. Besides, the THD is 0.32–1.37 % and the power consumption is 5.2 mW accordingly.     

A fast,straightforward, and accurate computer-aided design for highly efficient metasurface–assisted Fabry-Perot cavity antennas based on the equivalent circuit approach

In this paper, a fast, robust and accurate computer-aided procedure for design and analysis of highly efficient metasurface-assisted Fabry-Perot cavity antennas (FPCAs) is proposed. The automatic design algorithm is based on the equivalent circuit model (ECM) and it is capable of predicting the performances of FPCAs whose lateral walls are covered with a perfect electric conductor (PEC). In addition, it wipes out the computational burden arising from trial-and-error steps appearing in the conventional design techniques. As a prototype, according to the proposed design algorithm, a high gain FPCA with extremely high aperture efficiency is designed and fabricated for wireless applications. The equivalent circuit of the employed metasurface-based PRS is modified to enhance the accuracy of extracting the phase and magnitude of its reflection coefficient. To obtain the structural parameters of PRS, a hybrid optimization is applied to the proposed ECM. Simulated results show a maximum directivity of 18.6 dBi at 5.8 GHz leading to a high aperture efficiency of 126%. Experimental measurements on the fabricated prototype are also presented and the results confirm the theoretical and numerical predictions. The proposed design method is general and can be extended for other similar FPCA types exhibiting dual-, multi- and wide-band performances.     

A 1.4-V 48-μW current-mode front-end circuit for analog hearing aids with frequency compensation

正A current-mode front-end circuit with low voltage and low power for analog hearing aids is presented. The circuit consists of a current-mode AGC(automatic gain control) and a current-mode adaptive filter.Compared with its conventional voltage-mode counterparts,the proposed front-end circuit has the identified features of frequency compensation based on the state space theory and continuous gain with an exponential characteristic.The frequency compensation which appears only in the DSP unit of the digital hearing aid can upgrade the performance of the analog hearing aid in the field of low-frequency hearing loss.The continuous gain should meet the requirement of any input amplitude level,while its exponential characteristic leads to a large input dynamic range in accordance with the dB SPL(sound pressure level).Furthermore,the front-end circuit also provides a discrete knee point and discrete compression ratio to allow for high calibration flexibility.These features can accommodate users whose ears have different pain thresholds.Taking advantage of the current-mode technique,the MOS transistors work in the subthreshold region so that the quiescent current is small.Moreover,the input current can be compressed to a low voltage signal for processing according to the compression principle from the current-domain to the voltage-domain.Therefore,the objective of low voltage and low power(48μW at 1.4 V) can be easily achieved in a high threshold-voltage CMOS process of 0.35μm(V_(TON) + |V_(TOP)|≈1.35 V).The THD is below -45 dB.The fabricated chip only occupies the area of 1×0.5 mm~2 and 1×1 mm~2.     

A 90 μW continuous-time front-end with 10b SAR-ADC for capacitive MEMS accelerometers

This paper presents a low power read-out front-end for 3-axis MEMS capacitive accelerometer. The front-end includes the analog preamplifier (to sense the signal coming from the MEMS) and a Successive-Approximation 10b A/D Converter, for digitalization and off-chip digital-signal-processing. Power minimization is achieved by using a continuous-time sensing preamplifier (i.e. constant-charge capacitance-to-voltage conversion) and SAR-ADC with bridge capacitive reduction. Preamplifier programmable in-band gain allows to accommodate different MEMS sensitivities. A very high-impedance MOS transistor is used for MEMS biasing, thus providing very low frequency (<1 Hz) AC coupling. In a 0.13 μm CMOS technology, the full channel consumes 90 μW from a single 1.2 V supply voltage, and achieves an equivalent 67.9 dB_Full-Scale@SNR in [1 Hz–4 kHz] bandwidth by exploiting oversampling ratio.