A first multigigahertz digitally controlled oscillator for wireless applications

A novel digitally controlled oscillator (DCO) architecture for multigigahertz wireless RF applications, such as short-range wireless connectivity or cellular phones, is proposed and demonstrated. It deliberately avoids any use of an analog tuning voltage control line. Fine frequency resolution is achieved through high-speed dithering, yet the resulting spurious tones are very low. This enables to employ fully digital frequency synthesizers in the most advanced deep-submicrometer digital CMOS processes, which allow almost no analog extensions. It promotes cost-effective integration with the digital back-end onto a single silicon die. The demonstrator test chip has been fabricated in a digital 0.13 /spl mu/m CMOS process together with a digital signal processor to investigate noise coupling. The 2.4 GHz DCO core consumes 2.3 mA from a 1.5 V supply and has a very large tuning range of 500 MHz. The phase noise is -112 dBc/Hz at 500 kHz offset. The presented ideas have been incorporated in a commercial Bluetooth transceiver.     

A portable digitally controlled oscillator using novel varactors

This work presents a portable digitally controlled oscillator (DCO) by using two-input NOR gates as a digitally controlled varactor (DCV) in fine-tuning delay cell design. This novel varactor uses the gate capacitance difference of NOR gates under different digital control inputs to establish a DCV. Thus proposed DCO can improve delay resolution 256 times better than a single buffer design. This study also examines different types of NOR/NAND gates (2-input or 3-input) for DCV. The proposed DCO with novel DCV can be implemented with standard cells, and thus it can be ported to different processes in short time. Furthermore, the final circuit layout can be generated using an auto placement and routing (APR) tools. A test chip demonstrates that LSB resolution of the DCO can be improved to 1.55 ps with standard 0.35-/spl mu/m 2P4M CMOS digital cell library. The proposed DCO has good performance in terms of fine resolution, high portability, and short design turnaround cycle compared with conventional DCO designs.     

应用于DVB电视调谐器的低相位噪声数控晶体振荡器设计

本文提出了一种全集成的25-MHz数字控制晶体振荡器。该数控晶体振荡器基于Colpitts结构实现。通过自动幅度控制电路实现相位噪声的优化。通过10位的温度计译码电容阵列实现自动频率控制。测试结果表明,该数控晶体振荡器在1kHz和10kHz频偏处的相位噪声分别为–139 dBc/Hz和–151 dBc/Hz。频率调谐范围约为35ppm,频率精度为0.04ppm。该数控晶体振荡器在SMIC 0.18μm CMOS工艺下实现,电源电压1.8V,消耗电流1mA。     

A low-phase-noise digitally controlled crystal oscillator for DVB TV tuners

This paper presents a 25-MHz fully-integrated digitally controlled crystal oscillator(DCXO) with automatic amplitude control(AAC).The DCXO is based on Colpitts topology for one-pin solution.The AAC circuit is introduced to optimize the phase noise performance.The automatic frequency control is realized by a 10-bit thermometer-code segmental tapered MOS capacitor array,ensuring a～35 ppm tuning range and～0.04 ppm frequency step.The measured phase noise results are-139 dBc/Hz at 1 kHz and-151 dBc/Hz at 10 k...     

A digitally controlled 2.4-GHz oscillator in 65-nm CMOS

This article presents a 2.4-GHz digitally controlled oscillator (DCO) for the ISM band. The circuit is designed using a 65-nm CMOS technology with an operating voltage of 1.2 V. The DCO comprises an LC oscillator core and the digital interface logic. The measured total frequency range is from 2.26 to 3.04 GHz. Its frequency quantization step is approximately 20 kHz, and using a digital ΣΔ-modulator (SDM), its effective frequency resolution is better than 1 kHz. Current consumption of the oscillator core is tunable through a 6-bit digital word. The measured phase noise is −122 dBc/Hz at 1-MHz offset frequency with 4.8-mA current consumption.     

A portable high-frequency digitally controlled oscillator (DCO)

A novel digitally-controlled oscillator (DCO) is reported. Utilizing a new capacitive load, the new DCO is capable of producing much higher output frequencies than existing DCOs. All other components are fully digital and modular, allowing portability to any CMOS process and customization for different applications. At the heart of the DCO is a digital ring oscillator (DRO) that utilizes the new shunt-capacitive loads. Unprecedented higher frequencies are obtained through a novel idea of electrically removing the effect of un-enabled loads. Simple design conditions for achieving proper operation of the DRO are provided and verified through simulations with several technologies. Spice simulations verified the correct and superior operation of the DCO even with device mismatch. A custom layout of the DRO was generated using LFoundry's 150 nm technology. The total DRO area was found to be 418 µm². Comparison with other DCOs and VCO shows that the new DCO outperforms conventional DCOs in all aspects; maximum attainable frequency, power efficiency and required number of control bits to achieve a certain resolution.     

基于自由环振和飞加法器结构的时域数字控制振荡器

A time-domain digitally controlled oscillator （DCO） is proposed. The DCO is composed of a free-running ring oscillator （FRO） and a two lap-selectors integrated flying-adder （FA）. With a coiled cell array which allows uniform loading capacitances of the delay cells, the FRO produces 32 outputs with consistent tap spacing for the FA as reference clocks. The FA uses the outputs from the FRO to generate the output of the DCO according to the control number, resulting in a linear dependence of the output period, instead of the frequency on the digital controlling word input. Thus the proposed DCO ensures a good conversion linearity in a time-domain, and is suitable for time-domain all-digital phase locked loop applications. The DCO was implemented in a standard 0.13μm digital logic CMOS process. The measurement results show that the DCO has a linear and monotonic tuning curve with gain variation of less than 10%, and a very low root mean square period jitter of 9.3 ps in the output clocks. The DCO works well at supply voltages ranging from 0.6 to 1.2 V, and consumes 4 mW of power with 500 MHz frequency output at 1.2 V supply voltage.     

A time-domain digitally controlled oscillator composed of a free running ring oscillator and flying-adder

t supply voltages ranging from 0.6 to 1.2 V, and consumes 4 mW of power with 500 MHz frequency output at 1.2 V supply voltage.     

A digitally controlled oscillator in a 90 nm digital CMOS process for mobile phones

We propose and demonstrate the first RF digitally controlled oscillator (DCO) for cellular mobile phones. The DCO is part of a single-chip quad-band fully compliant GSM transceiver realized in a 90 nm digital CMOS process. Wide and precise linear frequency tuning is achieved through digital control of a large array of standard n-poly/n-well MOSCAP devices that operate in flat regions of their C- V curves. The varactors are partitioned into binary-weighted and unit-weighted banks that are sequentially activated during frequency locking and tracking. The finest varactor step size is 12 kHz at the 1.6-2.0 GHz high-band output. To attenuate the quantization noise to below the natural oscillator phase noise, the varactors undergo high-speed second-order /spl Sigma//spl Delta/ dithering. We analyze the effect of the /spl Sigma//spl Delta/ dithering on the phase noise and show that it can be made sufficiently small. The measured phase noise at 20 MHz offset in the GSM900 band is -165 dBc/Hz and shows no degradation due to the /spl Sigma//spl Delta/ dithering. The 3.6 GHz DCO core consumes 18.0 mA from a 1.4 V supply and has a very wide tuning range of 900 MHz to support the quad-band operation.     

A digitally temperature-compensated crystal oscillator

The base frequency of oscillators used in the Global System for Mobile Communication (GSM) network or Global Positioning System (GPS) receiver applications needs to be very stable with respect to temperature and supply-voltage variations. One approach to obtain extremely good frequency stability is the use of oven-stabilized crystal oscillators. With this kind of oscillator, a frequency stability versus temperature of a few ppb versus the standard temperature range can be achieved. In this paper, a digitally compensated crystal oscillator is described. The system provides a frequency stability of (Δf)/f<1.5 ppm for a temperature range of -40°C to 90°C compared to about ±20 ppm for a noncompensated crystal. The core of the system is an application-specified integrated circuit (ASIC) fabricated in a standard 0.8-μm CMOS process. The power consumption for the oscillator running at 13 MHz is 100 mW. The final device equipped with the ASIC, crystal blank, and a few external components fits into a 14×9×3 mm³ package     

LMS-based calibration of an RF digitally controlled oscillator for mobile phones

We propose a least-mean square based gain calibration technique of an RF digitally controlled oscillator (DCO) in an all-digital phase-locked loop (ADPLL). The DCO gain of about 12-kHz/least significant bit is subject to process, voltage and temperature variations, but is tracked and compensated in real time. Precise setting of the inverse DCO gain in the ADPLL modulating path allows direct wide-band frequency modulation that is independent from the ADPLL loop bandwidth. The technique is part of a single-chip fully compliant Global System for Mobile Communications (GSM)/EDGE transceiver in 90-nm digital CMOS.     

All-digital PLL using bulk-controlled varactor and pulse-based digitally controlled oscillator

This work presented a 150–450-MHz, all-digital phase-locked loop (ADPLL) implemented in a 0.18 μm CMOS process. The design utilizes bulk-controlled varactor and pulse-based digitally controlled oscillator (PB-DCO) providing a high timing resolution and a good jitter performance. The worst-case total locking time of the proposed ADPLL is 32 reference clock cycles. The divider used here divides by factors from 2 to 63. A test chip is implemented and verified. The RMS and peak-to-peak jitters are 6.7 and 44 ps, respectively, at 450-MHz. The peak-to-peak jitter is 2.0% at 450-MHz. When the multiplication of divider is varying at 150-MHz, the peak-to-peak jitters are less than 3.2%. The power consumption is 16.2-mW at 450-MHz. The core area of ADPLL is only 260 × 360 mm². This clock generator can be applied as re-usable silicon IP for system-on-chip (SoC) applications.     

A low-power and low-phase-noise LC digitally controlled oscillator featuring a novel capacitor bank

A monolithic low-power and low-phase-noise digitally controlled oscillator(DCO) based on a symmetric spiral inductor with center-tap and novel capacitor bank was implemented in a 0.18μm CMOS process with six metal layers.A third new way to change capacitance is proposed and implemented in this work.Results show that the phase noise at 1 MHz offset frequency is below -122.5 dBc/Hz while drawing a current of only 4.8 mA from a 1.8 V supply. Also,the DCO can work at low supply voltage conditions with a 1.6 ...     

一种基于新型电容阵列的低功耗低相位噪声数字控制振荡器

摘要： 利用0.18CMOS六层金属工艺实现了一个全集成的低功耗低相位噪声的数字控制振荡器,该数字控制振荡器谐振回路由中央抽头对称螺旋电感和电容阵列构成。文中介绍并实现了一种新型的改变电容的方法。该方法在不需要改变接入谐振回路电容的数量而通过改变其互联拓扑关系来实现。测试结果表明,在1.8V电源电压下,核心模块消耗4.8mA的电流,相位噪声在1MHz频偏处为-122.5dBc/Hz。在1.6V的低电源电压,消耗约4mA的电流情况下,1MHz频偏处相位噪声仍可达到-121.5dBc/Hz. 同时,电源推挽度小于10MHz/V。     

600MHz BiCMOS digitally controlled oscillator for clock recovery and frequency synthesis PLLs

A 16-bit digitally controlled BiCMOS ring oscillator (DCO) is described. This BiCMOS DCO design provides improved frequency stability under thermal fluctuations. Simulations of a 5-stage DCO using 1μm BiCMOS process parameters achieved a controllable frequency range of 90-640MHz with a linear/quasi-linear range of around 300MHz. A tiny test chip was fabricated using MOSIS Orbit 2μm low-cost analogue CMOS process technology that provides a lateral NPN bipolar device option. Monotone frequency gain (frequency vs control-word transfer function) with fine stepping (tuning) over several kHz was verified experimentally, thus auguring the prospect of accurate frequency lock in an all-digital phase-locked loop (ADPLL) application. Worstcase jitter due to digital control transitions at pathological control-word boundaries for the BiCMOS DCO was observed to be less than 50 ps. This BiCMOS design would thus provide performance enhancement in PLL applications such as clock recovery and frequency synthesis.     

Novel digitally programmable multiphase voltage controlled oscillator and its stability discussion

In this paper, a novel programmable current-mode multiphase voltage controlled oscillator (MVCO) is presented. The proposed MVCO consists of four identical first-order all-pass filters, which act for delay cells of the MVCO. By switching the programmable MOS switches on and off, the MVCO can provide six or eight different phase sinusoidal signals. Theoretically, the proposed MVCO can provide 2n (n ? 3) different phase sinusoidal signals by cascading n (n ? 3) first-order all-pass delay cells. Compared with previous reported works, this MVCO has the advantages of lower supply voltage, lower power consumption, a smaller chip area and more multi-outputs than other reported works. In particularly, by using programmable switches and cascading more first-order all-pass delay cells, the proposed MVCO can theoretically provide 2n (n ? 3) different phase sinusoidal signals.     

A digitally controlled PLL for SoC applications

A fully integrated digitally controlled phase-locked loop (PLL) used as a clock multiplying circuit is designed and fabricated. The PLL has no off-chip components and it is made from standard cells found in most digital standard cell libraries. The design is, therefore, portable between technologies as an IP block. Using a 0.35-/spl mu/m standard CMOS process and a 3.0-V supply voltage, the PLL has a frequency range of 152 to 366 MHz and occupies an on-chip area of 0.07 mm/sup 2/. In addition, the next version of this all-digital PLL is described in synthesizable VHDL code, which simplifies digital system simulation and change of process. A new time-to-digital converter with higher resolution is designed for the improved PLL. An improved digitally controlled oscillator is also suggested.     

一种用于手持移动终端的九频段双天线系统

提出了一种应用于手持移动终端的九频段双天线系统.该双天线系统由两个对称的天线单元、一个解耦地枝和一个浮置结构组成.构成天线单元的驱动分枝和寄生地枝共同激励起多个谐振模式.通过采用解耦地枝,降低了低频带内的互耦,改善了高频带内的阻抗匹配.通过添加浮置结构,增加了低频带和高频带的工作带宽,降低了高频带下限频率附近的互耦.实测结果表明:天线样品在低频带和高频带内的-6 dB公共阻抗带宽分别为276 MHz (692～968 MHz)和1 110 MHz(1 636～2 746 MHz),覆盖了LTE700/2300/2500,GSM850/900,DCS/PCS/UMTS和2.4-GHz WLAN频段;低频带内的互耦低于-10 dB,高频带内的互耦低于-13.7 dB.根据实测三维辐射方向图计算了双天线系统的包络相关系数、平均有效增益和分集增益计算结果表明,双天线系统具有良好的分集性能.     

Dual-band transmitters using digitally predistorted frequency multipliers for reconfigurable radios

Two methods for reconfigurable transmitters using frequency multipliers in conjunction with digital predistortion linearizers are developed. One method utilizes a circuit topology that can be switched between a fundamental-mode in-phase combined amplifier, and a push-push frequency doubler using input phasing. Investigation to maximize output harmonics out of regular power amplifiers (PAs) was performed, and the implementation of the device was successful for the amplifier- and doubler-mode operation. To satisfy optimal load-line conditions for the operation in both modes, a bi-tuned output-combining technique is introduced as well. Measurement results indicate that the circuit is able to transmit 28 dBm of output power at 900 MHz in the amplifier mode, and 22 dBm at 1800 MHz in the doubler mode. In combination with predistortion linearization, the reconfigurable transmitter was shown to be capable of amplifying IS-95B code-division multiple-access (CDMA) signals with an adjacent-channel power ratio (ACPR) up to -58dBc/30kHz. The second suggested method utilizes a fundamental-frequency PA followed by a varactor multiplier that can be bypassed with an RF switch. A varactor-diode doubler with a saturated conversion loss of 1.3 dB was built and tested. Using predistortion linearization techniques on both the PA and doubler, an ACPR of -53dBc/30kHz at 885-kHz offset was achieved for a CDMA signal transmitted at 1850 MHz.     

A monotonic digitally controlled delay element

A monotonic digitally controlled delay element (DCDE) is implemented in the 0.18 /spl mu/m CMOS technology. In this paper, the design procedure of the new architecture and measurement results are reported. The delay of the DCDE changes monotonically with respect to the digital input vector. The monotonicity is one of the important features of this new architecture. Due to its monotonic behavior, the design of the DCDE is rather straightforward. The DCDE can be analyzed by a simple set of empirical equations with reasonable accuracy and can be made more tolerant to process, temperature, and supply voltage variations. The implemented delay element provides a delay resolution of as low as 2 ps and consumes 170 /spl mu/W to 340 /spl mu/W static power depending on the digital input vector.