基于标准单元的低功耗FIR数字滤波器VLSI实现

功耗与硅面积一样已成为芯片设计中的关键问题，尤其是在数字信号处理集成电路设计中。基于标准单元的VLSI设计是实现数字信号处理模块芯片或模块的重要方法。该文提出了一种基于标准单元的低功耗FIR滤波器多层次设计方案，其中体系结构层次采用多层流水线策略，逻辑层次将加法集成到部分积压缩中，在电路层次采用最小器件，从而在最大限度减少面积的同时降低了FIR的功耗。根据实际需求，该设计方案易于扩展和变换，可灵活应用到其它类似的滤波器设计中。实现结果表明在TSMC0.25标准单元库下FIR的功耗最多可降低20％以上。     

Design of New Optimized Architecture Processor for DWT

This paper presents a VLSI implementation of One Dimensional Direct Discrete Wavelet transform (1-D DWT). The DDWT can be viewed as a multi-resolution decomposition of a signal. This means that it decomposes a signal into its components in different frequency bands (octave bands). We propose a new architecture using parallel filters. We consider the implementation of 1-D three levels DWT. The proposed architecture is simple and offers 16-bit precision on input and output data. It is constituted of three basic units: one register bank, four filters, and a control unit. The filters are of different lengths and with new coefficients derived from Daubechies filter coefficients. The designed processor architecture requires no interface circuitry for interconnection to a standard communication bus. The architecture can compute DWT at a data rate of 12×10⁶samples/s corresponding to a typical clock speed of 12 MHz. The architecture is simulated at the gate level in VLSI.     

Power and delay efficient fir filter design using ESSA and VL-CSKA based booth multiplier

FIR filter plays a major role in digital image processing applications. The power and delay performance of any FIR filter depends on the switching activities between the filter coefficients (FCs) and its basic arithmetic operations (i.e., multiplication and addition) performed in the convolution equations. In this paper, a new FIR filter is designed using Enhanced Squirrel Search Algorithm (ESSA) and Variable latency Carry skip adder (VL-CSKA) based booth multiplier. The proposed ESSA algorithm selects an optimal FC by minimizing the switching activities of FC based on the ripple contents, power and Transition width parameter to meet the required specifications of FIR filter in the frequency domain. Also, the VL-CSKA based booth multiplier is proposed to reduce the delay of FIR filter with parallel addition of partial products (PPs). In this design, the VL-CSKA adders utilize variable size and compound gate-based skip logic to deduce the delay with low power. The proposed FIR filter is simulated in Xilinx working platform by developing Verilog coding. The simulation result shows that the proposed FIR filter outperforms the state-of-the-art FIR filters by consuming only 0.142 mW power with delay of 28.175 ns.     

The Ising genetic algorithm with Gibbs distribution sampling: Application to FIR filter design

In this paper the design of maximally flat linear phase finite impulse response (FIR) filters is considered. The problem with using the genetic algorithm (GA) in this kind of problems is the high cost of evaluating the fitness for each string in the population. The designing of optimum FIR filters under given constraints and required criteria includes exhaustive number of evaluations for filter coefficients, and the repetitive evaluations of objective functions that implicitly constitutes construction of the filter transfer functions. This problem is handled here with acceptable results utilizing Markov random fields (MRF's) approach. We establish a new theoretical approach here and we apply it on the design of FIR filters. This approach allows us to construct an explicit probabilistic model of the GA fitness function forming what is called the “Ising GA” that is based on sampling from a Gibbs distribution. Ising GA avoids the exhaustive design of suggested FIR filters (solutions) for every string of coefficients in every generation and replace this by a probabilistic model of fitness every gap (period) of iterations. Experimentations done with Ising GA of probabilistic fitness models are less costly than those done with standard GA and with high quality solutions.     

采用8031作主控器的时域FIR数字滤波器

长期以来，ＦＩＲ数字滤波器大多是在频域上实现。因为，在时域上实现ＦＩＲ数字滤波所遇到的首要问题，是输入信号序列与冲激响应序列的卷积运算速度难以提高。然而，随着超大规模集成电路的飞速发展，硬件集成度与运算速度获得极大的改观，在时域上实现ＦＩＲ数字滤波已成为可能。ＩＭＳＡ１００是高速、高精度３２级数字信号处理器，是完成卷积运算的理想器件。本文论证了用ＩＭＳＡ１００实现时域ＦＩＲ数字滤波器的可行性和硬件设计中的一些问题，并给出了应用举例。在设计中选用８０３１单片机做主控器，大大提高了性能价格比，使这一设计具有很高的实用价值。     

Recursive FIR filter structures on FPGA

A new approach to piecewise-polynomial approximation and recursive implementation structures for linear-phase Finite Impulse Response (FIR) filters have been recently proposed. In this paper, we describe hardware prototype implementations of the new structures for all four types of linear-phase FIR filters using a Field Programmable Gate Array (FPGA) based platform. Narrowband lowpass filters and narrowband differentiators are used as design examples to demonstrate the functionality and efficiency of the implementations. The required wordlength and resource usage is analyzed.     

复系数FIR数字滤波器的神经网络设计方法

神经网络是一种设计实系数FIR滤波器的有效算法,为了将该方法扩展到复数域,建立统一的基于神经网络的滤波器设计框架,文中提出了一种用多层神经网络设计任意幅频响应的复系数FIR数字滤波器的新算法,主要思想是将设计问题转化为实系数多层神经网络的训练问题,在实数域对幅频响应的平方误差函数的实部和虚部分别进行最小化,误差将收敛到全局最小点.实验结果表明,利用该算法设计的滤波器具有较小的幅频响应误差和群延迟误差.该算法能解决具有任意幅频响应和群延迟要求的问题,是一种有效的设计算法.     

改进的粒子群优化算法设计FIR低通数字滤波器

粒子群优化算法(PSO)因具有参数少、易于实现等优点,在解决优化问题时表现出很好的性能。有限长单位脉冲响应(FIR)数字滤波器因具有稳定的结构、易于实现等优点,在实际中有着很广泛的应用。因此,将基于三角函数因子的改进PSO算法(TFPSO)用于对FIR低通数字滤波器性能的优化,并将其与基于折射原理反向学习(refrPSO)、基于反向学习(OPSO)的PSO算法所设计的FIR低通数字滤波器的性能进行比较。在实验中构造出一种性能较好的适应值函数,以验证这几种改进的PSO算法所设计的FIR低通数字滤波器的性能。实验结果表明,基于三角函数因子的PSO算法滤波性能较差,而基于折射原理反向学习的PSO算法性能最佳。     

Laguerre discrete-time filter design

The design of discrete-time ideal filters by finite impulse response (FIR) method requires long FIR filter structures.This is due to the infinite impulse response characteristics of the ideal filters. Optimum Laguerre filter structures with smaller length can be used instead of FIR filters to reduce the order of the filters.In this paper the method of designing optimum Laguerre ideal low-pass, band-pass, high-pass, and band-reject filters is introduced. The optimization is performed by evaluating the Laguerre parameter and coefficients when the mean-square-error between the frequency response of the desired filter and its corresponding Laguerre network frequency response is minimum. The problem with the Laguerre filter design is the complexity of computations for evaluating the optimum Laguerre parameter. This complexity is reduced to one half by introducing a lemma.Both, analytical and numerical solutions are presented and the results are illustrated via some examples. The corresponding results yield a reduced filter order, and appropriate linear phase, with lower ripples in stop-band and pass-band compared to the conventional FIR filters.     

Hardware based genetic evolution of self-adaptive arbitrary response FIR filters

This work presents a hardware implementation of an FIR filter that is self-adaptive; that responds to arbitrary frequency response landscapes; that has built-in coefficient error tolerance capabilities; and that has a minimal adaptation latency. This hardware design is based on a heuristic genetic algorithm. Experimental results show that the proposed design is more efficient than non-evolutionary designs even for arbitrary response filters. As a byproduct, the paper also presents a novel flow for the complete hardware design of what is termed as an Evolutionary System on Chip (ESoC). With the inclusion of an evolutionary process, the ESoC is a new paradigm in modern System on Chip (SoC) designs. The ESoC methodology could be a very useful structured FPGA/ASIC implementation alternative in many practical applications of FIR filters.     

FIR数字滤波器设计及FPGA实现

为了研究滤波器设计及实现方式,用VisualBasic6．0软件研制出了FIR数字滤波器的设计软件。为了验证软件设计滤波器是否正确,给出了设计实例,并将设计的滤波器与matlab软件设计的滤波器进行了比较,结果表明,两种软件设计的结果相同。设计软件可将滤波器直接导出VHDL文件及系数文件,经QuartusIl6．0软件综合后产生的网表文件可直接配置FPGA,实现了FIR数字滤波器的在线设计、在线修改。     

Pruned Feed-forward Networks for Efficient Implementation of Multiple FIR Filters with Arbitrary Frequency Responses

A new algorithm is presented for efficient implementation of multiple FIR filters in real-time applications. We introduce an analogy between the multiple FIR filters and linear feed-forward networks, and show how the FIR filters with any frequency characteristics may be designed by a learning algorithm of the network with proper choice of training patterns. Starting from a fully-connected feed-forward architecture, more efficient network architectures may be obtainable by pruning connection weights with minor contributions. For demonstration we design feed-forward networks for 16 bandpass cochlear filters with much less connection weights and moderate performance degradation.     

Novel Double Modular Redundancy Based Fault-Tolerant FIR Filter for Image Denoising

In signal processing and communication systems, digital filters are widely employed. In some circumstances, the reliability of those systems is crucial, necessitating the use of fault tolerant filter implementations. Many strategies have been presented throughout the years to achieve fault tolerance by utilising the structure and properties of the filters. As technology advances, more complicated systems with several filters become possible. Some of the filters in those complicated systems frequently function in parallel, for example, by applying the same filter to various input signals. Recently, a simple strategy for achieving fault tolerance that takes advantage of the availability of parallel filters was given. Many fault-tolerant ways that take advantage of the filter’s structure and properties have been proposed throughout the years. The primary idea is to use structured authentication scan chains to study the internal states of finite impulse response (FIR) components in order to detect and recover the exact state of faulty modules through the state of non-faulty modules. Finally, a simple solution of Double modular redundancy (DMR) based fault tolerance was developed that takes advantage of the availability of parallel filters for image denoising. This approach is expanded in this short to display how parallel filters can be protected using error correction codes (ECCs) in which each filter is comparable to a bit in a standard ECC. “Advanced error recovery for parallel systems,” the suggested technique, can find and eliminate hidden defects in FIR modules, and also restore the system from multiple failures impacting two FIR modules. From the implementation, Xilinx ISE 14.7 was found to have given significant error reduction capability in the fault calculations and reduction in the area which reduces the cost of implementation. Faults were introduced in all the outputs of the functional filters and found that the fault in every output is corrected.     

分数抽样率变换中线性相位FIR滤波器多相分解的对称性研究

为提高分数抽样率变换系统的计算效率, 在讨论其滤波器多相分解结构的基础上, 利用线性相位FIR滤波器的系数对称性, 构造多相分解系数的中心对称矩阵, 推导出适用于任意分数抽样率和任意滤波器阶数的高效实现方法, 并给出所需乘法与加法运算量的计算公式. 测试结果表明, 与直接计算相比, 采用本文方法可减少50%乘法运算和30%加法运算, 计算效率显著提高.     

Cascaded warped-FIR and FIR filter structure for loudspeaker equalization with low computational cost requirements

This paper proposes an improved filter structure and methodology for the equalization of loudspeakers and other audio systems. It employs a cascaded structure of a finite impulse response (FIR) filter and a warped-FIR filter in order to obtain the best performance of both types of filters. In the task of loudspeaker equalization, FIR filters achieve excellent resolution and equalization at high frequencies, but at low frequencies the resolution obtained is too poor when evaluated in a logarithmic frequency axis, that could only be improved using high order filters. To solve this lack of resolution at low frequencies, warped-FIR filters have been employed, but at the expense of decreasing the resolution of the filter at high frequencies and increasing the complexity of the filter structure and its computational cost. The proposed combination of both types of filters, combined with the correct selection of their orders, and the λ value for the warped-FIR filter, allows the FIR filter to maintain its good resolution at high frequencies and achieve enough resolution at low frequencies with the warped-FIR filter. In this way, lower order filters with lower computational cost could be obtained than when using FIR or warped-FIR only. This approximation attains a more uniform resolution of the filter when evaluated in octaves, behaving much more like human hearing, than the linear frequency resolution obtained when employing only FIR filters.     

Periodic stabilization of look-ahead filters in VLSI implementation

A linear look-ahead filter is a model of digital dynamical systems and infinite impulse response filters for fast pipeline processing in very large scale integration (VLSI) implementation of the digital systems. Two essential problems to be dealt with in the design of look-ahead filters are stability and computational complexity of the filter. In this paper, a new periodic scheme is proposed to stabilize the d-step look-ahead filter and provide minimum amount of computation in digital implementation of the filter.     

解离散系数滤波器设计问题的分支定界算法

基于离散系数滤波器设计问题已有的半定规划松弛模型,利用文献[6]的方法给出了该问题的二次规划松弛模型,该模型能给出比半定规划模型更好的界,然后运用分支定界方法求解该模型。与随机扰动方法相比,该方法能得到一个性能更好的次优解,对于精度要求较高的滤波器设计问题,这种方法非常有效,并通过了仿真实验的证实。     

Design of nonrecursive FIR filters with simultaneously MAXFLAT magnitude and prescribed cutoff frequency

Maximally-flat (MAXFLAT) FIR filter design still has a problem in overcoming the cutoff-frequency error due to approximation of the desired frequency response by some closed-form solution. In order to overcome such a difficulty, this paper describes a new method for the design of nonrecursive FIR filters with simultaneously MAXFLAT magnitude and accurate cutoff frequency. The proposed method provides a general formula to find interpolation coefficients for a new closed-form expression of this filter type, obtained by solving solutions of linear differential equations that are derived from the maximal flatness and cutoff-frequency conditions. In addition, this method efficiently determines the optimal degree of flatness by using a powerful objective error function derived from this closed-form solution, and allows direct and simple computation of the coefficients of the filter with the desired frequency response. The design examples are shown to provide a complete and accurate solution for the design of such filters.     

Multiplierless Adaptive Filtering

Bose, T., Venkatachalam, A., and Thamvichai, R., Multiplierless Adaptive Filtering, Digital Signal Processing12 (2002) 107–118When digital filters are designed with power-of-2 coefficients, the multiplications can be implemented by simple shifting operations. For VLSI implementations, multiplierless filters are faster and more compact than filters with multipliers. In this paper, an algorithm for finding and updating the power-of-2 coefficients of an adaptive filter is designed. The new method uses the well-known Genetic Algorithm (GA) for this purpose. The GA is used in a unique way in order to reduce computations. Small blocks of data are used for the GA and only one new generation is produced per sample of data. This, coupled with the fact that the coefficients are power-of-2, yields a computational complexity of O(N) additions and no multiplications. The algorithm is investigated for applications in adaptive linear prediction and system identification. The results are very promising and illustrate the performance of the new algorithm.     

一种提高双正交小波消失矩的算法及其在图像编码中的应用

文章介绍了一种提高任意双正交小波消失矩的方法。此法根据小波的消失矩与其对应FIR滤波器的Laurent多项式在z=1处零点阶数相等的关系,基于提升格式采用迭代法设计提升系数,便于工程实现。在图像压缩编码中,用此法可方便地提高所选小波的消失矩,改变滤波器的性能,获得所需的新小波,从而实现预期目标。