一种4-Mb高速低功耗CMOS SRAM的设计

高性能的系统芯片对数据存取速度有了更严格的要求,同时低功耗设计已成为VLSI的研究热点和挑战.本文设计了一款4-Mb(512K×8bit)的高速、低功耗静态存储器(SRAM).它采用0.25μm CMOS标准工艺和传统的六管单元.文章分析了影响存储器速度和功耗的原因,重点讨论了存储器的总体结构、灵敏放大器及位线电路.通过系统优化,达到15ns的存取时间.     

SRAM灵敏放大器的设计改进及其Hspice仿真分析

静态随机存取存储器（SRAM）由于其自身的低功耗和高速的优势而成为半导体存储器中不可或缺的重要产品。提高和改善静态存储器的性能依然是集成电路设计领域的重要课题。从降低静态存储器功耗的角度出发，重点研究了静态存储器的关键模块——灵敏放大器的工作机理和结构，设计了一种改进型的锁存型灵敏放大器，Hspice的仿真表明，该放大器的功耗大大低于传统的静态存储器的灵敏放大器模块的功耗。     

一种超低功耗、容错的静态随机存储器设计

为了减轻辐射环境中静态随机存储器（SRAM）受单粒子翻转（SEU）的影响以及解决低功耗和稳定性的问题,采用TSMC 90nm工艺,设计了一款可应用于辐射环境中的超低功耗容错静态随机存储器。该SRAM基于双互锁存储单元（DICE）结构,以同步逻辑实现并具有1KB（1K×8b）的容量,每根位线上有128个标准存储单元,同时具有抗SEU特性,提高并保持了SRAM在亚阈值状态下的低功耗以及工作的稳定性。介绍了这种SRAM存储单元的电路设计及其功能仿真,当电源电压VDD为0.3V时,该SRAM工作频率最大可达到2.7MHz,此时功耗仅为0.35μW;而当VDD为1V时,最大工作频率为58.2MHz,功耗为83.22μW。     

一种基于时钟抽取偏置电压技术的存储器位线

基于一种新型时钟延时单元,设计了一种片上存储器的位线。在不增加版图面积的前提下,通过周期性地改变保持管的衬底偏置电压,减小了短路功耗、泄漏功耗和延迟时间,同时增加了电路的抗工艺波动能力。在SMIC 65 nm工艺下,完成了传统位线、改进后的位线以及静态随机存取存储器(SRAM)的设计。仿真结果表明,在1 GHz时钟频率下,改进后的两种位线与传统位线相比,功耗延迟积分别减小了19.1%和15.9%。最后,通过蒙特卡洛分析可知,改进后的位线相比于传统位线具有较强的抗工艺波动能力,即功耗延迟积的方差减小了97.1%。     

多端口寄存器堆的低功耗设计方法

随着半导体工艺的飞速发展和芯片工作频率的提高,芯片的功耗迅速增加,导致芯片发热量的增大和可靠性的下降。因此,功耗成为集成电路设计中的一个重要考虑因素。寄存器堆作为微处理器的关键部件,为了满足其运算速度和指令级并行的流水线结构,高速和多端口读写成为发展的必然趋势,其低功耗设计对降低整个处理器的功耗具有重要的意义。读写位线、负载电容、灵敏放大器、时钟翻转等是影响寄存器堆总功耗的重要因素。针对各因素进行低功耗设计成为寄存器堆设计的关键。     

三值钟控绝热静态随机存储器设计

通过对多值逻辑、绝热电路和三值SRAM结构的研究,提出一种新颖的三值钟控绝热静态随机存储器(SRAM)的设计方案。该方案利用NMOS管的自举效应,以绝热方式对SRAM的行列地址译码器、存储单元、敏感放大器等进行充放电,有效恢复储存在字线、位线、行列地址译码器等大开关电容上的电荷,实现三值信号的读出写入和能量回收。PSPICE模拟结果表明,所设计的三值钟控绝热SRAM具有正确的逻辑功能和低功耗特性,在相同的参数和输入信号情况下,与三值常规SRAM相比,节约功耗达68%。     

一种阵列布局优化的256 kb SRAM

介绍了一种阵列布局优化的256 kb(8 k×32位)低功耗SRAM。通过采用分级位线和局部灵敏放大器结构,减少位线上的负载电容;通过电压产生电路,获得写操作所需的参考电压,降低写操作时的位线电压摆动幅度,有效地减少了SRAM读写操作时的动态功耗。与传统结构的SRAM相比,该256 kb SRAM的写功耗可减少37.70 mW。     

低位线摆幅的低功耗SRAM设计

本文提出了一种低位线摆幅（LVBS）的低功耗SRAM结构。这种SRAM采用电荷分享方法降低线电压幅值，在写操作时使得位线电压摆幅减少了50％，从而显著降低了位线动态功耗。同时本文还分析了由于位线电压降低带来的静态噪声容限（SNM）等问题。实验结果表明相比较常规SRAM，LVBS SRAM可以节约30％的动态功耗。     

一种适于FPGA芯片的SRAM单元及外围电路设计

静态存储器(SRAM)功耗是整个芯片功耗的重要组成部分,并且大规模SRAM的仿真在芯片设计中也相当费时。提出了一种基于40 nm CMOS工艺、适用于FPGA芯片的SRAM单元结构,并为该结构设计了外围读写控制电路。仿真结果表明,该结构的SRAM单元在保证正确的读写操作下,静态漏电电流远远小于同工艺下普通阈值CMOS管构造的SRAM单元。同时,为了FPGA芯片设计时大规模SRAM功能仿真的需要,为SRAM单元等编写了verilog语言描述的行为级模型,完成了整个设计的功能验证。     

TFT-LCD驱动芯片内置SRAM的低功耗设计

内置SRAM是单片集成TFT-LCD驱动控制芯片中的图像数据存储模块.针对内置SRAM的低功耗设计要求,采用HWD结构和动态逻辑的字线译码电路,实现了1.8Mb SRAM的低功耗设计.电路采用0.18μm CMOS工艺实现,Hspice和Ultrasim仿真结果表明,与静态字线译码电路相比,功耗减小了20%;与DWL结构相比,功耗减小了16%;当访存时钟频率为31MHz时,SRAM存储单元的读写时间小于8ns,电源峰值功耗小于123mW,静态功耗为0.81mW.     

Design techniques and test methodology for low-power TCAMs

Ternary content addressable memories (TCAMs) are gaining importance in high-speed lookup-intensive applications. However, the high cost and power consumption are limiting their popularity and versatility. TCAM testing is also time consuming due to the complex integration of logic and memory. In this paper, we present a comprehensive review of the design techniques for low-power TCAMs. We also propose a novel test methodology for various TCAM components. The proposed test algorithms show significant improvement over the existing algorithms both in test complexity and fault coverage.     

A new erasing and row decoding scheme for low supply voltageoperation 16-Mb/64-Mb flash memories

To improve the performance of high-density flash memories, several circuit technologies have been developed. A word-line boost and clamp scheme realizes low supply voltage read operations. A flash programming scheme utilizing Fowler-Nordheim (F-N) tunneling for programming before erasure and a negative gate biased erasing scheme accomplish low-power, high-speed, and 5-V-only erase operations. The chip size penalty is estimated to be only 3% for the 16-Mb flash memories     

Wordline voltage generating system for low-power low-voltage flashmemories

A low-power wordline voltage generating system is developed for low-voltage flash memories. The limit for the stand-by current including the operation current for the band-gap reference and the stand-by wordline voltage generator is discussed. The system was implemented on a 1.8-V 32-Mb flash memory fabricated with a 0.25-μm flash memory process and achieved with very low stand-by current of 2 μA typically, and high operating frequency of 25 MHz in read operation at 1.8 V. A low-voltage level shifter with high-speed switching is also proposed     

Low-Power Programmable FPGA Routing Circuitry

We consider circuit techniques for reducing field-programmable gate-array (FPGA) power consumption and propose a family of new FPGA routing switch designs that are programmable to operate in three different modes: high-speed, low-power, or sleep. High-speed mode provides similar power and performance to traditional FPGA routing switches. In low-power mode, speed is curtailed in order to reduce power consumption. Leakage is reduced by 28%–52% in low-power versus high-speed mode, depending on the particular switch design selected. Dynamic power is reduced by 28%–31% in low-power mode. Leakage power in sleep mode, which is suitable for unused routing switches, is 61%–79% lower than in high-speed mode. Each of the proposed switch designs has a different power/area/speed tradeoff. All of the designs require only minor changes to a traditional routing switch and involve relatively small area overhead, making them easy to incorporate into current commercial FPGAs. The applicability of the new switches is motivated through an analysis of timing slack in industrial FPGA designs. It is observed that a considerable fraction of routing switches may be slowed down (operate in low-power mode), without impacting overall design performance.      

Low-power and high-speed ROM modules for ASIC applications

We describe in this paper the design of a set of low-power and high-speed NOR-type ROM modules suitable for embedded applications in ASICs or SOCs. The circuit is derived from the four-phase high-speed precharge-discharge dynamic CMOS logic (NHS-PDCMOS) with the number of operational phases reduced from four to one. This facilitates the interconnections to other system blocks that are usually designed to be one phase. Experimental results show that for the size of 2K×8, the proposed high-speed ROM module is about 1.89 times faster, consumes 21% less power, and occupies similar silicon area as compared to a conventional design. Also for the same size, the proposed low-power ROM module is 1.17 times faster, 14% smaller, and consumes 83% less power as compared to the conventional design     

An SRAM design using dual threshold voltage transistors and low-power quenchers

Static random access memories (SRAM) are widely used in computer systems and many portable devices. In this paper, we propose an SRAM cell with dual threshold voltage transistors. Low threshold voltage transistors are mainly used in driving bit-lines while high threshold voltage transistors are used in latching data voltages. The advantages of dual threshold voltage transistors can be used to reduce the access time and maintain data retention at the same time. Also, the unwanted oscillation of the output bitlines of memories caused by large currents in bitlines is reduced by adding two back-to-back quenchers. The proposed quenchers not only prevent oscillation, but also reduce the idle power consumption when the memory cells are not activated by wordline signals. Meanwhile, a large noise margin is provided such that the gain of the sense amplifier will not be reduced to avoid the oscillation. Hence, high-speed and low-power readout operations of the SRAMs are feasible.     

High-speed operation of a low-power 4-bit serial-to-parallel converter

This paper presents a high-speed low-power 4-bit superconducting serial-to-parallel converter (SPC) that has been demonstrated experimentally to operate at data rates up to 1 Giga-bits (Gb/s). The primary design goals for this device are high-speed operation, low-power dissipation, and high circuit yield for use as a core element in an address decoder or a demultiplexer. First, the circuit design and optimization are discussed. Simulated performance of the circuit shows proper operation at 20 Gb/s, with a discussion of its potential for use at even higher rates. The power dissipation is computed to be 28 /spl mu/W in continuous operation and the predicted within-wafer yield is 95%. Measured results are then given for data rates of 100 Mb/s and 1 Gb/s.     

光纤通道8B/10B编码的ASIC研究与设计

在目前的高速串行数据传输中广泛采用的是8B/10B编解码,为了达到简化实现结构,用于大规模集成电路的目的,研究了现有各种不同的8B/10B编解码的特点和内在相关性,并在此基础上介绍了用一种VHDL设计8B/1B编码逻辑描述的方法,将其设计成专用集成电路或嵌入到FPGA中,构成一个逻辑运算量小,速度快,可靠性高的IP核,最后给出在Altera公司软件平台Quartus Ⅱ上进行的EDA综合仿真结果。该测试结果为采用本方法设计不同速率的超高速编解码芯片奠定了基础。     

Advanced bipolar circuits

Advances in high-speed, low-power bipolar circuits aimed at achieving superior power-delay performance and load-driving capability over conventional ECL and NTL circuits are reviewed. The basic principles underlying power/speed improvement including charge-buffering, DC/AC-coupled active pull-down schemes, and complementary push-pull approaches, are examined. The utilization and combination of these basic principles to form various high-speed, low-power circuits in both n-p-n-only and complementary circuit configurations and the design tradeoffs of these circuits are discussed     

Fully boosted 64K dynamic RAM with automatic and self-refresh

A novel high-speed low-power 64K dynamic RAM with enough margin has been attained using a double polysilicon and 3-/spl mu/m process technologies. To obtain a low soft error rate below 1/spl times/10/SUP -6/ errors per device hour without sacrificing the high-speed and low-power operation, some novel approaches are proposed in the circuit and device designs. In particular, fully boosted circuits and the Hi-C cell structure with polysilicon bit line are designed to increase the margin of the single 5-V power supply 64K dynamic RAM. The fabricated device provides a typical access time of 90 ns and an operating power of 190 mW at 25/spl deg/C. Also, the design features of the automatic and self-refresh functions on the same chip are described.