基于Zigbee的船舶状态监控系统的设计与实现

针对现有的船舶监控系统布线复杂、成本较高、维护困难等问题,并结合Zigbee无线通信特点,提出并设计了一种基于Zigbee技术的船舶状态监控系统。采用CC2530为硬件核心,并基于Z-stack协议栈进行软件开发。阐述了系统的整体构架,设计了节点的硬件组成及软件流程等关键技术问题。实验结果表明,该系统在数据采集传输、功耗等方面的性能达到了系统设计的基本要求,可广泛在船舶监控等方面推广应用。     

Design of a DVB-T/H COFDM Receiver for Portable Video Applications [Topics in Circuits for Communications]

Mobile video services have generated a lot of interest recently. To reach a cost-effective solution, design trade-offs among system performance, hardware complexity, and power consumption must be considered in the early design phase of such applications. In this article, we present a system overview, simulation platform, and hardware design of a DVB-T/H baseband receiver. Starting with a design platform, several algorithms on both inner and outer receivers are developed to meet target system performance under different channels. Then, system architecture and related key modules are explored, taking into account both silicon area and power consumption. Finally, several design issues related to the integration of the proposed DVB-T/H inner and outer receivers are addressed.     

A soft radio architecture for reconfigurable platforms

While many soft/software radio architectures have been suggested and implemented, there remains a lack of a formal design methodology that can be used to design and implement these radios. This article presents a unified architecture for the design of soft radios on a reconfigurable platform called the layered radio architecture. The layered architecture makes it possible to incorporate all of the features of a software radio while minimizing complexity issues. The layered architecture also enables a methodology for incorporating changes and updates into the system. An example implementation of the layered architecture on actual hardware is presented     

Software radio architecture: a mathematical perspective

As the software radio makes its transition from research to practice, it becomes increasingly important to establish provable properties of the software radio architecture on which product developers and service providers can base technology insertion decisions. Establishing provable properties requires a mathematical perspective on the software radio architecture. This paper contributes to that perspective by critically reviewing the fundamental concept of the software radio, using mathematical models to characterize this rapidly emerging technology in the context of similar technologies like programmable digital radios. The software radio delivers dynamically defined services through programmable processing capacity that has the mathematical structure of the Turing machine. The bounded recursive functions, a subset of the total recursive functions, are shown to be the largest class of Turing-computable functions for which software radios exhibit provable stability in plug-and-play scenarios. Understanding the topological properties of the software radio architecture promotes plug-and-play applications and cost-effective reuse. Analysis of these topological properties yields a layered distributed virtual machine reference model and a set of architecture design principles for the software radio. These criteria may be useful in defining interfaces among hardware, middleware, and higher level software components that are needed for cost-effective software reuse     

Global open ethernet (GOE) system and its performance evaluation

This paper presents an overview of global open Ethernet (GOE) architecture as a cost-effective Ethernet-based virtual private network (VPN) solution, and discusses a hardware and software implementation of a prototype system. Three main approaches have been proposed for a VPN solution on metro-area network: resilient packet ring, Ethernet over multiprotocol label switching (EoMPLS), virtual bridged local area network-tag stacking (Q-in-Q). None of these schemes can satisfy the following requirements at the same time: network topology flexibility, affordable network functionalities, low equipment cost, and low operational cost. The proposed GOE system is designed to solve VPN management problems of these approaches with MPLS VPN functionality at a low cost of Ethernet-based solution. The key components of GOE are: 1) a novel GOE tag for high-speed switching and 2) a novel routing and protection module via per-destination multiple rapid spanning tree protocol (PD-MRSTP). Via the analytical performance evaluation of EoMPLS, Q-in-Q, and GOE, we show that the memory cost and the network utilization of GOE is two-three times smaller and 22% higher than the other approaches, respectively. We also have developed a GOE prototype system and obtained the following remarkable hardware and software performance results. The GOE core switch delivered 100% of theoretical maximum throughput (10 G) with zero packet loss even with the field programmable gate array platform, and its 10-G port density is 1.5 times denser than the best currently available products. The GOE switch using PD-MRSTP also delivered a significantly fast protection switching time (1.975 ms), which was significantly faster than legacy Ethernet switches. These performance evaluation results prove that the proposed GOE system can be used as a cost-effective high-performance Ethernet-based VPN solution.     

Hardware implementation perspectives of digital video watermarking algorithms

We consider hardware implementation aspects of the digital watermarking problem through the implementation of a well-known video watermarking algorithm called just another watermarking system (JAWS); we discuss the time and area constraints that must be satisfied by a successful hardware implementation. A hardware architecture that implements the algorithm under the constraints is then proposed. The architecture is analyzed to gain an understanding of the relationships between algorithmic features and implementation cost. Some general findings of this work that can be applied toward making algorithmic developments more amenable to hardware implementation are finally presented.     

软件无线电体系结构研究

软件无线电体系结构是实现软件无线电的具体设计结构，包括软件和硬件体系结构两方面，它们是软件无线电技术的核心之一。本文比较全面地描述了目前实用的软件无线电软硬件体系结构，提出了具体的划分方法，并比较了它们的性能，它们将对相关问题的研究起到一定借鉴作用。     

Hardware-software co-design of embedded systems [and prolog]

This paper surveys the design of embedded computer systems, which use software running on programmable computers to implement system functions. Creating an embedded computer system which meets its performance, cost, and design time goals is a hardware-software co-design problem-the design of the hardware and software components influence each other. This paper emphasizes a historical approach to show the relationships between well-understood design problems and the as-yet unsolved problems in co-design. We describe the relationship between hardware and software architecture in the early stages of embedded system design. We describe analysis techniques for hardware and software relevant to the architectural choices required for hardware-software co-design. We also describe design and synthesis techniques for co-design and related problems     

A PC-based software receiver using a novel front-end technology

Since the software radio concept was introduced, much progress has been made in the past few years in making it a reality. Many software radio based systems have been designed through the development efforts of both commercial and noncommercial organizations. While the term software radio has meant many things, the ultimate goal in software radio has been the realization of an agile radio that can transmit and receive signals at any carrier frequency using any protocol, all of which can be reprogrammed virtually instantaneously. Such a system places great demands on the limits of data converter and processor technologies since it requires real-time disposition of gigasamples of data produced by direct conversion of wireless signals into digital data. From a processing standpoint, the challenge in software radio is to exploit the three basic processor types-fixed architecture processors, FPGAs, and programmable DSPs/RISCs/CISCs-in such a way as to optimize the three-way trade-offs between speed, power dissipation, and programmability. With respect to the latter characteristic, the issues of high-level language interfaces, portability, and reprogramming speed must be considered. This article describes the architecture and operation of a PC-based software radio receiver. The development environment is a real-time PC-based platform that allows testing to be done in a simple manner using the main software functionality of a PC. The front-end of the receiver implemented in hardware represents a novel wideband design (bandwidth of up to 100 MHz centered at a carrier frequency of up to 2 GHz) that functionally converts wireless signals directly into a gigasample digital data stream in the receiver (and vice versa in the transmitter). This direct conversion approach shows the greatest promise in realizing the main goal of software radio     

A network processor‐based architecture for multi‐gigabit traffic analysis

The wide availability of cheap and effective commodity PC hardware has driven the development of versatile traffic monitoring software such as protocol analyzers, traffic characterizers and intrusion detection systems. Most of them are designed to run on general purpose architectures and are based on the well‐known libpcap API, which has rapidly become a de facto standard. Although many improvements have been applied to packet capturing software, it still suffers from several performance flaws, mainly due to the underlying hardware bottlenecks. To overcome these issues, this paper proposes a system architecture, which combines the high performance of a Network Processor card with the flexibility of software‐based solutions. It allows for removing most part of the hardware limitations exhibited by a purely PC‐based architecture, while preserving the full compliance to any software applications based on libpcap. In addition, the proposed system enables the use of monitoring applications at the wire speed, with the possibility of on‐the‐fly data processing. The system performance has been thoroughly assessed: the results show that it clearly outperforms the previous PC‐based solutions in terms of packet capturing power, while the timestamping accuracy is as good as that achieved by DAG cards. Copyright © 2009 John Wiley & Sons, Ltd.     

SDI接口数字监视设备的设计与实现

介绍了一种对SDV(串行数字视频)信号进行解码的设备设计方案，提出了该系统的总体构架，并对该系统的硬件设计、软件设计进行了全面的论述。设计的产品具有较高的性能价格比，已进入了推广阶段。     

基于嵌入式Linux平台的集群渲染系统设计实现

在计算机图形学的影视动漫产业中,3D图形渲染始终是影响制作周期和成本的主要因素。对于小型工作室或动漫企业而言,自行构建一个具有商业渲染能力的集群渲染系统,需要大量的成本投入和高端的技术支持。针对以上问题,采用常用智能设备和开源软硬件,提出了一种基于嵌入式Linux平台的集群渲染系统构建方案。主要包括软硬件选择、操作系统移植安装和配置、硬件架构搭建、制作3D场景文件进行渲染测试。测试结果验证了该系统的可行性,且其运行良好,不影响渲染质量。     

Maintenance Techniques in Distributed Communications Switching Systems

The reliability and maintainability design criteria that were a part of large central-control communication systems, have been combined to produce deferred maintenance concepts in fully distributed communication systems. Combining these concepts allows the achievement of a cost-effective life-cycle design for communication switching systems. In a hardware/software environment one should not separate hardware maintainability and software maintainability, nor separate the reliability and maintainability of the system. Reliability models are being developed that reflect a constant rate for transient faults and a decreasing rate for catastrophic faults. The relationship of software bugs to their number and type of manifestation is being defined. Designs for primarily non-attended system sites should include appropriate maintenance concepts in order to be cost effective. If two or more individual repairs can be made with each maintenance visit to a site, the total area maintenance staff can be reduced. Implementation of deferred maintenance techniques can raise the availability level of the services provided, especially for a distributed communication switching system. Several examples of practical techniques for developing deferred maintenance concepts are presented, and topics such as the manning versus non-manning of sites, the time of day effects on state diagrams, centralized maintenance, and computer modeling techniques are discussed. The current and potential maintainability concepts and analysis tools that are discussed in this paper can be used to develop cost-effective maintenance concepts as distributed systems become more prevalent.     

Coupling between knowledge-based and algorithmic methods

The integration of knowledge-based techniques with traditional algorithmic software is discussed. Typical problems in power system planning and operation are better solved when the two techniques are combined. Functional aspects of a hybrid problem solving strategy are described and illustrated by two examples from power system operation. Available methods for practical implementation are reviewed. Sample applications from the literature are used to illustrate different approaches to hardware and software integration. Some of these applications have been successfully integrated with existing systems in operational environments. Future energy management systems based on an open architecture are likely to make it easier to integrate knowledge-based systems. Still, software integration issues continue to be a challenge. Particular problems are: automation of complex tasks by intelligent coordination, development of highly flexible software organizational schemes, and methods for easy data exchange between applications based on different software paradigms     

A Lossless Data Compression and Decompression Algorithm and Its Hardware Architecture

In this paper, we propose a new two-stage hardware architecture that combines the features of both parallel dictionary LZW (PDLZW) and an approximated adaptive Huffman (AH) algorithms. In this architecture, an ordered list instead of the tree-based structure is used in the AH algorithm for speeding up the compression data rate. The resulting architecture shows that it not only outperforms the AH algorithm at the cost of only one-fourth the hardware resource but it is also competitive to the performance of LZW algorithm (compress). In addition, both compression and decompression rates of the proposed architecture are greater than those of the AH algorithm even in the case realized by software     

Deployment of Run-Time Reconfigurable Hardware Coprocessors Into Compute-Intensive Embedded Applications

Day after day, embedded systems add more compute-intensive applications inside their end products: cryptography or image and video processing are some examples found in leading markets like consumer electronics and automotive. To face up these ever-increasing computational demands, the use of hardware accelerators synthesized in field-programmable gate arrays (FPGA) lets achieve processing speedups of orders of magnitude versus their counterpart CPU-based software approaches. However, the inherent increment in physical resources penalizes in cost. To address this issue, dynamically reconfigurable hardware technology definitively reached its maturity. SRAM-based reconfigurable logic goes beyond the classical conception of static hardware resources distributed in space and held invariant for the entire application life cycle; it provides a new design abstraction featured by the temporal partitioning of such resources to promote their continuous reuse, reconfiguring them on the fly to play a different role in each instant. This new computing paradigm lets balance the design of embedded applications by partitioning their functionality in space and time—through a series of mutually-exclusive processing tasks synthesized multiplexed in time on the same set of resources—and achieving thus cost savings in both area and power metrics. However, the exploitation of this system versatility requires special attention to avoid performance degradation. Such technical aspects are addressed in this work intended to be a survey on reconfigurable hardware technology and aimed at defining an open, standard and cost-effective system architecture driven by flexible coprocessors instantiated on demand on reconfigurable resources of an FPGA. This concept fits well with the functional features demanded to many embedded applications today and its feasibility has been proved with a state-of-the-art commercial SRAM-based FPGA platform. The achieved results highlight dynamic partial reconfiguration as a potential technology to lead the next computing wave in the industry.     

DMB-T数字电视接收系统的研制

所介绍的DMB-T数字电视接收系统系基于USB2.0接口上,采用DMB-T电子调谐器、CY7C68013通用串行总线接口器件和计算机软件解码播放技术的系统.描述了所采用的系统硬件结构,并分析了软件结构.所设计的系统使用方便,结构简单,便于实现,成本低,且具有良好的市场前景.     

2D DWT VLSI architecture for wavelet image processing

A cost-effective VLSI architecture with separate data-paths and their corresponding filter structure is proposed for performing a two-dimensional discrete wavelet transform (2D DWT). Compared with the conventional 2D DWT VLSI architectures, the proposed semi-recursive 2D DWT VLSI architecture has minimum hardware cost, and optimised data-bus utilisation, scheduling control overhead and storage size     

基于GPS和GSM混合定位系统的设计与实现

本文叙述了基于GPS和GSM混合定位系统的设计和实现。介绍了基于GPS和GSM混合定位系统的系统结构及其优点。然后从移动定位终端出发,详细地介绍了定位终端的硬件设计结构,I^2C总线技术及软件结构,给出了硬件和软件的模块化设计思路。     

基于USB的DVB-T数字电视接收系统设计

本文所介绍的DVB-T地面数字电视接收系统基于USB2.0接口,采用DVB-T电子调谐器DT6034、通用串行总线接口器件ISP1581和计算机软件解码播放技术,描述了系统的硬件结构和软件结构.所设计的系统使用方便、结构简单、便于实现、成本低,且具有良好的市场前景.