通信LSI/VLSI工艺

本文介绍通信LSI/VLSI电路制作技术中目前比较通用的工艺。总的来说,通信电路工艺是以前LSI/VLSI22艺的继续和发展。文中论述的重点是那些和过去LSI/VLSI工艺不同的方面,而这些方面主要体现在模拟电路的制作工艺上。     

CMOS-双极管单片相容器件研究

本文报告了CMOS-双极管单片相容器件的初步研究结果。给出了这种相容器件的优值特性、结构设计和电路应用实例。指出CMOS-双极管单片相容器件技术对发展高性能模拟集成电路(HAIC)、大规模集成电路(LSI)和超大规模集成电路(VLSI)有积极意义。     

发展中的BiCMOS技术

BiCMOS技术将双极器件和CMOS器件有机结合起来，充分发挥它们各自长处，使其既具有双极电路高速、强驱动能力的优产、，又具有CMOS高集成度、低功耗的优声、，已成为LSI和VLSI电路的重要发展方向。本文论证了BiCMOS技术在亚微米领域中的发展及其器件性能，并阐述了该技术在高密度存储器中的应用，指出为了使我国集成电路大生产技术腾飞，在亚微米领域中发展BiCMOS技术有着特殊的意义。     

硅衬底中缺陷的控制和利用

衬底硅中缺陷的控制和利用对半导体器件,尤其是LSI、VLSI电路极为重要。本文报道了有关这方面研究的一些实验结果。与未经处理的硅片相比,用IG法处理过的硅片,其n+p结的漏电流和MOS产生寿命可分别改善1—3和1—2个数量级,而用CCG法处理过的二极管的合格率可提高将近2倍。为了满足LSI、VLSI电路对衬底质量提出日益苛刻的要求,作者认为应联合实行两种或多种缺陷控制方法。     

LSI高密度封装的类型

随着LSI和VLSI的飞速发展,LSI高密度封装技术变得越来越重要。本文叙述了高密度封装的类型,介绍了它们的一般结构,并提供了封装的外形标准。     

采用激光再结晶方法的SOI技术

绝缘层上的硅单晶生长(SOI)技术,是可能实现高性能、高可靠性CMOS—LSI或高性能薄膜晶体管固体显示等器件的新的半导体工艺技术。特别是它是制作新功能器件,或即将突破二维VLSI性能极限而实现三维电路器件的必不可少的技术。     

组装42个芯片的厚膜多层基板

<正> 一、序言 微电子组装技术的推广是组装技术的一次革命。它与LSI、VLSI技术相辅相成,互为补充,平行发展,以满足目前对电子设备小型化、轻量化、高可靠及高速度等要求。特别是在雷达、通讯及计算机等电子设备中,电路品种多,功能各异,往往需要将不同集成度的元器件组装在一起,才     

不需要IC经验的Mead-Conway设计方法

本文介绍了设计LSI/VLSI电路的最新技术——Mead—Conway设计法。Mead和Conway夫妇创立的集成系统设计技术以他们在1979年合写的教科书“集成系统导论”为代表,曾获美国《电子学》杂志1981年成果奖(见Electronics,Vol、54,No.21,Oct.1981,PP102—105)。该技术把系统级结构和器件级制造融为一体,以现代化的CAD技术为基础,把VLSI技术推向了一个新的里程碑。这对于没有集成电路设计经验的系统设计人员特别有益。 本文以通用异步接收机的设计为例,介绍了该项技术所涉及到的几个方面以及基本的设计过程。     

用于超高速数字和混合模拟/数字LSI/VLSI电路的自对准栅Ⅲ-Ⅴ族异质结构FET技术

报道了一种用于制作高速数字及混合模拟/数字LSI/VLSI集成电路的平面离子注入自对准栅技术。采用增强型(e-型)n~+-(Al,Ga)As/MODFET,超晶格MODFET及掺杂沟道异质结构场效应晶体管(DCHFET),实现了4位模-数转换器,2500门8×8乘法器/累加器和4500门16×16复数乘法器,其外延层采用的是分子束外延生长。利用标称栅长1μm的器件,已做出有实际电路结构的直接耦合场效应逻辑(DCFL)环形振荡器,其传播延迟为30ps/级,功耗为1.2mW/级。在LSI电路运用时,若加载一个2.5门的平均扇出并采用大约长1000μm的高密度互连线,则这些门的延迟为89ps/门,功耗为1.38mW/门。室温下,高性能的电压比较器电路在Nyquist模拟输入频率下的取样速率大于2.5GHz,静态滞后小于1mV。已做出工作频率高达2GHz的全函数4位A/D转换电路。据我们所知,这是迄今报道的应用MBE生长LSI异质结构FET技术制作的最大的数字和混合模拟/数字电路。     

E/D型HEMT DCFL倒相器

<正> 电子工业部第十三研究所于87年5月在国内首次研制成功HEMT数字IC的基本单元电路——E/D型HEMT DCFL倒相器。该电路具有器件数少、逻辑设计简单、速度快、功耗小等特点,因而特别适合于超高速、低功耗LSI/VLSI。采用中科院半导体提提供的MBE材料,其结构是在SI GaAs衬底上,依次生长     

Devices and circuits for bipolar (V)LSI

It is shown that bipolar circuits can continue to play an important role in high-performance LSI and VLSI circuits, because power supply voltages and logic swings can be minimized independently of dimensions, and because the speed degradation due to on-chip wiring capacitances is less severe than in MOSFET/MESFET types of circuit. General performance improvements (in speed and packing density) of logic gates are obtained by increasing transistor fT, and decreasing parasitic capacitances, series resistances and device areas, by using oxide isolation, self-aligned techniques and polysilicon electrodes. Fast switching diodes (such as Schottky barrier diodes and lateral polydiodes) improve the flexibility of circuit design. Logic circuits (such as I²L, LS, DTL, ISL, STL, ECL, and NTL), which already perform in LSI and VLSI circuits or are realistic proposals for them, are discussed.     

BiCMOS circuit technology for a 704 MHz ATM switch LSI

This paper describes BiCMOS level-converter circuits and clock circuits that increase VLSI interface speed to 1 GHz, and their application to a 704 MHz ATM switch LSI. An LSI with a high speed interface requires a BiCMOS multiplexer/demultiplexer (MUX/DEMUX) on the chip to reduce internal operation speed. A MUX/DEMUX with minimum power dissipation and a minimum pattern area can be designed using the proposed converter circuits. The converter circuits, using weakly cross-coupled CMOS inverters and a voltage regulator circuit, can convert signal levels between LCML and positive CMOS at a speed of 500 MHz. Data synchronization in the high speed region is ensured by a new BiCMOS clock circuit consisting of a pure ECL path and retiming circuits. The clock circuit reduces the chip latency fluctuation of the clock signal and absorbs the delay difference between the ECL clock and data through the CMOS circuits. A rerouting-Banyan (RRB) ATM switch, employing both the proposed converter circuits and the clock circuits, has been fabricated with 0.5 μm BiCMOS technology. The LSI, composed of CMOS 15 K gate logic, 8 Kb RAM, I Kb FIFO and ECL 1.6 K gate logic, achieved an operation speed of 704-MHz with power dissipation of 7.2 W     

The prospects for ultrahigh-speed VLSI GaAs digital logic

Recent advances in the state of GaAs integrated circuit fabrication technology have made possible the demonstration of ultrahigh performance (tau_{d} sim 100ps) GaAs digital IC's with up to 64 gate MSI circuit complexities and with gate areas and power dissipations sufficiently low to make VLSI circuits achievable. It is the purpose of this paper to evaluate, based on the current state of GaAs IC technology and the fundamental device physics involved, the prospects of achieving an ultrahigh-speed VLSI GaAs IC technology. The paper includes a performance comparison analysis of Si and GaAs FET's and switching circuits which indicates that, for equivalent speed-power product operation, GaAs IC's should be about six times faster than Si IC's. The state of the art in GaAs IC fabrication and logic circuit approaches is reviewed, with particular emphasis on those approaches which are LSI/VLSI compatible in power and density. The experimental performance results are compared for the leading GaAs logic circuit approaches, both for simple ring oscillators and for more complex sequential logic circuits (which have demonstrated equivalent gate delays as low astau_{d} = 110ps).     

A single-chip NMOS analog front-end LSI for modems

Presents a fully integrated analog front-end LSI chip which is an interface system between digital signal processors and existing analog telecommunication networks. The developed analog LSI chip includes many high level function blocks such as A/D and D/A converters with 11 bit resolution, various kinds of SCFs, an AGC circuit, an external control level adjuster, a carrier detector, and a zero crossing detector. Design techniques employed are mainly directed toward circuit size reductions. The LSI chip is fabricated in a 5 /spl mu/m line double polysilicon gate NMOS process. Chip size is 7.14/spl times/6.51 mm. The circuit operates on /spl plusmn/5 V power supplies. Typical power consumption is 270 mW. By using this analog front-end LSI chip and a digital signal processor, modern systems can be successfully constructed in a compact size.     

Digital communication devices

This paper discusses how codecs are used in PCM telecommunication circuits, and also how they can be used for alternative applications.The past developments and future trends of LSI telecommunication circuits are also discussed.     

LSI processing technology for planar GaAs integrated circuits

A planar GaAs integrated circuit (IC) fabrication technology capable of LSI complexity has been developed. The circuit and fabrication approaches were chosen to satisfy LSI requirements for high yield, high density, and low power. This technology utilizes Schottky-diode FET logic (SDFL) incorporating both high-speed switching diodes and 1-µ m GaAs MESFET's. Circuits are fabricated directly on semi-insulating GaAs using multiple localized implantations. Rapid progress in the development of this technology has already led to the successful demonstration of high-speed (tau_{d} sim 100ps) low-power (∼500 µW/gate) GaAs MSI (∼60-100 gates) circuits. Extension of the current MSI technology to the LSI/VLSI domain will depend critically on device yield which will be dictated by the GaAs material properties and by the fabrication processes used. The purpose of this paper is to describe a GaAs IC process technology which combines advanced planar device and multilevel interconnect structures with several LSI compatible processes including multiple localized ion implantations, reduction photolithography, plasma etching, reactive ion etching, and ion milling.     

大规模集成电路中的互连问题和微波技术

本文叙述了大规模和超大规模集成电路中当电路规模和工作速度增加时的互连问题,此时互连系统中出现的波效应将十分明显,并将影响集成电路的电性能。为对这种效应进行估算并和集成电路的整体设计相配合,必须与微波理论和方法相结合,本文对这一领域的研究工作进行了概括性的评述。     

Planar GaAs IC technology: Applications for digital LSI

This technology utilizes multiple localized ion implantations directly into semi-insulating GaAs substrates, with unimplanted areas providing isolation between circuit elements. This approach allows for high yield, high density circuits, with optimization of various types of devices (e.g., GaAs MESFETs, high-speed Schottky-barrier diodes, etc.) made possible by optimizing the implantation profile for each type of device. The application of this fabrication technology for high-speed, ultra low power digital integrated circuits using a new circuit approach called Schottky diode-FET logic (SDFL) is described. Experimental GaAS SDFL logic ICs with LSI/VLSI compatible power levels (200-500 /spl mu/W/gate) and circuit densities (<10/SUP -3/ mm/SUP 2//gate) have been fabricated.     

A high yield buried p-layer fabrication process for GaAs LSIcircuits

GaAs MESFETs for LSI and VLSI require high transconductance to drive large wiring loads, but they must also exhibit extremely good uniformity and reproducibility. To provide ion-implanted MESFETs that meet these conflicting needs, the authors developed a 0.7-μm buried p-layer (BP) multifunction self-aligned gate (MSAG) fabrication process which has demonstrated excellent yields for circuits of up to 5000 gates. Device and circuit performance has been studied as a function of BP implant dose. LSI circuit yield and performance have been characterized using 4×4-, 8×8-, 12×12-, 16×16-, and 20×20-bit parallel-array multipliers on the same die. A high-dose BP implant has resulted in σV_T as low as 8 mV over 3-in wafers and 20×20-bit multipliers with self-test yields of 61%. Measured worst-case multiplication times range from 870 ps for the 4×4-bit to 6.5 ns for the 20×20-bit multipliers, representing record speeds for these multipliers. The average gate delays for these multipliers are 51 to 67 ps, the fastest extracted gate delays reported for LSI circuits