Reducing MOSFET 1/f noise and power consumption by switched biasing

Switched biasing is proposed as a technique for reducing the 1/f noise in MOSFET's. Conventional techniques, such as chopping or correlated double sampling, reduce the effect of 1/f noise in electronic circuits, whereas the switched biasing technique reduces the 1/f noise itself. Whereas noise reduction techniques generally lead to more power consumption, switched biasing can reduce the power consumption. It exploits an intriguing physical effect: cycling a MOS transistor from strong inversion to accumulation reduces its intrinsic 1/f noise. As the 1/f noise is reduced at its physical roots, high frequency circuits, in which 1/f noise is being upconverted, can also benefit. This is demonstrated by applying switched biasing in a 0.8 μm CMOS sawtooth oscillator. By periodically switching off the bias currents, during time intervals that they are not contributing to the circuit operation, a reduction of the 1/f noise induced phase noise by more than 8 dB is achieved, while the power consumption is also reduced by 30%     

Micropower switched capacitor biquadratic cell

The implementation of the double correlated sampling noise reduction technique in conventional strays-insensitive switched capacitor biquad building blocks is described. The function is performed by an offset cancellation circuit which is incorporated into the structure without the use of any additional capacitor, only minor modifications in the switching topology, and one supplementary clock phase. Consequently, a significant reduction of the low-frequency (1/f) noise is made possible and the usual differential amplifiers may be replaced by simple inverting amplifiers operated in class AB, featuring high-speed, low-quiescent power dissipation and low noise. An experimental micropower SC biquadratic filter section designed for `leapfrog' or `follow-the-leader feedback' structures has been developed using high gain (>80 dB) CMOS push/pull inverting amplifiers together with a three-phase clocking sequence. The integrated circuit, implemented in a low-voltage Si-gate CMOS process, achieves excellent accuracy and less than 5 /spl mu/W power dissipation with a 32 kHz sampling rate and /spl plusmn/1.5 V supplies; dynamic range is 66 dB.     

Circuit techniques for reducing the effects of op-ampimperfections: autozeroing, correlated double sampling, and chopperstabilization

In linear IC's fabricated in a low-voltage CMOS technology, the reduction of the dynamic range due to the dc offset and low frequency noise of the amplifiers becomes increasingly significant. Also, the achievable amplifier gain is often quite low in such a technology, since cascoding may not be a practical circuit option due to the resulting reduction of the output signal swing. In this paper, some old and some new circuit techniques are described for the compensation of the amplifier's most important nonideal effects including the noise (mainly thermal and 1/f noise), the input-referred dc offset voltage as well as the finite gain resulting in a nonideal virtual ground at the input     

消除CMOS读出电路噪声方法研究

对红外焦平面阵列CMOS读出电路中几种常见的噪声及其抑制技术进行了分析和讨论,重点研究了消除读出电路噪声的新方法——双复位法。该方法克服了以往相关双取样的缺点,没有增加电路功耗和硅集成电路的复杂程度,只要电容参数选择合理,理论上能完全消除KTC噪声,而且对1／f噪声也起到抑制作用。     

Infrared focal plane array incorporating silicon IC processcompatible bolometer

A 128×128 element bolometer infrared image sensor using thin film titanium is proposed. The device is a monolithically integrated structure with a titanium bolometer detector located over a CMOS circuit that reads out the bolometer's signals. By employing a metallic material like titanium and refining the CMOS readout circuit, it is possible to minimize 1/f noise. It is demonstrated that the use of low 1/f noise material will help increase bias current and improve the S/N ratio. Since the fabrication process is silicon-process compatible, costs can be kept low     

一种新型低噪声高均匀性红外焦平面读出电路

针对非制冷微测辐射热计焦平面阵列,设计了一种低噪声、高均匀性的读出电路。该读出电路结合相关双采样技术和自归零技术,对固定图像噪声以及l/f噪声都能起到很好的抑制作用。目前,该电路已应用到160×120阵列的非制冷微测辐射热计焦平面上,并在0.5μm CMOS工艺下成功流片。测试结果表明,固定图像噪声仅为0.087 V,均方根噪声为256μV。     

Low Noise Readout Circuit for Biosensor SoC

Presented is a low noise interface circuit that is tuned to the needs of self-assembly monolayers biosensor SoC. The correlated double sampling（CDS） unit of the readout circuit can reduce 1/f noise, KTC noise and fixed noise of micro arrays effectively. The circuit is simulated in a 0.6 μm/level 7 standard CMOS process, and the simulated results show the output voltage has a good linearity with the transducing current of the micro arrays. This is a novel circuit including four amplifiers sharing a common half-circuit and the noise reducing CDS unit. It could be widely used for micro array biosensors.     

A CMOS chopper amplifier

A highly sensitive CMOS chopper amplifier for low-frequency applications is described. It is realized with a second-order low-pass selective amplifier using a continuous-time filtering technique. The circuit has been integrated in a 3-/spl mu/m p-well CMOS technology. The chopper amplifier DC grain is 38 dB with a 200-Hz bandwidth. The equivalent input noise is 63 nV//spl radic/Hz and free from 1/f noise. The input offset is below 5 /spl mu/V for a tuning error less than 1%. The amplifier consumes only 34 /spl mu/W.     

High-performance RF mixer and operational amplifier BiCMOS circuits using parasitic vertical bipolar transistor in CMOS technology

The electrical characteristics of the parasitic vertical NPN (V-NPN) BJT available in deep n-well 0.18-/spl mu/m CMOS technology are presented. It has about 20 of current gain, 7 V of collector-emitter breakdown voltage, 20 V of collector-base breakdown voltage, 40 V of Early voltage, about 2 GHz of cutoff frequency, and about 4 GHz of maximum oscillation frequency at room temperature. The corner frequency of 1/f noise is lower than 4 kHz at 0.5 mA of collector current. The double-balanced RF mixer using V-NPN shows almost free 1/f noise as well as an order of magnitude smaller dc offset compared with CMOS circuit and 12 dB flat gain almost up to the cutoff frequency. The V-NPN operational amplifier for baseband analog circuits has higher voltage gain and better input noise and input offset performance than the CMOS ones at the identical current. These circuits using V-NPN provide the possibility of high-performance direct conversion receiver implementation in CMOS technology.     

1/f noise synthesis model in discrete-time for circuit simulation

Flicker noise, popularly known as 1/f noise is a commonly observed phenomenon in semiconductor devices. To incorporate 1/f noise in circuit simulations, models are required to synthesize such noise in discrete time. This paper proposes a model based on the fact that 1/f processes belong to the class of statistically self-similar random processes. The model generates 1/f noise in the time domain (TD) with a simple white noise input and is parameterized by a quantity whose value can be adjusted to reflect the desired 1/f parameter, that is, the slope of the 1/f spectrum. It thus differs from most of the earlier modeling approaches, which were confined to the spectral domain. To verify fit between the model and actual 1/f noise measurements, experiments were conducted using discrete devices such as a PIN photodiode at various bias conditions and sampling frequencies. The noise synthesized by the model was found to provide a good match to the measurements. Furthermore, it is demonstrated that the proposed 1/f noise model can also be incorporated in circuit simulations as a noise current or noise voltage source, which was not feasible earlier with the conventional spectral domain representation. To validate the inclusion of 1/f noise in circuits as TD current or voltage, simulations were carried out on a CMOS ring oscillator and the clock jitter due to 1/f noise was investigated.     

A monolithically integrated three-axis accelerometer using CMOScompatible stress-sensitive differential amplifiers

In this paper, the development of a bulk-micromachined CMOS integrated three-axis accelerometer which includes analog signal conditioning circuits is presented. The accelerometer was designed to simplify the signal processing tasks by incorporating a set of circuits for three-axis signal conditioning. This approach resulted in a 25% reduction of the circuit area. Stress-sensitive differential amplifiers (SSDAs) have been used as signal transducers, because they can be conveniently formed in a small area. The sensitivity and resolution of the fabricated devices realized in 8×8 mm² die area were 192 mV/g and 0.024 g for Z-axis acceleration, and 23 mV/g and 0.23 g for X and Y axis acceleration, respectively. The electrical noise component in the analog CMOS circuits was reduced by using a chopper stabilization technique. It was observed that there is a proper chopping clock frequency range to maximize the noise reduction effect. The noise of the SSDA was found to be related with the characteristics of CMOS differential amplifiers used. Typical temperature coefficient of sensitivity was about -2000 ppm/°C, which could be reduced to -320 ppm/°C or less by selecting a proper bias condition     

CMOS technology for MS/RF SoC

Accelerated scaling of CMOS technology has contributed to remove otherwise fundamental barriers preempting its widespread application to mixed-signal/radio-frequency (MS/RF) segments. Improvements in device speed, matching, and minimum noise figure are all consistent with fundamental scaling trends. Other figures-of-merit such as linearity and 1/f noise do not scale favorably but are not considered to be roadblocks when viewed from a circuit design perspective. Furthermore, interconnect architectural scaling trends in logic technology have facilitated improvements in passive-component performance metrics. These improvements compounded with innovations in circuit design have made CMOS technology the primary choice for cost driven MS/RF applications. This paper reviews active and passive elements of CMOS MS/RF system-on-chip (SoC) technology from a scaling perspective. The paper also discusses the implications that physical phenomena such as mechanical stress and gate leakage as well as gate patterning have on technology definition and characterization.     

Principle of simple correlated double sampling and its reduced-area low-noise low-power circuit realization

In this paper a simple block diagram of the simple and low-power correlated double sampling (CDS) is proposed suppressing the readout noise of CMOS active pixel sensor such as the kT/C noise, the 1/f noise and the fixed pattern noise. The principle of the simple CDS is described, analyzed and simulated. Based on the simple and low-power CDS principle a reduced-area, low-power and low-noise CDS circuit for CMOS APS is realized. For one spur track of the conventional CDS has saved and the low-power single-ended difference pair is used to finish the difference and amplified function, the area of the pixel cell with proposed CDS is reduced by a factor of above 2. Based on the standard TSMC 0.6 μm process the Hspice simulation results show that the active pixel cell with proposed CDS achieves a low power dissipation of 73.96 μW, the noise bandwidth of about 100 kHz, and the total output noise voltage of less than \( 4.45\;{{\text{nV}} \mathord{\left/ {\vphantom {{\text{nV}} {\sqrt {\text{Hz}} }}} \right. \kern-\nulldelimiterspace} {\sqrt {\text{Hz}} }} \) in the noise bandwidth.     

A fully integrated 5.8 GHz U-NII band 0.18-/spl mu/m CMOS VCO

A fully integrated 5.8 GHz CMOS L-C tank voltage-controlled oscillator (VCO) using a 0.18-/spl mu/m 1P6M standard CMOS process for 5 GHz U-NII band WLAN application is presented. The VCO core circuit uses only PMOS to pursue a better phase noise performance since it has less 1/f noise than NMOS. The measurement is performed by using a FR-4 PCB test fixture. The output frequency of the VCO is from 5860 to 6026 MHz with a 166 MHz tuning range and the phase noise is -96.9 dBc/Hz at 300 kHz (or -110 dBc/Hz at 1 MHz) with V ctrl = 0 V. The power consumption of the VCO excluding buffer amplifiers is 8.1 mW at V/sub DD/ = 1.8 V and the output power is -4 dBm.     

A low noise interface circuit design of micro-machined gyroscope

The analyses of MEMS gyroscope interface circuit on thermal noise, 1/f noise and phase noise are made in this paper. A closed-loop differential driving circuit and a low-noise differential detecting circuit based on the high frequency modulation are designed to limit the noise. The interface chip is implemented in a standard 0.5 μ m CMOS process. The test results show that the resolution of sensitive capacity can reach to 6.47 × 10^-20 F at the bandwidth of 60 Hz. The measuring range is ± 200°/s and the nonlinearity is 310 ppm. The output noise density is 5.8°/(h·√Hz). The angular random walk (allen-variance) is 0.092°/√h and the bias instability is 2.63°/h.     

Low 1/f noise design of Hi-CMOS devices

Low-frequency noise characteristics of High-Performance CMOS(Hi-CMOS) devices were measured. It was found that the equivalent input noise power SVg,eqfor n-channel MOSFET's has a 1/fα spectrum (0.8 < α < 0.95) above 10 µA, even for sealed-down devices with channel lengths LGof 2 µm. The SVg,eqis clearly proportional to 1/Leffdown to 0.8 µm. The noise characteristics of p-channel and n-channel MOSFET's were compared. It was found that in Hi-CMOS devices, noise reduction in normally-off-type p-channel devices was obtained by light boron-ion implantations at doses below 10¹²cm^-2. The 1/f noise level of p-channel devices was reduced to 1/10- 1/20 that of n-channel devices. In n-channel devices, the low-frequency noise power is a slow increasing function of the drain current. In p-channel devices, on the other hand, a threshold current was observed at which the noise begins to increase rapidly. The results are discussed in this paper in relation to the theoretical model of 1/f noise. The device design for reducing 1/f noise in CMOS differential amplifiers is also examined.     

A voltage overscaled low-power digital filter IC

In this brief, we present an integrated circuit implementation of a low-power digital filter in 0.35-/spl mu/m 3.3-V CMOS process. The low-power technique combines voltage overscaling (VOS) and algorithmic noise tolerance (ANT) to push the limits of energy efficiency beyond that achievable by voltage scaling alone. VOS refers to scaling the supply voltage beyond the limit imposed by the throughput constraints. ANT is an algorithmic level error-control technique that is employed to restore the algorithmic performance degradation in terms of output signal-to-noise ratio (SNR) caused by VOS. Measured results indicate 40%-67% reduction in energy dissipation over optimally voltage-scaled systems with less than 1-dB loss in SNR for a wide range of filter bandwidths (0.05f/sub s/-0.25f/sub s/, where f/sub s/ is the sampling frequency).     

基于电流镜积分的红外探测器读出电路设计

详细分析了电流镜积分(CMI)读出电路的工作原理、设计过程和CMI结构的噪声,并用CSMC 0.5μm CMOS工艺对所设计的电路进行仿真和版图设计,仿真结果表明CMI结构在电源电压为5 V,积分电容为2 pF时能提供一个较大的电荷存储能力(6.25x107个电子);在光生电流为50 pA时,探测器偏压稳定在3.615...     

A low-noise amplifier with automatic gain control and anticlipping control in CMOS technology

A CMOS low-noise amplifier (LNA) with two variable gain ranges of 6 and 9 dB is presented. Variable gain is realized by using linearized MOS resistive circuits (MRCs) as voltage-controlled resistors. One of these resistors is located in the feedback loop of a transresistance output stage and the other is in the bias current generator of the transconductance input stage. Using compatible lateral bipolar transistors (CLBTs) in the fully differential transconductance input stage, the circuit takes advantage of the linear dependence of transconductance on bias current. The equivalent noise is 14 nV/ square root Hz and free from 1/f noise in the voice band. The circuit was integrated in a 2- mu m CMOS process and has an active area of 0.8 mm/sup 2/.<>     

Analysis of temporal noise in CMOS photodiode active pixel sensor

Temporal noise sets the fundamental limit on image sensor performance, especially under low illumination and in video applications. In a CCD image sensor, temporal noise is primarily due to the photodetector shot noise and the output amplifier thermal and 1/f noise. CMOS image sensors suffer from higher noise than CCDs due to the additional pixel and column amplifier transistor thermal and 1/f noise. Noise analysis is further complicated by the time-varying circuit models, the fact that the reset transistor operates in subthreshold during reset, and the nonlinearity of the charge to voltage conversion, which is becoming more pronounced as CMOS technology scales. The paper presents a detailed and rigorous analysis of temporal noise due to thermal and shot noise sources in CMOS active pixel sensor (APS) that takes into consideration these complicating factors. Performing time-domain analysis, instead of the more traditional frequency-domain analysis, we find that the reset noise power due to thermal noise is at most half of its commonly quoted kT/C value. This result is corroborated by several published experimental data including data presented in this paper. The lower reset noise, however, comes at the expense of image lag. We find that alternative reset methods such as overdriving the reset transistor gate or using a pMOS transistor can alleviate lag, but at the expense of doubling the reset noise power. We propose a new reset method that alleviates lag without increasing reset noise