Dynamic range improvement by narrow-channel effect suppression andsmear reduction technologies in small pixel IT-CCD image sensors

Technologies for narrow-channel effect suppression in photodiodes (PDs) and vertical CCDs (V-CCDs) and for smear reduction in PDs have been developed in order to improve dynamic range in small pixel interline-transfer CCD (IT-CCD) image sensors. The new technologies have been applied to a progressive-scan IT-CCD image sensor with 5 μm square pixels and have (1) increased the charge handling capability of its V-CCDs to 4500 electrons/V; (2) improved its smear value to -95 dB; and (3) increased the saturation charge of its PDs to 2.3×10⁴ electrons     

A 2/3-in 2 million pixel STACK-CCD HDTV imager

A 2/3-in optical format 2 M pixel STACK-CCD imager has been developed. The STACK-CCD imager, overlaid with an amorphous silicon photoconversion layer, realizes a large signal charge handling capability of 1.0×10⁵ electrons, a -140 dB smear noise and a 90 dB dynamic range with a newly introduced device configuration and its unique operation. The 5.0 μm(H)×5.2 μm(V) unit pixel imager with sufficiently low image lag has been realized by a novel bias charge injection scheme These device performances are the best ever achieved by a CCD HDTV imager. This is the first such imager satisfying the device performances required for a practical use 2/3-in 2 M pixel HDTV imager     

CMOS active pixel image sensors for highly integrated imagingsystems

A family of CMOS-based active pixel image sensors (APSs) that are inherently compatible with the integration of on-chip signal processing circuitry is reported. The image sensors were fabricated using commercially available 2-μm CMOS processes and both p-well and n-well implementations were explored. The arrays feature random access, 5-V operation and transistor-transistor logic (TTL) compatible control signals. Methods of on-chip suppression of fixed pattern noise to less than 0.1% saturation are demonstrated. The baseline design achieved a pixel size of 40 μm×40 μm with 26% fill-factor. Array sizes of 28×28 elements and 128×128 elements have been fabricated and characterized. Typical output conversion gain is 3.7 μV/e^- for the p-well devices and 6.5 μV/e^- for the n-well devices. Input referred read noise of 28 e^- rms corresponding to a dynamic range of 76 dB was achieved. Characterization of various photogate pixel designs and a photodiode design is reported. Photoresponse variations for different pixel designs are discussed     

Light-soaking effects on a-Si:H photodiodes deposited by thelaminar-flow photo-CVD method

A 2/3-in, 2-Mpixel, STACK-CCD imaging sensor has been developed for HDTV solid-state imagers. A new a-Si:H photo-conversion layer, fabricated by the laminar-flow photo-chemical-vapor-deposition method, is overlaid on the vertical CCD scanning circuitry in the sensor. The photodegradation behavior of a-Si:H photodiodes is investigated in terms of dark-current density, electron μτ product and transient photocurrent. These properties are degraded as a result of light-induced defects in the a-Si:H layer. The Staeblar-Wronski constants, C_sw , are estimated to be 7.5×10^-7 at no voltage and 1.1×10^-7 at a reverse voltage of 6 V applied to the photodiode during light-soaking with an AM-1 lamp. The lifetime of the photodiode is determined by the degradation of the transient photocurrent, and is estimated to be about 2.2×10⁸ h for 1 lx light exposure. The lifetime is considered to be improved compared with that of previous-type photodiode reported before (1.5×10⁷ h for 1.5 lx light exposure) and clearly satisfies the needs for practical use of the device     

A 1-mm 50 k-Pixel IT CCD image sensor for miniature camera system

The world's smallest image sensor (1-mm 50 k-pixel interline CCD) has been developed. It features an extremely small pixel of 4×4 μm² integration of a V_sub adjust circuit, and a packageless assembly of a chip provided microlens. The resultant chip size and the assembled device outer size are 1.1(H)×1.34(V) mm and 1.2(H)×1.5(V) mm, respectively     

A 1/3-in 410000-pixel CCD image sensor with feedback field-plateamplifier

The design considerations and performance of a 1/3-in format 410000-pixel interline transfer charge coupled device (CCD) (IL-CCD) image sensor are described. Some techniques have been introduced in order to shrink the pixel size to 6.4(H)×7.5(V) μm without any deterioration in dynamic range and, signal-to-noise (S/N) ratio. The photodiode structure is designed to reduce the knee effect so as to avoid an overflow of the vertical CCD (V-CCD) register up to 500 times the saturating illumination. A depleted-well CCD structure is introduced to maintain the maximum charge-handling capability of 92000 electrons/packet in the V-CCD register, and high enough transfer efficiency of the horizontal CCD (H-CCD) registers with 5-V_p-p pulse driving. A feedback field-plate amplifier (FFPA) is introduced to raise the sensitivity of the output amplifier to 16.2 μV/electron in order to obtain a large enough S/N ratio to the background noise of the peripheral circuits in a video camera     

A 128×128-pixel standard-CMOS image sensor with electronicshutter

A 128×128-pixel image sensor with a 20 s-10^-4 s electronic shutter has been integrated in a 1.2-μm digital CMOS technology. The pixel cell consists of four PMOS transistors and a photodiode with antiblooming suppression. Each pixel measures 24 μm by 24 μm and has a fill factor of 25%. Current is used to transfer pixel signals to the column readout amplifiers in order to minimize voltage swings on the highly capacitive column lines. Correlated double sampling is used to reduce intracolumn fixed pattern noise. The saturation voltage is 470 mV. The peak output signal to noise ratio is 45 dB, and the optical dynamic range is 56 dB. The frame transfer rate is 1.7 ms per frame     

A 1/4-inch 330 K square pixel progressive scan CMOS active pixelimage sensor

In this paper, three pixel structures have been studied as candidates to realize high density CMOS active pixel sensors. A novel cell structure, the “I-shaped” cell, in which the active regions are formed along a straight line, has been proposed for high-packing density devices. The “I-shaped” cells can realize minimum cell area of 16F², 14F², and 14F ² (F: design rule) for three-transistor-type, two-transistor-type, and one-transistor-type pixels, respectively. A 1/4-inch format progressive scan CMOS active pixel sensor with 640 (H)×480 (V) pixels has been fabricated using a 0.6-μm CMOS process. The sensor operates with 5.0 V single power supply, and power consumption is below 30 mW     

Sensitivity of CMOS based imagers and scaling perspectives

CMOS based imagers are beginning to compete against CCDs in many areas of the consumer market because of their system-on-a-chip capability. Sensitivity, however, is a main weakness of CMOS imagers and enhancements and deviations from standard CMOS processes are necessary to keep up sensitivity with downscaled process generations. In the introductory section several definitions for the sensitivity of image sensors are reviewed with regard to their potential to allow meaningful comparison of different detector structures. In the main section, the standard CMOS sensor architecture is compared to detector structures designed to improve the sensitivity, namely the photogate (PG), the pinned photodiode (PPD) and the thin film on ASIC (TFA) approach. The latter uses a vertical integration of the photodiode on top of the pixel transistors. A careful analysis of the relevant electrical, optical and technological parameters and many previously published experimental data for different imagers reveals that only the PPD and the TFA enhancements provide satisfactory sensitivity and withstand scaling down to 0.18 μ processes. Due to the higher fill factor and the higher quantum efficiency TFA provides significantly better values than PPD. The radiometric sensitivity of a 5 μm×5 μm TFA pixel is found to amount to 11.9 V/(μ/cm²) for a 0.25 μm process and 27.5 V/(μJ/cm²) for a 0.18 μm process     

A single-chip CMOS APS camera with direct frame difference output

A complementary metal-oxide-semiconductor (CMOS) active pixel sensor (APS) camera chip with direct frame difference output is reported in this paper. The proposed APS cell circuit has in-pixel storage for previous frame image data so that the current frame image and the previous frame image can be read out simultaneously in differential mode. The signal swing of the pixel circuit is maximized for low supply voltage operation. The pixel circuit occupies 32.2×32.2 μm² of chip area with a fill factor of 33%. A 128×98 element prototype camera chip with an on-chip 8-bit analog-to-digital converter has been fabricated in a 0.5-μm double-poly double-metal CMOS process and successfully tested. The camera chip consumes 56 mW at 30 frames/s with 3.3 V power supply     

Monolithic CCD imagers in HgCdTe

Charge-coupled device (CCD) infrared detector arrays in 5 μm cutoff HgCdTe have been demonstrated for low background applications. These fully monolithic 128 by 28 element CCD arrays incorporate time-delay-and-integrate (TDI) detection, serial readout multiplexing, charge-to-voltage conversion and buffer amplification in the HgCdTe detector chip. Operation of these devices at 77 K have produced average detectivity values exceeding 3×10¹³ cm-Hz^1/2/W for a background flux level of 6×10¹² photon/cm²-sec in the 3.0 μm to 5.5 μm spectral band. Overall performance data indicates the monolithic HgCdTe CCD to be a promising alternative to present midwave infrared hybrid focal plane array technology     

A new p-channel MOSFET with large-tilt-angle implanted punchthroughstopper (LATIPS)

A buried-channel p-MOSFET with a large-tile-angle implanted punchthrough stopper (LATIPS) is described. In this device the n⁺ LATIPS region was successfully realized adjacent to the p⁺ source/drain, even without a sidewall spacer, by taking advantage of the n⁺ large-tilt-angle implant. In spite of the relatively deep p⁺ junction of 0.2-μm depth and the low n-well concentration of 1×10¹⁶ cm^-3, the 0.5-μm LATIPS device (with corresponding channel length of 0.3 μm) achieved high punchthrough resistance, e.g. a low subthreshold swing of 95 mV/decade with a high transconductance of 135 mS/mm     

A pixel size shrinkage of amplified MOS imager with two-line mixing

This paper describes a pixel size shrinkage of an amplified MOS image sensor (AMI). We have developed a new circuit technique to achieve the reduction of a pixel size while realizing vertical two-line mixing and high sensitivity. A 1/4-in format 250-k pixel image sensor was developed using a 0.8-μm CMOS process. The difference from the conventional CMOS process is an additional layer of ion-implantation process. The power supply voltages of this imager are 4 and 6 V. The dynamic range of 75 dB, the sensitivity of 1.8 μA/Ix, and the smear noise of less than -120 dB have been attained for the pixel size of 7.2 (H)×5.6 (V) μm². Although the measured fixed pattern noise ratio (FPN) of this imager is -55 dB, analysis with a test chip shows that FPN can be improved by 2 dB by adopting a suitable gate length for amplifier and resetting MOSFET, respectively     

A 1 K×1 K high dynamic range CMOS image sensor with on-chipprogrammable region-of-interest readout

An integrated 1024×1024 CMOS image sensor with programmable region-of-interest (ROI) readout and multiexposure technique has been developed and successfully tested. Size and position of the ROI is programmed based on multiples of a minimum readout kernel of 32×32 pixels. Since the dynamic range of the irradiance normally exceeds the electrical dynamic range of the imager that can be covered using a single integration time, a multiexposure technique has been implemented in the imager. Subsequent sensor images are acquired using different integration times and recomputed to form a single composite image. A newly developed algorithm performing the recomputation is presented. The chip has been realized in a 0.5-μm n-well standard CMOS process. The pixel pitch is 10 μm² and the total chip area is 164 mm ²     

A small pixel CMD image sensor

A charge modulation device (CMD) imager with pixel dimensions of 7.3 μm(H)×7.6 μm(V) was designed, fabricated, and examined. These pixel dimensions are suitable for an HDTV imager with a 1-in image format. The optical aperture ratio is 34%. The effective number of pixels in the imager is 660 horizontal and 492 vertical. The saturation signal current is 17 μA/pixel at an exposure of 1 lx-s with good linearity of photoconversion characteristics. The peak of its spectral response occurs at a wavelength of 575 nm. The blooming suppression ratio of the CMD was measured to be -122 dB. The sensor produces a high-quality image with no degradation in spatial resolution and no image lag. These features show that the CMD imager is eminently suitable for a further high-resolution imager sensor     

A 1/3-in 510(H)×492(V) CCD image sensor with mirror imagefunction

A 1/3-in optical format 510(H)×492(V) interline charge-coupled-device (CCD) image sensor with a mirror-image function has been developed. To realize both a normal image and a mirror image, the horizontal shift register (H-CCD) is transferred forward and backward by a four-electrode, quasi-two-phase clock drive. The unit cell size is 9.6(H)×7.5(V) μm². An on-chip microlens has been developed to achieve a sensitivity of 28 mV/lx, which is higher than that of the conventional 1/2-in device. The hole accumulation diode (HAD) sensor used has the advantage of low dark current, negligibly small lag, high blooming suppression, and a variable-speed electronic shutter. The smear reduction level is -83 dB. Horizontal resolution of 330 TV lines is obtained     

Ultra-sensitive autocorrelation of 1.5 μm light with singlephoton counting silicon avalanche photodiode

1.5 μm two-photon absorption in a single photon counting silicon avalanche photodiode at record continuous-wave levels below 100 μW is reported. Autocorrelation of a 10 GHz, 1.67 picosecond pulse-train using this device demonstrates 1.5 × 10^-3 (mW)² peak-power times average-power sensitivity without the use of lock-in detection     

A photodiode cell for applications to position and motionestimation sensors

An optical cell has been designed and fabricated using standard digital 1.6 μm CMOS technology. It has been designed for applications to sensors where the image acquisition time of fast moving objects or documents is of primary importance. The cell contains a photodiode working in storage mode and a shielded MOS capacitor acting as analog frame buffer. A chip prototype containing 64 linear arrays of 64 cells whose size is 36×36 μm² has been tested and measurements have proved the functionality down to microsecond-range of exposure times. By virtue of the proposed read-out technique, the sensor architecture provides simultaneous image acquisition of irregular moving objects allowing precise detection of position and motion     

Fabrication of p-i-n photodiodes on LPE-grown substrates

Epitaxial growth of a thick heavily doped silicon layer on a highly resistive silicon wafer by the yo-yo solute feeding method and its application to p-i-n photodiodes are discussed. An abrupt transition of the impurity profile is obtained between the n⁺ layer (1.95×10¹⁹ cm^-3, 450 μm) and the n^- layer (7.0×10¹¹ cm^-3, 80 μm). It is possible to use the thick intrinsic layers as the active region of power devices     

A new cryogenic CMOS readout structure for infrared focal planearray

A new current readout structure for the infrared (IR) focal-plane-array (FPA), called the switch-current integration (SCI) structure, is presented in this paper. By applying the share-buffered direct-injection (SBDI) biasing technique and off focal-plane-array (off-FPA) integration capacitor structure, a high-performance readout interface circuit for the IR FPA is realized with a pixel size of 50×50 μm². Moreover, the correlated double sampling (CDS) stage and dynamic discharging output stage are utilized to improve noise and speed performance of the readout structure under low power dissipation. In experimental SCI readout chip has been designed and fabricated in 0.8-μm double-poly-double-metal (DPDM) n-well CMOS technology. The measurement results of the fabricated readout chip at 77 K with 4 and 8 V supply voltages have successfully verified both the readout function and the performance improvement. The fabricated chip has a maximum charge capacity of 1.12×10⁸ electrons, a maximum transimpedance of 1×10⁹ Ω, and an active power dissipation of 30 mW. The proposed CMOS SCI structure can be applied to various cryogenic IR FPA's