A discrete spatial model for wafer yield prediction

Yield analysis is one of the key concerns in the fabrication of semiconductor wafers. An effective yield analysis model will contribute to production planning and control, cost reductions and the enhanced competitiveness of enterprises. In this article, we propose a novel discrete spatial model based on defect data on wafer maps for analyzing and predicting wafer yields at different chip locations. More specifically, based on a Bayesian framework, we propose a hierarchical generalized linear mixed model, which incorporates both global trends and spatially correlated effects to characterize wafer yields with clustered defects. Both real and simulated data are used to validate the performance of the proposed model. The experimental results show that the newly proposed model offers an improved fit to spatially correlated wafer map data.     

A novel hybrid resampling for semiconductor wafer defect bin classification

Generally, defective dies on semiconductor wafer maps tend to form spatial clusters in distinguishable patterns which contain crucial information on specific problems of equipment or process, thus it is highly important to identify and classify diverse defect patterns accurately. However, in practice, there exists a serious class imbalance problem, that is, the number of the defective dies on semiconductor wafer maps is usually much smaller than that of the non-defective dies. In various machine learning applications, a typical classification algorithm is, however, developed under the assumption that the number of instances for each class is nearly balanced. If the conventional classification algorithm is applied to a class imbalanced dataset, it may lead to incorrect classification results and degrade the reliability of the classification algorithm. In this research, we consider the semiconductor wafer defect bin data combined with wafer warpage information and propose a new hybrid resampling algorithm to improve performance of classifiers. From the experimental analysis, we show that the proposed algorithm provides better classification performance compared to other data preprocessing methods regardless of classification models.     

Boosted Stacking Ensemble Machine Learning Method for Wafer Map Pattern Classification

Recently, machine learning-based technologies have been developed to automate the classification of wafer map defect patterns during semiconductor manufacturing. The existing approaches used in the wafer map pattern classification include directly learning the image through a convolution neural network and applying the ensemble method after extracting image features. This study aims to classify wafer map defects more effectively and derive robust algorithms even for datasets with insufficient defect patterns. First, the number of defects during the actual process may be limited. Therefore, insufficient data are generated using convolutional auto-encoder (CAE), and the expanded data are verified using the evaluation technique of structural similarity index measure (SSIM). After extracting handcrafted features, a boosted stacking ensemble model that integrates the four base-level classifiers with the extreme gradient boosting classifier as a meta-level classifier is designed and built for training the model based on the expanded data for final prediction. Since the proposed algorithm shows better performance than those of existing ensemble classifiers even for insufficient defect patterns, the results of this study will contribute to improving the product quality and yield of the actual semiconductor manufacturing process.     

Defect pattern recognition on wafers using convolutional neural networks

In semiconductor manufacturing, wafer testing is performed to ensure the performance of each product after wafer fabrication. The wafer map is used to visualize the color-coded wafer test results based on the locations. The defects on the wafer map may be randomly distributed or form clustered patterns. The various clustered defect patterns are usually caused by assignable faults. The identification of the patterns is thus important to provide valuable hints for the root causes diagnosis. Solving the problems helps improve the manufacturing processes and reduce costs. In this study, we present a novel convolutional neural network (CNN)–based method to automatically recognize the defect pattern on wafer maps. Our method uses polar mapping before the training of CNN to transform the circular wafer map into a matrix, which can be processed within CNN architecture. This procedure also reduces the input size and solves variations in wafer sizes and die sizes. To eliminate the effects of rotation, we apply data augmentation in the training of CNN. Experiments using the real-world dataset prove the effectiveness and superiority of our method.     

Multi-step ART1 algorithm for recognition of defect patterns on semiconductor wafers

The integrated circuits (ICs) on wafers are highly vulnerable to defects generated during the semiconductor manufacturing process. The spatial patterns of locally clustered defects are likely to contain information related to the defect generating mechanism. For the purpose of yield management, we propose a multi-step adaptive resonance theory (ART1) algorithm in order to accurately recognise the defect patterns scattered over a wafer. The proposed algorithm consists of a new similarity measure, based on the p-norm ratio and run-length encoding technique and pre-processing procedure: the variable resolution array and zooming strategy. The performance of the algorithm is evaluated based on the statistical models for four types of simulated defect patterns, each of which typically occurs during fabrication of ICs: random patterns by a spatial homogeneous Poisson process, ellipsoid patterns by a multivariate normal, curvilinear patterns by a principal curve, and ring patterns by a spherical shell. Computational testing results show that the proposed algorithm provides high accuracy and robustness in detecting IC defects, regardless of the types of defect patterns residing on the wafer.     

A model-based clustering approach to the recognition of the spatial defect patterns produced during semiconductor fabrication

Defects on semiconductor wafers tend to cluster and the spatial defect patterns of these defect clusters contain valuable information about potential problems in the manufacturing processes. This study proposes a model-based clustering algorithm for automatic spatial defect recognition on semiconductor wafers. A mixture model is proposed to model the distributions of defects on wafer surfaces. The proposed algorithm can find the number of defect clusters and identify the pattern of each cluster automatically. It is capable of detecting defect clusters with linear patterns, curvilinear patterns and ellipsoidal patterns. Promising results have been obtained from simulation studies.     

Simultaneous order-lot pegging and wafer release planning for semiconductor wafer fabrication facilities

In semiconductor wafer fabrication facilities, order-lot pegging is the process of assigning wafer lots to orders and meeting the due dates of orders is considered one of the most important operational issues. In many cases of order-lot pegging, some orders cannot be fulfilled with the current wafers in the lots being processed, necessitating the release of additional new wafer lots into the wafer fabrication facility. In this paper, we propose a simultaneous decision model for order-lot pegging and wafer release planning in semiconductor wafer fabrication facilities, and develop a Lagrangian heuristic for solving the model. The results of computational experiments conducted using randomly generated problem instances that mimic actual field data from a Korea semiconductor wafer fabrication facility indicate that the performance of the Lagrangian heuristic is superior to that of a practical greedy algorithm for practical-sized problem instances. The results also point to how sensitivity analysis can be used to answer important managerial questions for effective management of the semiconductor wafer fabrication process.     

Wafer yield prediction using derived spatial variables

Unreliable chips tend to form spatial clusters on semiconductor wafers. The spatial patterns of these defects are largely reflected in functional testing results. However, the spatial cluster information of unreliable chips has not been fully used to predict the performance in field use in the literature. This paper proposes a novel wafer yield prediction model that incorporates the spatial clustering information in functional testing. Fused LASSO is first adopted to derive variables based on the spatial distribution of defect clusters. Then, a logistic regression model is used to predict the final yield (ratio of chips that remain functional until expected lifetime) with derived spatial covariates and functional testing values. The proposed model is evaluated both on real production wafers and in an extensive simulation study. The results show that by explicitly considering the characteristics of defect clusters, our proposed model provides improved performance compared to existing methods. Moreover, the cross‐validation experiments prove that our approach is capable of using historical data to predict yield on newly produced wafers.     

A hierarchical model for characterising spatial wafer variations

Silicon wafers are commonly used materials in the semiconductor manufacturing industry. Their geometric quality directly affects the production cost and yield. Therefore, improvement in the quality of wafers is critical for meeting the current competitive market needs. Conventional summary metrics such as total thickness variation, bow and warp can neither fully reflect the local variability within each wafer nor provide useful insight for root cause diagnosis and quality improvement. The advancement of sensing technology enables two-dimensional (2D) data mapping to characterise the geometric shapes of wafers, which provides more information than summary metrics. The objective of this research is to develop a statistical model to characterise the thickness variation of wafers based on 2D data maps. Specifically, the thickness variation of wafers is decomposed into macro-scale and micro-scale variations, which are modelled as a cubic curve and a first-order intrinsic Gaussian Markov random field, respectively. The models can successfully capture both the macro-scale mean trend and the micro-scale local variation, with important engineering implications for process monitoring, fault diagnosis and run-to-run control. A practical case study from a wafer manufacturing process is performed to show the effectiveness of the proposed methodology.     

Using in-line equipment condition and yield information for maintenance scheduling and dispatching in semiconductor wafer fabs

Yield is one of the most important measures of manufacturing performance in the semiconductor industry, and equipment condition plays a critical role in determining yield. Researchers and practitioners alike have traditionally treated the problems of equipment maintenance scheduling and production dispatching independently, ignoring how equipment condition may affect different product types or families in different ways. This paper addresses the problem of how to schedule maintenance and production for a multiple-product, multiple-stage production system. The problem is based on the situation found in semiconductor wafer fabrication where the equipment condition deteriorates over time, and this condition affects the yield of the production process. We extend a recently developed Markov decision process model of a single-stage system to account for the fact that semiconductor wafers have multiple layers and thus make repeated visits to each workstation. We then propose a methodology by which the single-stage results can be applied in a multi-stage system. Using a simulation model of a four-station wafer fab, we test the policies generated by the model against a variety of other maintenance and dispatching policy combinations. The results indicate that our method provides substantial improvements over traditional methods and performs better as the diversity of the product set increases. In the scenarios examined, the reward earned using the policies from the combined production and maintenance scheduling method was an average of more than 70° higher than the reward earned using other policy combinations such as a fixed-state maintenance policy and a first-come, first-serve dispatching policy.     

Economic in-line inspection sampling strategy with learning effects

This paper presents an innovative approach to a wafer inspection strategy that incorporates learning dynamics in semiconductor manufacturing factories. Using the data from fabrication lines (fabs) we demonstrate algorithms for computing the sampling strategy in terms of the percentage of wafers to sample for a process in different phases of a product life cycle. The average selling price and wafer starts per weeks are considered in the model. The paper provides an optimal solution methodology and concludes that the learning benefits of quality control activities may achieve the most cost-effective operations.     

In Situ Monitoring of Photoresist Thickness Uniformity of a Rotating Wafer in Lithography

The coating of the photoresist on the semiconductor substrate is a common process in lithography sequence. It is important to monitor the uniformity of the photoresist thickness across the substrate as the nonuniformity in photoresist thickness leads to variations in the linewidth/critical dimension (CD). In this paper, we propose a simple in situ photoresist thickness monitoring system. Our approach involves the integration of a single spectrometer to measure the photoresist thickness contour on the wafer during the spin-coating step or the edge-bead removal step. We note that the existing approaches in the monitoring of photoresist thickness are for the cases of nonrotating wafers. Our proposed approach also does not require extra processing steps compared with offline tools, which require the wafer to be moved from the processing equipment to the metrology tool. The experimental results are compared with an offline ellipsometer: the worst-case error is found to be less than 1%.      

Automatic identification of spatial defect patterns for semiconductor manufacturing

This research proposes an on-line diagnosis system based on denoising and clustering techniques to identify spatial defect patterns for semiconductor manufacturing. Today, even with highly automated and precisely monitored facilities used in a near dust-free clean room and operated with well-trained process engineers, the occurrence of spatial signatures on the wafer still cannot be avoided. Typical defect patterns shown on the wafer, including edge ring, linear scratch, zone type and mixed type, usually contain important information for quality engineers to remove their root causes of failures. In this paper, a spatial filter is simultaneously used to judge whether the input data contains any systematic cluster and to extract it from the noisy input. Then, an integrated clustering scheme combining fuzzy C means (FCM) with hierarchical linkage is adopted to separate various types of defect patterns. Furthermore, a decision tree based on two cluster features (convexity and eigenvalue ratio) is applied to a separated pattern to provide decision support for quality engineers. Experimental results show that both real dataset and synthetic dataset have been successfully extracted and classified. More importantly, the proposed method has potential to be further applied to other industries, such as liquid crystal display (LCD) and plasma display panel (PDP).     

A machine learning approach to yield management in semiconductor manufacturing

Yield improvement is one of the most important topics in semiconductor manufacturing. Traditional statistical methods are no longer feasible nor efficient, if possible, in analysing the vast amounts of data in a modern semiconductor manufacturing process. For instance, a typical wafer fabrication process has more than 1000 process parameters to record on a single wafer and one manufacturing plant may produce tens of thousands wafers a day. Traditional approaches have limits in extracting the full benefits of the data. Therefore, the manufacturing data is poorly exploited even in the most sophisticated processes. Now it is widely accepted that machine learning techniques can provide powerful tools for continuous quality improvement in a large and complex process such as semiconductor manufacturing. In this work, memory based reasoning (MBR) and neural network (NN) learning are combined for yield improvement and an integrated framework is proposed for a yield management system based on hybrid machine learning techniques. In this hybrid system of NN and MBR, the feature weight set which is calculated from the trained neural network plays the core role in connecting both learning strategies and the explanation on prediction can be given by obtaining and presenting the most similar examples from the case base. The proposed system has advantages in typical semiconductor manufacturing problems such as scalability to large datasets, high dimensions and adaptability to dynamic situations.     

Efficiently extracting frequent patterns from continuous uncertain data

Uncertain frequent pattern mining has been much discussed in recent decades. It is widely used in various fields and helps analysts to comprehend the deep meaning of collected data from the frequencies of items. In past studies, researchers have focused on discrete models. However, a discrete model only explains the presence of combinations of items without giving specific data intervals. To compensate for the drawbacks of discrete models, we focus on continuous uncertain data and improve a continuous uncertain frequent tree for the extraction of frequent patterns, notably time costs. Attribute overlapping usually causes the high time cost in the extraction phase. To avoid long branches in the tree, two approaches are proposed. The first approach is to name each attribute at given level with an uncertain frequent pattern. By using links and reshaping the uncertain frequency tree, the number of combinations decreases. The second approach is called uncertain frequent pattern map transforming. It uses a discrete transformation to decrease the time cost. In experiments, our two approaches were compared with different mainstream approaches. According to the results, our approaches not only cost less time to explore frequent patterns but also exhibited high accuracy for continuous uncertain data.     

Markov Random Fields in Pattern Recognition for Semiconductor Manufacturing

Under the most general conditions of an anisotropic Markov random field, we model the two-dimensional spatial distribution of microchips on a silicon wafer. The proposed model improves on its predecessors as it stipulates the spatial correlation of different strengths in all eight directions. Its canonical parameters represent the intensity of failures, main effects, and interactions of neighboring chips. Explicit forms of conditional distributions are derived, and maximum pseudo-likelihood estimates of canonical parameters are obtained. This numerical characteristic summarizes general patterns of clusters of failing chips on a wafer, capturing their size, shape, direction, density, and thickness. It is used to classify incoming wafers to known root-cause categories by matching them to the closest pattern.     

Monocrystalline silicon used for integrated circuits: still on the way

With the rapid development of semiconductor technology, highly integrated circuits (ICs) and future nano-scale devices require large diameter and defect-free monocrystalline silicon wafers. The ongoing innovation from silicon materials is one of the driving forces in future micro and nano-technologies. In this work, the recent developments in the controlling of large diameter silicon crystal growth processes, the improvement of material features by co-doping with the intend-introduced impurities, and the progress of defect engineered silicon wafers (epitaxial silicon wafer, strained silicon, silicon on insulator) are reviewed. It is proposed that the silicon manufacturing infrastructure could still meet the increasingly stringent requirements arising from ULSI circuits and will expand Moore’s law into a couple of decades.     

A run-to-run controller for product surface quality improvement

In semiconductor manufacturing, the surface quality of silicon wafers has a significant impact on the subsequent processes that produce devices using the wafers as a component. The surface quality of a wafer is characterised by a two-dimensional (2-D) data structure: the geometric requirement for the wafer surface is smooth and flat and the thickness should fall within certain specification limits. Therefore, both low deviation and high uniformity are desirable for control over the wafer quality. In this work, we develop a run-to-run control algorithm for improving wafer quality. Considering the unique 2-D data structure, we first construct a model that encompasses the spatial correlation of the observations on the wafer surface to link the wafer quality with the process variables, and subsequently develop a recursive algorithm to generate optimal set points for the controllable factors. More specifically, a Gaussian-Kriging model is used to characterise the spatial dependence of the thickness measures of the wafer and a recursive least square method is employed to update the estimates of the model parameters. The performance of the new controller is studied via simulation and compared with existing controllers, which demonstrates that the newly proposed controller can effectively reduce the surface variations of the silicon wafers.     

Yield prediction via spatial modeling of clustered defect counts across a wafer map

In this paper we propose spatial modeling approaches for clustered defects observed using an Integrated Circuit (IC) wafer map. We use the spatial location of each IC chip on the wafer as a covariate for the corresponding defect count listed in the wafer map. Our models are based on a Poisson regression, a negative binomial regression, and Zero-Inflated Poisson (ZIP) regression. Analysis results indicate that yield prediction can be greatly improved by capturing the spatial distribution of defects across the wafer map. In particular, the ZIP model with spatial covariates shows considerable promise as a yield model since it additionally models zero-defective chips. The modeling procedures are tested using a practical example.     

Data transformation in SPC for semiconductor machinery control: A case of monitoring particles

Yield is an important indicator of productivity in semiconductor manufacturing. In the complex manufacturing process, the particles on wafers inevitably cause defects, which may result in chip failure and thus reduce yield. Semiconductor manufacturers initially use wafer testing to control the machine for the number of particles. This machinery control procedure aims to detect any unusual condition of machines, reduce defects in actual wafer production and thus improve yield. In practice, the distribution of particles does not usually follow a Poisson distribution, which causes an overly high rate of false alarms in applying the c-chart. Consequently, the semiconductor machinery cannot be appropriately controlled by the number of particles on machines. This paper primarily combines data transformation with the control chart based on a Neyman type-A distribution to develop a machinery control procedure applicable to semiconductor machinery. The proposed approach monitors the number of particles on the testing wafer of machines. A semiconductor company in Taiwan in the Hsinchu Science Based Industrial Park demonstrated the feasibility of the proposed method through the implementation of several machines. The implementation results indicated that the occurrence of false alarms declined extensively from 20% to 4%.