Impact of die-to-die and within-die parameter fluctuations on themaximum clock frequency distribution for gigascale integration

A model describing the maximum clock frequency (FMAX) distribution of a microprocessor is derived and compared with wafer sort data for a recent 0.25-μm microprocessor. The model agrees closely with measured data in mean, variance, and shape. Results demonstrate that within-die fluctuations primarily impact the FMAX mean and die-to-die fluctuations determine the majority of the FMAX variance. Employing rigorously derived device and circuit models, the impact of die-to-die and within-die parameter fluctuations on future FMAX distributions is forecast for the 180, 130, 100, 70, and 50-nm technology generations. Model predictions reveal that systematic within-die fluctuations impose the largest performance degradation resulting from parameter fluctuations. Assuming a 3σ channel length deviation of 20%, projections for the 50-nm technology generation indicate that essentially a generation of performance gain can be lost due to systematic within-die fluctuations. Key insights from this work elucidate the recommendations that manufacturing process controls be targeted specifically toward sources of systematic within-die fluctuations, and the development of new circuit design methodologies be aimed at suppressing the effect of within-die parameter fluctuations     

基于ARM的嵌入式计算机系统的低功耗设计与实现

嵌入式计算机系统被广泛应用于便携式和移动性较强的产品中,而这些产品的低功耗设计的目标是在满足用户对性能需求的前提下,尽可能降低系统的能耗,延长设备的待机时间[1].基于ARM处理器的嵌入式计算机系统主要通过低功耗微处理器选择、接口驱动电路的设计、电源供给电路设计、动态电源管理等来实现系统的低功耗.该系统已经在产品应用,系统性能稳定,功耗很小.     

基于CAN总线的接口电路设计

文中介绍了CAN总线的主要性能及特点,CAN总线在实际工业应用中的总体结构,同时给出了CAN总线协议转换器的硬件设计方法和通信协议.主要研究了CAN总线接口电路设计,所设计的总线接口电路由微处理器、CAN控制器、CAN,总线收发器组成,并且详细介绍了CAN控制器、CAN收发器的功能以及CAN总线接口的硬件电路和硬件条件下的软件设计,为后续CAN总线接口电路的应用打下了基础.     

干式电力变压器振动信号调理电路的设计

基于振动法的变压器状态监测系统通过安装在变压器器身上的振动传感器来测量运行中的变压器的振动信号,通过对干式电力变压器振动特性的分析,得出振动量的量化特性,方便了调理电路的参数设计.振动信号的调理过程,采用一种内装IC的加速度传感器YD35D,适合用来测量电力变压器的振动信号,通过电荷放大器、增益放大电路和滤波电路将加速度信号转变成微处理器可采集的0-5v的模拟电压量,较为详细地介绍了信号处理各部分电路的设计及电阻电容的参数计算公式.通过电子电路仿真软件Multisim对电路参数进行了合理配置,仿真结果表明系统的信号幅度控制合理,滤波效果明显,电路设计具有实际应用价值.     

一种微处理器控制电子引信电路的设计

针对机械式引信系统可靠性低、精度差,以及模拟电子引信系统抗干扰性差等问题,研究设计了一种微处理器控制的电子引信系统.文章以一种多功能引信电路为例,介绍了微处理器控制引信系统的设计及工艺制造.样品的试验结果和使用情况表明,该设计方案切实可行,安全可靠;参数修改、调整灵活便捷;设计思路新颖,并具有推广性.     

基于AT91RM9200微处理器的最小系统设计

AT91RM9200是Atmel公司生产的基于ARM920T核的高性能、低功耗的16/32位RISC(精简指令集计算机)微处理器,主要应用于工业控制方面。文中介绍了AT91RM9200型ARM9微处理器和基于该处理器的最小嵌入式系统的硬件设计,采用模块化的设计方法,并给出了最小系统中电源、晶振电路、复位电路、存储器模块、JTAG、UART等各主要模块的外围应用电路及其选型,最后给出了简单的硬件调试方法和结果。用户根据最小系统的设计方案进行适当增加便可轻易地开发出适合自己的嵌入式系统。     

单片机在微型氧气机中的应用

采用PSA技术分离制氧的微型氧气机广泛应用于医疗保健等场合，其电气控制线路非常适合使用单片机技术来实现。本文分析了PSA制氧装王的工作过程，给出了单片机控制电路的硬件设计与软件设计方案。试制结果表明，该控制方案是有效的。     

An embedded 32-b microprocessor core for low-power andhigh-performance applications

An embedded RISC microprocessor core fabricated in a six-layer metal 0.18-μm CMOS process implementing the ARM^TM V.5TE instruction set is described. The core described is the first implementation of the Intel XScale Microarchitecture^TM. The microprocessor core, which includes caches, memory management units, and a bus controller, comprises a hard-embedded block 16.77 mm² in size. The implementation is primarily custom logic in a variety of circuit styles. The processor dissipates 450 mW at 1.3 V, 600 MHz, and scales between 55 mW at 0.7 V, 200 MHz, and 900 mW at 1.65 V 800 MHz. Architectural performance is 1000 MIPS at 800 MHz with efficiency ranging from over 850 MIPS/W at 1.65 V to over 4500 MIPS/W at 0.75 V. Architectural and circuit design approaches for low power and high performance are described and measured results from the initial implementation are shown. The first implementation VLSI chip has a 3.3-V pin interface and supports a 0.75-1.65-V core voltage range     

Design of a 32 b monolithic microprocessor based on GaAs HMESFETtechnology

This paper examines the design of a 32-b GaAs Fast RISC microprocessor (F-RISC/I). F-RISC/I is a single chip GaAs Heterojunction MESFET (HMESFET) processor targeted for implementation on a multichip module (MCM) together with cache memories. The CPU architecture, circuit design. Implementation, and testing are optimized for a seven-stage instruction pipeline implemented with GaAs super-buffered FET logic (SBFL). We have been able to verify novel GaAs SBFL standard cells and compare measured CPU performance with performance estimates based on circuit and device models. The prototype 32-b microprocessor has been implemented using an automated standard cell approach because of time constraints and fabricated using an experimental process by Rockwell International. The CPU chip integrates 92340 transistors on a 7×7 mm² die and dissipates 6.13 W at 180 MHz. Test results from a prototype fabrication run have demonstrated the operation of the ALU, the program counter, and the register file with delays below 6, 5, and 3.4 ns, respectively. The successful modeling and verification indicate that a 0.5 μm HMESFET implementation of F-RISC/I could achieve a peak performance of 350 MHz. The wiring delays account for 42% of the critical path delay     

一种MLS地面静态标校测角接收机的设计与实现

从嵌入式系统高性能、低功耗、低成本特点出发，结合嵌入式 MLS 测角接收机的设计理念，开展了基于 ARM 微处理器的 MLS 测角接收机研制，详细介绍了硬件电路设计、信号处理软件设计和交互界面设计。测试表明，研制的 MLS 测角接收机功能、性能满足设计要求。     

基于LPC2210的LED显示屏控制系统设计

当LED显示器采用8位/16位微处理器时,存在运行速度慢、寻址能力弱和功耗大等问题。文中采用32位ARM7微处理器LPC2210为核心控制器件,完成LED显示屏控制系统的设计。系统采用可扩展、模块化设计,以LED显示屏的显示电路和ARM微处理器控制电路为核心,并通过LPC2210微处理器自带的锁相环（PLL）,对系统进行倍频设计,有效提高了系统的可扩展性。通过对各模块的调度可方便实现点阵LED屏以双色、多样化方式显示各种信息,也可通过简单的级联实现屏的扩展。     

High-performance microprocessor architectures

Over the past few years, microprocessor designs have undergone an evolution process shaped largely by improvements in LSI circuit technology and experiences gained from the very large user community. By and large, most microprocessors have internal architectures that are patterned after classical CPU structures. This trend is changing rapidly. High-performance LSI microprocessors are emerging at a slow but steady pace, with architectural features borrowed from larger and more powerful computers. This paper examines aspects of pipelined concurrency and microprogramming as applied to LSI microprocessors, for the purpose of enhancing performance.     

The design of the microarchitecture of UltraSPARC-I

The realization of a high performance modern microprocessor involves hundreds of person-years of conception, logic design, circuit design, layout drawing, etc. In order to leverage effectively the 5-10 millions of transistors available, careful microarchitecture tradeoff analysis must be performed. This paper describes not only the microarchitecture of UltraSPARC-I, a 167 MHz 64-b four-way superscalar processor, but more importantly it presents the analysis and tradeoffs that were made “en route” to the final chip. Among several issues, the in-order execution model is compared with alternatives, variations of the issue-width of the machine as well as the number of functional units are described, subtle features that are part of the memory hierarchy are explained, and the advantages of the packet-switched interconnect are exposed     

A 433-MHz 64-b quad-issue RISC microprocessor

A quad-issue custom VLSI microprocessor is described. This microprocessor implements the Alpha architecture and achieves an estimated performance of 13.3 SPECint9S and 18.4 SPECfp95 at 433 MHz. The 9.6 million transistor die measures 14.4 mm×14.5 mm, and is fabricated in a 0.35-μm, four-metal layer CMOS process. This chip dissipates less than 25 W at 433 MHz using a 2.0 V internal power supply. The design was leveraged from a prior 300-MHz, 3.3-V, 0.50-μm CMOS design. It includes several significant architectural enhancements and required circuit solutions for operation at 2.0 V. The chip will operate at nominal internal power supply voltages up to 2.5 V allowing improved performance at the cost of increased power consumption. At 2.5 V, the chip operates at 500 MHz and delivers 15.4 SPECint95 (est) and 21.1 SPECfp95 (est). This paper describes the chip implementation details and the strategy for efficiently migrating the existing design to the 0.35-μm technology     

A 0.25-μm, 600-MHz, 1.5-V, fully depleted SOI CMOS 64-bitmicroprocessor

A 0.25-μm, four-layer-metal, 1.5-V, 600-MHz, fully depleted (FD) silicon-on-insulator (SOI) CMOS 64-bit ALPHA1 microprocessor integrating 9.66 million transistors on a 209-mm² silicon die has been developed leveraging the existing bulk design. FD-SOI technology is used because it has better immunity for dynamic leakage current than partially depleted SOI in high speed dynamic circuits without body contact. C-V characteristics of metal-oxide-silicon-oxide-silicon with and without source-drain junctions are described to explain the behavior of FD-SOI transistor. Race, speed, and dynamic stability have been simulated to reassure the circuit operation. Key process features are shallow trench isolation, 4-nm gate oxide, 30-nm co-silicide, 46-nm silicon film, and 200-nm buried oxide. The FD-SOI microprocessor runs 30% faster than that of bulk, and it passes the reliability and system test     

基于Mega8单片机的CAN总线智能节点设计

智能节点能通过节点电路中的微处理器对CAN控制器编程设置工作方式I、D地址、波特率等参数,实现对网络上的信息接收和发送,他主要由微处理器和可编程的CAN控制器组成。以AVR系列8位单片机Mega8和Philips CAN控制器SJA1000为基础,设计了Mega8单片机与CAN总线的智能节点接口电路,并给出了详细的接口电路原理图和软件设计流程图。实验证明,此设计有效地优化了以传统8位微处理器为核心的节点电路,增强了所在系统的稳定性和节点通信的可靠性。     

Microprocessor control of a transistorized induction heating power supply

This paper describes the incorporation of a microprocessor based power controller into a transistorized induction heating power supply. The use of the system is illustrated by the implementation of circuit protection and power control procedures. In the design, emphasis has been placed on the efficient use of the microprocessor, a high level of interference immunity within the system, and the provision of a fault monitoring system so that the performance of the unit can be assessed continuously.     

可编程器件Microblaze的应用与实现

MicroBlaze是基于Xilinx公司FPGA 的微处理器IP核,可以利用其便捷性优化嵌入式系统设计,同时简化硬件电路,提高系统性能。     

A 150 MHz 0.6 μm BiCMOS superscalar microprocessor

An implementation of the Pentium microprocessor architecture in 0.6 μm BiCMOS technology is described. Power dissipation is reduced and performance is enhanced over the previous generation. Processor features, implementation technology, and circuit techniques are discussed. An internal clock rate of 150 MHz is achieved at 3.7 V and -55°C     

一种基于单片机的透光率检测仪的设计和测试

透光率的检测涉及民用和科研的许多方面。文章报告了一个基于单片机的透光率检测仪的设计和测试。它具有电路结构简单、光路调节方便等优点,可应用于某些科研实验中透光率的检测。