Hot-carrier-induced degradation in p-channel LDD MOSFET's

When the p-channel MOSFET is stressed near the maximum substrate current Isub, the lifetime t (5-percent increase in the transconductance) followstI_{sub} = A(I_{sub}/I_{d})^{-n}, with n = 2.0. A simple electron trapping model is proposed to explain the observed power law relationship. The current ratioI_{sub}/I_{d}and the maximum channel electric field decrease with increasing stress time, which is consistent with electron trapping in the oxide during the stress.     

Hot-carrier drifts in submicrometer p-channel MOSFET's

Hot-carrier-induced shifts in p-channel MOSFET operating characteristics have been observed down to drain voltages of - 6 V. Cases are discussed in which p-MOSFET's show up to two orders of magnitude larger degradation than corresponding n-MOSFET's. The shifts include current and threshold voltage increases. From dependences on stress gate voltage, stress drain voltage, time, and substrate current, the hot-carrier origin of the shifts is specified in detail.     

Hot-carrier effects in Hydrogen-passivated p-channel polycrystalline-Si MOSFET's

The dependence of hot-carrier effects on channel length and stress-bias voltage in hydrogen-passivated accumulation-mode p-channel polycrystalline-Si MOSFET's operating in the saturation region has been studied, Before stress, these devices exhibit a minimum value of current at VGS≈ 0 V but as VGSincreases above 0 V, they show an increase in (leakage) current due to field-enhanced generation of carriers near the drain. After stress, the current at VGS≈ 0 V increases slightly with respect to its pre-stress value. However, the current then monotonically decreases as VGSincreases above 0 V unlike the situation before stress. No change in reverse mode (source and drain reversed) characteristics and no change in the ON-state (VGS< 0 V) forward-mode characteristic was observed after stress. These observations are shown to be due to hot-carrier-induced acceptor-type interface states near the drain in forward-mode operation.     

Mobility degradation in very thin Oxide p-channel MOSFET's

The effective hole mobility in large-area p-channel MOSFET's decreases systematically over a wide range of oxide fields as the gate oxide thickness decreases from 240 to 31 Å. A scattering mechanism based on the variations of the gate-charge-induced Coulomb scattering potential in the channel resulting from gate oxide thickness and/or structural fluctuations over the gate area is proposed to explain the results.     

Effects of hot-carrier trapping in n- and p-channel MOSFET's

Detailed measurements of hot-carrier gate current and its trapping effects were studied on both n- and p-channel MOSFET's down to submicrometer channel lengths. Comparison of the measurements for these two types of devices is made. No hot-hole gate current or hot-hole trapping was detected in p-channel MOSFET's. A hot-electron gate current is present not only in n-channel MOSFET's, but also in p-channel MOSFET's where the current is increased by hot-electron trapping. By trapping hot electrons uniformly over the channel in n-MOSFET's, it was shown that hot-electron trapping produces only negative oxide charge without generating interface traps.     

Anomalous radiation effect in p-channel MOSFET's under electron irradiation

An anomalous shift in the gate threshold voltage of high-transconductance p-channel MOSFET's has been observed during exposure to space-like radiation of 2 × 10¹²electrons/cm²that is two and one half to three times its saturation value at 2 × 10¹⁴electrons/cm²and is five to seven times its pre-irradiation value.     

Comparison of characteristics of n-channel and p-channel MOSFET's for VLSI's

A comparison of device characteristics of n-channel and p-channel MOSFET's is made from the overall viewpoint of VLSI construction. Hot-carrier-related device degradation of device reliability, as well as effective mobility, is elaborately measured for devices having effective channel lengths of 0.5-5 µm. From these experiments, it is found that hot-electron injection due to impact ionization at the drain, rather than "lucky hot holes," imposes a new constraint on submicrometer p-channel device design, though p-channel devices have been reported to have much less trouble with hot-carrier effects than n-channel devices do. Additionally, p-channel devices are found to surpass n-channel devices in device reliability in that they have a highest applicable voltage BVDCthat is more than two times as high as for n-channel devices. It is also experimentally confirmed that the effective hole mobility approaches the effective electron mobility when effective channel lengthL_{eff} < 0.5µm. These significant characteristics of p-channel devices imply that p-channel devices have important advantages over n-channel devices for realization of sophisitcated VLSI's with submicrometer dimensions. It is also shown that hot holes, which may create surface states or trap centers, play an important role in such hot-carrier-induced device degradation as transconductance degradation.     

Subhalf-micrometer p-channel MOSFET's with 3.5-nm gate Oxide fabricated using X-ray lithography

Subhalf-micrometer p-channel MOSFET's with ultra-thin gate oxide (3.5 nm) have been fabricated using X-ray lithography and electron cyclotron resonance (ECR) plasma etching. The fabricated MOSFET's with 0.2-µm channel lengths show long-channel behavior and extremely high (200 mS/mm) transconductance.     

Measurements of residual defects and 1/f noise in ion-implanted p-channel MOSFET's

This paper describes the measurements of excess noise and residual defects of extremely low concentrations (<1 × 10⁹cm^-2) in ion-implanted p-channel MOSFET's. The activation energy and the density of the residual defects after high-temperature annealing were measured using a transient capacitance technique. The test FET's were ion-implanted with fluences of 5 × 10¹¹to 4 × 10¹²using³¹p⁺,¹¹B⁺, or²⁸Si⁺species. A post-implant anneal was carried out in an N2or an Ar ambient for 20 min at various temperatures. For¹¹B⁺-implanted MOSFET's after annealing above 1000°C, a high residual defect concentration was observed near the conduction band edge; whereas after annealing the defect density as a result of²⁸Si⁺or³¹p⁺implantation was equal to that of control MOSFET's. The density-of-state data agree with the equilibrium measurements of excess (1/f) noise power. The excess noise was measured as a function of the drain current. The distribution of1/fnoise power versus potential minimum of holes in the equilibrium condition is similar to that of interface state density. In nonequilibrium operation, a reduction of excess noise was achieved owing to the presence of buried channel created by ion implant.     

Experimental characterization of gold-doped infrared-sensing MOSFET's

The operation of a new type of infrared photon detector is described. This device is a gold-doped n-channel MOSFET that employs impurity photoionization to modulate its drain-to-source conductance. A simple mathematical model is developed whereby the infrared-sensing MOSFET (IRFET) can be analyzed, and experimental results that verify the model are provided. The near-infrared, i.e., wavelengths from 1.38 to 3.54 µm, response of gold impurity centers in the space-charge region behind the strong surface inversion layer of a MOSFET is shown to correspond to the characteristics observed previously by other authors for the gold centers in bulk silicon. A static read-only memory capability and high responsivity, typically 4 mW/µJ, are the most significant IRFET characteristics. Applications in large-scale-integrated imaging arrays are anticipated.     

Experimental characterization of circuits for controlledprogramming of floating-gate MOSFET's

This paper presents the results of measurements performed on test structures implementing circuits for controlled erase of floating gate MOSFET's. The obtained results show that, with cells fabricated using standard technology, the obtained performance is sufficiently good to allow use in analog applications. The circuit has been demonstrated to be robust with respect to variations of the programming pulse characteristics and to partially compensate cell aging effects on the threshold window. This latter feature is particularly interesting for digital applications because it allows the reduction of the window margin, thus improving memory endurance     

Experimental evidence for quantum mechanical narrow channel effectin ultra-narrow MOSFET's

The authors describe a new narrow channel effect by quantum mechanical effects in ultra-narrow MOSFET's. Threshold voltage increase is observed at room temperature in ultra-narrow MOSFET's whose channel width is less than 10 nm. This result is in excellent agreement with simulation that takes account of quantum confinement in the silicon narrow channel, indicating that the increase in threshold voltage is caused by the quantum mechanical narrow channel effect     

Single-device-well MOSFET's

A novel MOSFET structure based on merging a surface enhancement-type device and a buried depletion-type device in a Single Device Well (SDW) is described. The SDW MOSFET structure utilizes the inherent two-dimensional geometry of a MOSFET device well to obtain two devices perpendicular to each other, having the same gate, thereby utilizing the hitherto nonutilized volume of the well. The two perpendicular currents of the devices in the merged structure are analyzed. An analytical model is developed and circuit CAD simulations are performed. A test chip is fabricated and the structure performance is evaluated. Some circuit examples are given.     

Reliability evaluation on sense-switch p-channel flash

In this paper,the reliability of sense-switch p-channel flash is evaluated extensively.The endurance result indicates that the p-channel flash could be programmed and erased for more than 10 000 cycles;the room temperature read stress shows negligible influence on the p-channel flash cell;high temperature data retention at 150℃is extrapolated to be about 5 years and 53 years corresponding to 30％and 40％degradation in the drive current,respectively.Moreover,the electrical para-meters of the p-channel flash at different operation temperature are found to be less affected.All the results above indicate that the sense-switch p-channel flash is suitable to be used as the configuration cell in flash-based FPGA.     

Gate-self-aligned p-channel germanium MISFETs

The authors have fabricated the first gate-self-aligned germanium MISFETs and have obtained record transconductance for germanium FETs. The devices fabricated are p-channel, inversion-mode germanium MISFETs. A germanium-oxynitride gate dielectric is used and aluminum gates, serve as the mask for self-aligned source and drain implants. A maximum room-temperature transconductance of 104 mS/mm was measured for a 0.6-μm gate length. A hole inversion channel mobility of 640 cm² /V-s was calculated using transconductance and capacitance data from long-channel devices. This large hole channel mobility suggests that germanium may be an attractive candidate for CMOS technology     

Parameters influencing far infrared videodetection with submicron-size Schottky diodes

The voltage responsivity of videodetectors using submicron GaAs Schottky diodes has been investigated in the 0.7–3.7 THz range. Incident submillimeter power level, DC bias and video-load influences are discussed within the framework of existing theories. Various diodes types differing in semiconductor parameter values as well as junction geometries are compared. The submillimeter frequency response is studied and interpreted in terms of plasma resonance effects in the epilayer.     

MOSFET's on Au-diffused high-resistivity Si substrates

Si MOSFET's on Au-diffused high-resistivity substrates were fabricated and their electrical properties were investigated. At 80 K, the current leakage between the source and drain of both n- and p-channel devices decreased below 10^-10A, and the devices exhibited normally-off behaviors. Au concentrations (N) in Si substrates as a function of diffusion temperature Tdiffwas determined from the change in the threshold voltage.Nversus Tdiffthus obtained is in fairly good agreement with that obtained by other methods. Dependence of effective mobility on Tdiffwas investigated in the form of a MOS device. The effective mobility decreased with increasing Tdiff, and it became clear that the diffusion temperature must be lower than about 700°C to obtain semi-insulating substrates with reasonably high carrier mobility. A C-MOS inverter was fabricated using an Au-diffused Si substrate, where no isolation wells were needed, in operation at low temperatures.     

GaAs microwave MOSFET's

GaAs microwave metal-oxide-semiconductor field-effect transistors (MOSFET's) with plasma-grown native oxides as gate insulator have been fabricated using a low-temperature magnetically controlled plasma-oxidation technique. A small-signal enhancement device with the gate length of 2.0 µm has demonstrated useful unilateral power gains in the 2-8-GHz frequency range. A maximum frequency of oscillation in the enhancement device is 13 GHz. This is the highest in all enhancement-mode GaAs devices reported up to this time. A medium-power depletion device with the gate length of 1.8 µm has the maximum frequency of oscillation of 22 GHz. This value is 10 percent larger than that of the best analogous metal-semiconductor field-effect transistor (MESFET). The intrinsic current-gain cutoff frequency for the depletion MOSFET is 4.5 GHz which is 22 percent higher than that of the MESFET. The superiority of the depletion MOSFET in the small-signal microwave performance over the MESFET results from the smaller gate parasitic capacitance in the MOSFET as compared to the MESFET. The depletion MOSFET has produced 0.4-W output power at 6.5 GHz as a Class A amplifier. Quite a large frequency dispersion of transconductance is observed in the enhancement MOSFET at a frequency range between 10 and 100 kHz and attributed to interface states. The effect of the interface states does not severely restrict the microwave-frequency capabilities of the enhancement MOSFET as well as the depletion MOSFET since the interface states are unable to follow the input-signal variations at high frequencies.     

IGFET circuit performance-n-channel versus p-channel

The n-channel insulated-gate field-effect transistor offers a factor of 2 to 3.4 mobility advantage (depending on crystal orientation and substrate doping level) over p-channel devices. In addition, several advantages result from the fact that the work function difference between an aluminum gate and the silicon substrate is about -0.8 volt for a p substrate compared with about zero for an n substrate. In particular, this results in a low threshold voltage that allows the use of a substrate bias to adjust the threshold voltage over a useful design range resulting in an added flexibility in choice of thresholds and substrate doping, a reduction in the effect of source-substrate bias on device threshold, decreased junction capacitance, and larger parasitic thick-oxide thresholds for a given insulator thickness. The speed, power, and density advantages of the n-channel device are illustrated for logic and memory circuits using representative n- and p-channel device designs.