A fast block-based nonlinear decoding algorithm for /spl Sigma//spl Delta/ modulators

Previous work has established that the digital output of a /spl Sigma//spl Delta/ modulator as an A/D converter contains more information about the analog input than is extracted with conventional linear filtering. Under reasonable mathematical assumptions, optimal nonlinear decoding of the digital output can achieve significantly larger signal-to-noise ratios than linear filtering. However, the hitherto proposed decoding algorithms only demonstrate conceptual feasibility and are impractical from a computational point of view. We present a new block-based decoding algorithm that, like previous work, employs projections onto convex sets. The algorithm owes its speed to a change of projection norm, an accelerated convergence scheme, and a decimation-like subsampling; it is on the order of 10/sup 4/-10/sup 5/ times faster than one previously published algorithm for typical parameter values, and about 2-10 times slower than linear decoding. The new algorithm is applicable to all currently popular /spl Sigma//spl Delta/ architectures.<>     

On The General Relation Between /spl alpha/ and Q (Correspondence)

The relation between the quality factor Q and the attenuation constant /spl alpha/ of a transmission line has been known as follows: /spl alpha/ = /spl beta/ / /2Q where /spl beta/ is the phase constant. Recently from the following relation of propagation constant at resonance /spl Gamma/(/spl omega//sub 0/) + /spl part//spl Gamma/ / /spl part//spl omega/ /spl Delta//spl omega//spl cong/ i/spl beta/(/spl omega//sub 0/), where /spl Gamma/(/spl omega//sub 0/) = /spl alpha/(/spl omega//sub 0/) + i/spl beta/(/spl omega//sub 0/). Yeh derived a general relation between Q and /spl alpha/, namely, /spl alpha/ = /spl upsi//sub p/ / /spl upsi//sub g/ /spl beta/ / /2Q where /spl upsi//sub p/, and /spl upsi//sub g/ are the phase velocity and group velocity of the wave respectively. This general relation can be derived very simply from the generally accepted definition of /spl alpha/ and Q.     

Gain, refractive index, and /spl alpha/-parameter in InGaAs-GaAs SQW broad-area lasers

Gain, refractive index, and the linewidth enhancement factor, or /spl alpha/-parameter, are measured in broad-area InGaAs-GaAs single-quantum-well semiconductor lasers using below-threshold amplified spontaneous emission spectra and a far-field filtering technique. The /spl alpha/ parameter is shown to increase dramatically with increasing carrier density and wavelength. Modes propagating in the transparent substrate of the lasers are shown to have a significant influence on the measured value of /spl alpha/.     

Thermo-optical modulation at /spl lambda/=1.5 /spl mu/m in an /spl alpha/-SiC-/spl alpha/-Si-/spl alpha/-SiC planar guided-wave structure

A planar waveguide based on an amorphous silicon-amorphous silicon carbide heterostructure is proposed for the realization of passive and active optical components at the wavelengths /spl lambda/=1.3-1.5 /spl mu/m. The waveguide has been realized by low temperature plasma enhanced chemical vapor deposition and is compatible with the standard microelectronic technologies. Thermo-optical induced modulation at /spl lambda/=1.5 /spl mu/m is demonstrated in this waveguide. Numerical simulations predict that operation frequencies of about 3 MHz are possible. The measurements have also allowed the determination of the previously unknown thermo-optical coefficient of undoped amorphous silicon at this wavelength.     

New radix-(2/spl times/2/spl times/2)/(4/spl times/4/spl times/4) and radix-(2/spl times/2/spl times/2)/(8/spl times/8/spl times/8) DIF FFT algorithms for 3-D DFT

In this paper, new three-dimensional (3-D) radix-(2/spl times/2/spl times/2)/(4/spl times/4/spl times/4) and radix-(2/spl times/2/spl times/2)/(8/spl times/8/spl times/8) decimation-in-frequency (DIF) fast Fourier transform (FFT) algorithms are developed and their implementation schemes discussed. The algorithms are developed by introducing the radix-2/4 and radix-2/8 approaches in the computation of the 3-D DFT using the Kronecker product and appropriate index mappings. The butterflies of the proposed algorithms are characterized by simple closed-form expressions facilitating easy software or hardware implementations of the algorithms. Comparisons between the proposed algorithms and the existing 3-D radix-(2/spl times/2/spl times/2) FFT algorithm are carried out showing that significant savings in terms of the number of arithmetic operations, data transfers, and twiddle factor evaluations or accesses to the lookup table can be achieved using the radix-(2/spl times/2/spl times/2)/(4/spl times/4/spl times/4) DIF FFT algorithm over the radix-(2/spl times/2/spl times/2) FFT algorithm. It is also established that further savings can be achieved by using the radix-(2/spl times/2/spl times/2)/(8/spl times/8/spl times/8) DIF FFT algorithm.     

An H/sub /spl infin// optimization and its fast algorithm for time-variant system identification

In some estimation or identification techniques, a forgetting factor /spl rho/ has been used to improve the tracking performance for time-varying systems. However, the value of /spl rho/ has been typically determined empirically, without any evidence of optimality. In our previous work, this open problem is solved using the framework of H/sub /spl infin// optimization. The resultant H/sub /spl infin// filter enables the forgetting factor /spl rho/ to be optimized through a process noise that is determined by the filter Riccati equation. This paper seeks to further explain the previously derived H/sub /spl infin// filter, giving an H/sub /spl infin// interpretation of its tracking capability. Additionally, a fast algorithm of the H/sub /spl infin// filter, called the fast H/sub /spl infin// filter, is presented when the observation matrix has a shifting property. Finally, the effectiveness of the derived fast algorithm is illustrated for time-variant system identification using several computer simulations. Here, the fast H/sub /spl infin// filter is shown to outperform the well known least-mean-square algorithm and the fast Kalman filter in convergence rate.     

Design and fabrication of ultra-small overlapped AWG demultiplexer based on /spl alpha/-Si nanowire waveguides

A novel layout for an ultra-compact arrayed-waveguide grating (AWG) demultiplexer is presented. The present layout has two overlapped free propagation regions, and is more compact than a conventional layout. Using /spl alpha/Si-on-SiO/sub 2/ nanowire waveguides, an ultra-small 4/spl times/4 AWG (about 40/spl times/50 /spl mu/m/sup 2/) with channel spacing of 11 nm is fabricated and characterised.     

The tiling phenomenon in /spl Sigma//spl Delta/ modulation

The theoretical error signal analysis of a sigma-delta (/spl Sigma//spl Delta/) modulator is a difficult problem due to the presence of a nonlinear operation (the amplitude quantization) in a feedback loop. In this paper, new deterministic knowledge on the transfer function of a /spl Sigma//spl Delta/ modulator is established, thanks to some recently observed properties of its state variables. For a large class of typical /spl Sigma//spl Delta/ modulators with constant inputs, the state variables appear to remain in a tile. We show what characteristics in a /spl Sigma//spl Delta/ modulator are specifically responsible for this property and give some initial proof of it. Under a constant input, the tiling phenomenon has as fundamental consequence that the output is a fixed and memoryless modulo function of n successive integrated versions of the input. This gives the theoretical knowledge that the modulator has an equivalent feedforward circuit expression. We give some immediate theoretical consequences on error analysis including the case of time-varying inputs.     

A 50-/spl mu/A standby 1M/spl times/1/256K/spl times/4 CMOS DRAM with high-speed sense amplifier

A 1M word/spl times/1-bit/256K word/spl times/4-bit CMOS DRAM with a test mode is described. The use of an improved sense amplifier for the half-V/SUB CC/ sensing scheme and a novel half-V/SUB CC/ voltage generator have yielded a 56-ns row access time and a 50-/spl mu/A standby current at typical conditions. High /spl alpha/-particle immunity has been achieved by optimizing the impurity profile under the bit line, based on a triple-layer polysilicon n-well CMOS technology. The RAM, measuring 4.4/spl times/12.32 mm/SUP 2/, is fit to standard 300-mil plastic packages.     

Robust speed control of an induction motor: an /spl Hscr//sub /spl infin// control theory approach with field orientation and /spl mu/-analysis

In this paper we present a robust speed control strategy for an induction motor under field orientation. The control framework employed properly represents the induction motor state-space model and its inherent variations, which are treated as structured uncertainties. Applying an /spl Hscr//sub /spl infin//, optimization methodology on this framework we derive a stabilizing controller to meet design objectives and then robust stability and performance against such variations are checked by using /spl mu/-analysis. No on-line tuning is required for the parameters of the derived controller, which is the dynamic system responsible to keep the rotor flux orientation as well as the speed regulation at design levels, irrespective of the motor operating points. A general methodology arose from the usage of the proposed strategy and simulated experiments showed satisfactory results for the robust speed control of an induction motor.     

Theory and applications of incremental /spl Delta//spl Sigma/ converters

Analog-Digital (A/D) converters used in instrumentation and measurements often require high absolute accuracy, including very high linearity and negligible dc offset. The realization of high-resolution Nyquist-rate converters becomes very expensive when the resolution exceeds 16 bits. The conventional delta-sigma (/spl Delta//spl Sigma/) structures used in telecommunication and audio applications usually cannot satisfy the requirements of high absolute accuracy and very small offset. The incremental (or integrating) converter provides a solution for such measurement applications, as it has most advantages of the /spl Delta//spl Sigma/ converter, yet is capable of offset-free and accurate conversion. In this paper, theoretical and practical aspects of higher order incremental converters are discussed. The operating principles, topologies, specialized digital filter design methods, and circuit level issues are all addressed. It is shown how speed, resolution, and A/D complexity can be optimized for a given design, and how with some special digital filters improved speed/resolution ratio can be achieved. The theoretical results are verified by showing design examples and simulation results.     

Genetic algorithm approach to fixed-order mixed H/sub 2//H/sub /spl infin// optimal deconvolution filter designs

The mixed H/sub 2//H/sub /spl infin// optimal deconvolution filter is proposed to achieve the H/sub 2/ optimal reconstruction and a desired robustness against the effect of uncertainties in signal processing from the H/sub /spl infin// norm perspective. However, the conventional mixed H/sub 2//H/sub /spl infin// optimal design filters are very complicated and are not practical for industrial applications. For simplicity of implementation and conservation of operation time, the fixed-order mixed H/sub 2//H/sub /spl infin// optimal deconvolution filter design is interesting for engineers in signal processing from the practical design perspective. In this study, to avoid the trap of local minima, a design method based on the genetic algorithm is introduced to treat the nonlinear optimization design problem of the fixed-order mixed H/sub 2//H/sub /spl infin// deconvolution filter. The convergence property of our design algorithm is also discussed. Finally, an example is presented to illustrate the design procedure and confirm the robustness performance of the proposed method.     

Moire/spl acute/ minimization condition in three-dimensional image displays

A moire/spl acute/ minimization condition is found analytically for the contact-type three-dimensional (3-D) imaging systems by approximating 3-D displays as four superposed sine gratings. Finding maximization conditions for two-dimensional (2-D) waves in this structure provides minimization of moire/spl acute/s. The global extremum was found at a certain angle which does not depend on the period. Experiments confirm the analytical findings. Practical advantage of using that angle is in its wide areas of applications: 3-D displays can be made to have almost invisible moire/spl acute/s with using this angle without regards to other specific parameters like pixel size and pitch of the screen.     

The rank and kernel of extended 1-perfect /spl Zopf//sub 4/-linear and additive non-/spl Zopf//sub 4/-linear codes

A binary extended 1-perfect code of length n + 1 = 2/sup t/ is additive if it is a subgroup of /spl Zopf//sub 2//sup /spl alpha// /spl times/ /spl Zopf//sub 4//sup /spl beta//. The punctured code by deleting a /spl Zopf//sub 2/ coordinate (if there is one) gives a perfect additive code. 1-perfect additive codes were completely characterized and by using that characterization we compute the possible parameters /spl alpha/, /spl beta/, rank, and dimension of the kernel for extended 1-perfect additive codes. A very special case is that of extended 1-perfect /spl Zopf//sub 4/-linear codes.     

A 4 /spl mu/m NMOS NAND structure PLA

A PLA of NAND structure, using a NMOS Si gate process, has been developed to minimize chip area and maintain medium fast speed. The smallest memory cell size of 7/spl times/9 /spl mu/m is achieved by using ion implantation for PLA bit programming with 4 /spl mu/m design rules. Dynamic clocking scheme and self-timing circuits which are used in this PLA are described. With PLA size at 20/spl times/20/spl times/20, transistor size of 8 /spl mu/m/4 /spl mu/m, and cell size of 7/spl times/12 /spl mu/m, an internal access time of 150 ns is achieved with an external 4 MHz clock. Measured circuit power dissipation is 20 mW under normal conditions.     

A CMOS 1/spl times/-16/spl times/ speed DVD write channel IC

Optical recording demands a meticulous write strategy to control the laser beam power and regulate the phase change layer temperature tightly. The width, height, and delay of a string of short pulses applied to the laser diode need to be adjusted in fine steps, and the writing speed varies widely per applications. A multi-phase phase-locked loop (PLL) tracks a wide range of clock frequencies, and provides a low-jitter time base for write pulses. With two enabling circuit concepts, PLL loop filter voltage folding/unfolding and switch-in of parallel MOS resistors in delay cells, it is possible to operate a PLL to cover a frequency range spanning over three octaves with one VCO. A 10-stage differential VCO is phase-locked to the input channel clock ranging from 26 to 420 MHz (1/spl times/-16/spl times/ DVD speed), and its 20-phase outputs are used to generate write pulses. The pulsewidth and delay are programmed with 120 /spl plusmn/ 40 ps time resolution. The prototype chip fabricated in 0.35 /spl mu/m CMOS occupies 3.5/spl times/3.3 mm/sup 2/, and consumes 294 mW at 3.3 V.     

Numerical method for determining the quantization error PDF of single-bit /spl Sigma//spl Delta/ Modulators

Existing models for the quantizer of /spl Sigma//spl Delta/ modulators make assumptions on the probability density function (pdf) of the quantization error, or some other convenient signal of the modulator. In this paper, a method for the determination of this pdf for single-bit /spl Sigma//spl Delta/ modulators is presented. First, a numerical method is proposed in order to solve the simplified equation for the quantization error pdf for first-order systems considering noiseless and noisy dc input signals. Then, it is shown how most practical high-order (>2)/spl Sigma//spl Delta/ modulators, resulting from well-established design methods, can be modeled as first-order systems plus an additive noise source at the input. Hence, their quantization error pdf is analyzed using the proposed method. Simulation results are shown to be in considerable agreement with those of the proposed method.     

On /spl Zopf//sub 4/-linear Preparata-like and Kerdock-like codes

We say that a binary code of length n is additive if it is isomorphic to a subgroup of /spl Zopf//sub 2//sup /spl alpha// /spl times/ /spl Zopf//sub 4//sup /spl beta//, where the quaternary coordinates are transformed to binary by means of the usual Gray map and hence /spl alpha/ + 2/spl beta/ = n. In this paper, we prove that any additive extended Preparata (1968) -like code always verifies /spl alpha/ = 0, i.e., it is always a /spl Zopf//sub 4/-linear code. Moreover, we compute the rank and the dimension of the kernel of such Preparata-like codes and also the rank and the kernel of the /spl Zopf//sub 4/-dual of these codes, i.e., the /spl Zopf//sub 4/-linear Kerdock-like codes.     

Quasi-equivalent feedforward system in asymptotic /spl Sigma//spl Delta/ modulation

It was previously shown that sigma-delta (/spl Sigma//spl Delta/) modulators of "asymptotic" type theoretically yield an equivalent feedforward system where the recursive nonlinear mechanisms are extracted from the feedback loop and reduced to a memoryless function. With time-varying inputs, we show in this paper, partially by mathematical derivations and partially by experiment, that this system is quasi-equivalent to the original modulator in a sense that we explain. This reduction of the nonlinear mechanisms should permit more refined modeling of the /spl Sigma//spl Delta/ errors in future research, with a better account of the original nonlinearities of asymptotic /spl Sigma//spl Delta/ modulation.