Characterization of various stress-induced oxide traps in MOSFET'sby using a subthreshold transient current technique

An oxide trap characterization technique by measuring a subthreshold current transient is developed. This technique consists of two alternating phases, an oxide charge detrapping phase and a subthreshold current measurement phase. An analytical model relating a subthreshold current transient to oxide charge tunnel detrapping is derived. By taking advantage of a large difference between interface trap and oxide trap time-constants, this transient technique allows the characterization of oxide traps separately in the presence of interface traps. Oxide traps created by three different stress methods, channel Fowler-Nordheim (F-N) stress, hot electron stress and hot hole stress, are characterized. By varying the gate bias in the detrapping phase and the drain bias in the measurement phase, the field dependence of oxide charge detrapping and the spatial distribution of oxide traps in the channel direction can be obtained. Our results show that 1) the subthreshold current transient follows a power-law time-dependence at a small charge detrapping field, 2) while the hot hole stress generated oxide traps have a largest density, their spatial distribution in the channel is narrowest as compared to the other two stresses, and 3) the hot hole stress created oxide charges exhibit a shortest effective detrapping time-constant     

Investigation of oxide charge trapping and detrapping in a MOSFETby using a GIDL current technique

We proposed a new measurement technique to investigate oxide charge trapping and detrapping in a hot carrier stressed n-MOSFET by measuring a GIDL current transient. This measurement technique is based on the concept that in a MOSFET the Si surface field and thus GIDL current vary with oxide trapped charge. By monitoring the temporal evolution of GIDL current, the oxide charge trapping/detrapping characteristics can be obtained. An analytical model accounting for the time-dependence of an oxide charge detrapping induced GIDL current transient was derived. A specially designed measurement consisting of oxide trap creation, oxide trap filling with electrons or holes and oxide charge detrapping was performed. Two hot carrier stress methods, channel hot electron injection and band-to-band tunneling induced hot hole injection, were employed in this work. Both electron detrapping and hole detrapping induced GIDL current transients mere observed in the same device. The time-dependence of the transients indicates that oxide charge detrapping is mainly achieved via field enhanced tunneling. In addition, we used this technique to characterize oxide trap growth in the two hot carrier stress conditions. The result reveals that the hot hole stress is about 10⁴ times more efficient in trap generation than the hot electron stress in terms of injected charge     

Influence of holes on neutral trap generation

Using a newly proposed method for estimating the neutral trap density, generation characteristics of the neutral trap during various stress types have been investigated. From the analysis of the trap-generation kinetics, two types of trap generation closely related to holes have been identified. At the first stage of stress application, holes interact with the pre-existing structural origins of the neutral traps, then the neutral traps are generated. Influence of hole energy on this type of trap generation is also identified. After that, as holes pass, they also create the structural origins of the traps. The holes interact with these structural origins and the neutral traps are generated as a secondary effect. Thus, the increase in the neutral trap density shows up clearly with increase in the hole fluence. The stress-strength dependence of the increase in the neutral trap density can also be interpreted in terms of the influence of hole energy on the trap generation     

Quantifying charging damage in gate oxides of antenna structures for WLR monitoring

A new method to quantify the reliability risk for gate oxide with plasma induced charging damage (PID) is established. Based on existing antenna test methodology the quantity of inflicted damage is expressed in a physical meaningful number by means of a simple model applicable for thick oxides (>5 nm).This model takes trap activation, trap filling, detrapping and also traps generation under constant current test condition (“revealing stress”, “diagnostic stress”) into account. For the corresponding development of the measurable external supply voltage with time an equation is derived. Experimental test data from different oxide thicknesses are fitted to this model equation to obtain its main parameters, the cross section values. These cross section values describe the probabilities for the different trap/detrap processes during stress. Cross section values thus found extend published data for lower electric fields to high electric fields necessary for a fast test.The number of plasma induced traps, which was added to the oxide during wafer processing, can now be determined by applying an electron trapping rate (ETR) test method, and combining it with our dynamic trap generation/filling model. The obtained number of PID related traps opens a path to calculate the corresponding reduction of oxide lifetime. Real measurement data are used to illustrate the method and its applicability to fast wafer level reliability (fWLR) monitoring.     

Characterizing wearout, breakdown and trap generation in thin silicon oxide

A model describing how wearout leads to breakdown in thin silicon oxides has been developed. During wearout defects or traps are generated inside the oxide and at the oxide interfaces. The signature of the trap generation is the permanent change in the transient current, in response to a voltage pulse, from an exponential decay to a 1/time decay. In oxides thinner than approximately 20 nm the dominant trap generation mechanism appears to be determined by the high fields across the oxides and not electron flow through the oxides. Locally higher current densities, flowing through the traps generated during wearout, lead to local breakdown. This model is critically dependent on the measurement of the properties of the traps generated inside the oxides during the wearout phase. The techniques for measurement of these traps and some of their properties have been described. The ability of this model to describe oxide charging, low-level leakages, transient currents, the role of asperities, polarity dependences, and the fluence, time, thickness, voltage and temperature dependences of oxide breakdown distributions has been discussed.     

A new technique to extract oxide trap time constants in MOSFET's

A new technique to determine oxide trap time constants in a 0.6 μm n-MOSFET subject to hot electron stress has been proposed. In this method, we used GIDL current as a direct monitor of the oxide charge detrapping-induced transient characteristics. An analytical model relating the GIDL current evolution to oxide trap time constants was derived. Our result shows that under a field-emission dominant oxide charge detrapping condition, Vgs=-4 V and Vds=3 V, the hot electron stress generated oxide traps exhibit two distinct time constants from seconds to several tens of seconds     

The SILC study by PDO method

Stress induced leakage current (SILC) has been discussed for a long time by many researchers. The oxide traps are believed to be the cause of SILC, but characterization of these traps is still not clear. In this paper, we demonstrate that the SILC related oxide traps can be distinguished into two kinds with different characterization parameter by PDO method. Linear fitting also shows that double oxide trap model is better than single oxide trap model.     

Dynamic oxide voltage relaxation spectroscopy

A new method for trap characterization of oxidized silicon is described. The Dynamic Oxide Voltage Relaxation Spectroscopy (DOVRS) is an improved version of the formerly proposed Oxide Voltage Relaxation Spectroscopy (OVRS) technique which applies a periodic long duration constant current for tunneling injection. It has been demonstrated that the new technique can be used not only to separate and identify the oxide trap from interface trap, but also to separate and determine the centroid from the oxide trap density generated in the MOS system by the tunneling current stress. In the pulse constant current mode, the OVRS measurement can be completed instead of using the double current-voltage technique. Thus the new method results in more accurate and quicker measurements of the oxide trap centroid. Analytical expressions for computing the paramaters of the interface and oxide traps are derived. The effect of the channel carrier mobility on the spectroscopy is also considered. Two types of oxide and two types of interface traps were observed at a pulse constant Fowler-Nordheim current stress by the new method of DOVRS     

Study of electron traps in the thin interfacial oxide layer of Al-, Au- and Sn-n GaAs Schottky barriers by detrapping experiments

Electron traps in MIS-type Schottky barriers on n-GaAs were investigated by measuring the change of the flat-band voltage, due to detrapping, as a function of time. The trap depth and the capture cross section for a particular trap were obtained from the temperature dependence of the time constant for detrapping. It was found that the detrapping process in some cases is a two-state thermionic emission and tunneling process. For other trapping levels the results indicated clearly that the mechanism was different from the thermionic emission and tunneling process.     

Hole trapping and trap generation in the gate silicon dioxide

Oxide breakdown has been proposed to be a limiting factor for future generation CMOS. The breakdown is caused by defect generation in the oxide. Although electron trap generation has received much attention, there is little information available on the hole trap generation. The relatively high potential barrier for holes at the oxide/Si interface makes it difficult to achieve a high level of hole injection. Most previous work was limited to an injection level Q_inj of 10¹⁴ cm^-2. In this paper, we investigate the hole trapping and trap generation when Q_inj reaches the order of 10¹⁸ cm^-2. When Q_inj <10¹⁵ cm^-2, the trapping is dominated by the as-grown traps. As Q_inj increases further, however, it is found that the generation of new traps controls the trapping. The trap generation does not saturate up to the oxide breakdown. The trapping kinetics for both the as-grown and the generated traps is studied. The relationship between the density of generated traps and the Q_inj is explored. Attention is paid to how the trapping and trap generation depends on the distance from the interface. In contrast to the uniform generation of electron traps across the oxide, we found that the hole trap generation was not uniform and it moved away from the interface as Q_inj increased     

Properties of high-voltage stress generated traps in thin siliconoxide

It has previously been shown that trap generation inside thin oxides during high voltage stressing can be coupled to time-dependent-dielectric-breakdown distributions through the statistics linking wearout to breakdown. Since the stress-generated traps play a crucial role in the wearout/breakdown process, it is important to understand the properties of these traps. The properties of the traps in oxides with thicknesses between 2.5 nm and 22 nm have been studied, with emphasis on oxides in the 8.5-nm to 13-nm thickness range. The Coulombic scattering cross section of the traps responsible for the reduction in the tunneling current, an estimate of the spatial and energy distribution of the traps, and the charging/discharging properties of the traps have been measured. It will be shown that the measured properties of the high-voltage, stress-generated traps can be adequately described by the tunneling of electrons into and out of traps     

Reversible and irreversible interface trap centres generated at high electric fields in MOS structures

In this work, we present results of the study of interface trap generation processes at the Si–SiO₂ interface in MOSFET structures caused by high oxide field stress. Changes in areal density and energy distribution in the Si band gap of the interface traps were monitored using the II-level conventional charge pumping technique. The generated interface traps were divided into two types: reversible and irreversible in relation to their discharge by low field electron injection. A broad presentation of changes in density and energy distribution of the interface traps was included. The threshold value of oxide field for interface trap generation was obtained.     

用于VLSI的SiO_xN_y薄膜的界面陷阱

采用雪崩热电子注入技术研究了用于VLSI的快速热氮化的SiO_xN_y薄膜界面陷阱。给出这种薄介质膜禁带中央界面陷阱密度随氮化时间的变化关系,观察到这种薄膜存在着不同类型的密度悬殊很大的电子陷阱。指出雪崩热电子注入过程中在Si/SiO_xN_y界面上产生两类性质不同的快界面态陷阱,并给出这两种陷阱在禁带中能级位置及密度大小关系;同时还给出禁带中央界面陷阱密度随雪崩注入剂量呈现弱“N”形变化关系,并对实验结果进行了讨论。     

Low-frequency noise spectroscopy of polycrystalline siliconthin-film transistors

Polycrystalline silicon thin-film transistor (polysilicon TFT's) characteristics are evaluated by using a low-frequency noise technique. The drain current fluctuation caused by trapping and detrapping processes at the grain boundary traps is measured as the current spectral density. Therefore, the properties of the grain boundary traps can be directly evaluated by this technique. The experimental data show a transition from 1/f behavior to a Lorentzian noise. The 1/f noise is explained with an existing model developed for monocrystalline silicon based on fluctuations of the inversion charge near the silicon-oxide interface. The Lorentzian spectrum is explained by fluctuations of the grain boundary interface charge with a model based on a Gaussian distribution of the potential barriers over the grain boundary plane. Quantitative analysis of the 1/f noise and the Lorentzian noise yield the oxide trap density and the energy distribution of the grain boundary traps within the forbidden gap     

Hot-hole-induced negative oxide charges in n-MOSFETs

We investigate the generation of electron traps by hole injection during hot-carrier stressing of n-MOSFETs. These generated electron traps are filled by an electron injection following the primary hole stress. The effect is proven and quantified by monitoring the detrapping kinetics in the multiplication factor and the charge pumping current. The traps are located in the oxide within the first few nanometers to the interface. An interaction of those traps with interface states is found in that charged electron traps inhibit charging or uncharging of interface states. The kinetics of hot-carrier-induced fixed negative charges in n- and p-channel MOSFET's are compared showing significant differences in the properties of the two species of traps. Hole-induced electron traps are located much closer to the interface and their energetic level is deeper. Finally, a method is presented that allows the quantification of the effect for reliability purposes. We conclude that under digital and analog operation conditions in which hole effects cannot completely be ruled out, this effect has to be considered.<>     

Hot carrier effects in polycrystalline silicon thin-film transistors: analysis of electrical characteristics and noise performance modifications

Hot-carrier effects on both the electrical characteristics and the noise performance in polycrystalline silicon thin film transistors are analysed. The devices were fabricated by using a combined solid phase crystallization (SPC) and excimer laser annealing (ELA) process, combining the beneficial aspects of the two techniques. Hot-carrier degradation results in the formation of both interface states, which have been evaluated through the analysis of the sheet conductance and of oxide traps near the insulator/semiconductor interface, as evidenced by the 1/f noise measurements. Oxide traps are calculated evaluating the flat band voltage spectral density associated with interface charge fluctuations in the damaged part of the interface. A strong correlation between interface state and oxide trap densities has been found, suggesting a common origin for the generation mechanism of the two types of defects.     

Extrapolation of high-voltage stress measurements to low-voltageoperation for thin silicon-oxide films

Breakdown and wearout in MOS capacitors fabricated with 10 nm-thick silicon oxide films on p-type silicon are discussed. They have been stressed at high voltages. The high-voltage-stress-induced changes in the oxide properties are extrapolated to low operating voltages. The stress voltages ranged from -7.5 V to -14.5 V. The fluence during the stress was systematically varied front 2×10^-5 C/cm² to 6 C/cm² by varying the stress time at each voltage. The number of interface traps generated by the stress increased as the stress voltage and fluence increased. However, the interface trap generation rate decreased as the fluence increased. The trap generation rate at low operating voltages was very high, but because the current through the oxide was small, the total number of traps generated was low. The trap generation rate was proportional to the inverse square root of the fluence with a voltage dependence that decreased as the fluence increased. Extrapolation of the high-voltage-stress measurements to 5 V shows that easily detectable changes in the oxide properties would only occur after several years of 5 V operation. Extrapolation of charge-to-breakdown and time-to-breakdown data to 5 V operation indicates that breakdown would occur after hundreds of years of device operation     

Correlation of trap generation to charge-to-breakdown (Qbd): a physical-damage model of dielectric breakdown

Ultrathin gate and tunnel oxides in MOS devices are subjected to high-field stress during device operation, which degrades the oxide and eventually causes dielectric breakdown. Oxide reliability, therefore, is a key concern in technology scaling for ultra-large scale integration (ULSI). Here we provide critical new insight into oxide degradation (and consequently, reliability) by a systematic study of five technologically relevant parameters, namely, stress-current density, oxide thickness, stress temperature, charge-injection polarity (gate versus substrate), and nitridation of pure oxide. For all five parameters, a strong correlation has been observed between oxide degradation and the generation of new traps (distinct from the filling of intrinsic traps). Further, we observe that this correlation is independent of the trap polarity (positive versus negative). Based on this correlation, and based on the fundamental link between electronic properties and atomic structure, a physical-damage model of dielectric breakdown has been proposed. The concept of the physical-damage model is that the oxide suffers dielectric breakdown when physical damage due to broken bonds forms a defect-filled filamentary path in the oxide, that conducts excessive current. A good monitor of this physical damage is trap generation, which we believe is caused by physical bond breaking in the oxide and at the interface. The model has been quantified empirically by the correlation between trap generation and Q_bd     

Characterization of charge trapping and high-field endurance for15-nm thermally nitrided oxides

Device-quality gate oxides have been nitrided using both rapid thermal processing and conventional furnace treatment. Charge trapping and high-field endurance including breakdown field and time-dependent dielectric breakdown, are investigated in detail. It is found that proper nitridation can eliminate positive charge accumulation in oxides, increase charge to breakdown, suppress high-field injection-induced interface state generation, and decrease the dependence of the breakdown field on the gate area as a result of the reduced density of microdefects. Experimental results show that although both the density and capture cross-section of the bulk and interface traps increased by nitridation, the combined effects of bulk and interface traps induced by high-field injection can improve the stability of the flatband voltage. For lightly nitrided oxides, the trap generation rate is greatly decreased as compared with the as-grown oxide. Not only are the density and capture cross-section of the traps affected by nitridation, but also the locations of the trapped-charge centroids are changed. The experimental results for postnitridation annealing suggest that these property modifications most likely result from nitridation-induced structural changes rather than hydrogenation alone     

Effects of the metal gate on the stress-induced traps in Ta2O5/SiO2 stacks

The degradation of Ta₂O₅-based (10 nm) stacked capacitors with different top electrodes, (Al, W, Au) under constant current stress has been investigated. The variation of electrical characteristics after the stress is addressed to gate-induced defects rather than to poor-oxidation related defects. The main wearout parameter in Ta₂O₅ stacks is bulk-related and a generation only of bulk traps giving rise to oxide charge is observed. The post-stress current–voltage curves reveal that stress-induced leakage current (SILC) mode occurs in all capacitors and the characteristics of pre-existing traps define the stress response. The results are discussed in terms of simultaneous action of two competing processes: negative charge trapping in pre-existing electron traps and stress-induced positive charge generation, and the domination of one of them in dependence on both the stress level and the gate used. The charge build-up and the trapping/detrapping processes modify the dominant conduction mechanism and the gate-induced defects are precursors for device degradation. It is concluded that the impact of the metal gate on the ultimate reliability of high-k stacked capacitors should be strongly considered.