A new high performance phase shifter using BaxSr1-xTiO3 thin films

In this paper, a new device topology has been proposed to implement parallel plate capacitors using Ba_xSr_1-xTiO₃ (BST) thin films. The device layout utilizes a single parallel capacitor and minimizes conductor losses in the base electrode. The new design simplifies the monolithic process and overcomes the problems associated with electrode patterning. An X-band 180° phase shifter has been implemented using the new device design. The circuit provided 240° phase shift with an insertion loss of only 3 dB at 10 GHz at room temperature. We have shown a figure of merit 93°/dB at 6.3 GHz and 87°/dB at 8.5 GHz. To our knowledge, these are the best figure of merit results reported in the literature for distributed phase shifters implemented using BST films at room temperature     

A 1-GHz active phase shifter with a ferroelectric varactor

An active phase shifter circuit implemented with discrete components is reported. The tuning element, a ferroelectric varactor, is a parallel plate capacitor with Ba/sub 0.5/Sr/sub 0.5/TiO/sub 3/ (BST) as the dielectric. The circuit consists of two bipolar junction transistors coupled with a feedback network, which contains the varactor and thus produces a transfer function that can be varied with a control voltage. The active nature of the circuit allows for signal gain, while the BST varactor provides a high-Q tuning element. This represents an improvement over strictly passive phase shifters with ferroelectric elements. Circuit simulation results are presented and compared with measured data from the implemented system. The network, even with markedly nonideal transistors, can provide a true all-pass response over the frequency band of interest (200-1100 MHz). The measurement results demonstrate an analog tunability of about 100/spl deg/ with a gain variation of about 0.6 dB at I GHz when using a BST capacitor with a tunability of 2.75:1.     

Loss-Free Balancing Circuit for Series Connection of Electrolytic Capacitors Using an Auxiliary Switch-Mode Power Supply

Most of today's power converters such as three-phase variable-speed drives, uninterruptible power systems, welding converters, and telecom and server power supplies are based on voltage-source converters equipped with bulky dc-link electrolytic capacitors. To be able to handle full dc bus voltage, the dc bus capacitor is arranged as series-connected electrolytic capacitors rated at lower voltage. An electrolytic capacitor, however, is not an ideal capacitor. It has significant leakage current that strongly depends on the capacitor temperature, voltage, and ageing conditions. To compensate large dispersion of the leakage current and ensure acceptable sharing of the total dc bus voltage among the series-connected capacitors, a passive balancing circuit is often used. Drawbacks of the ordinary passive balancing circuit, such as size, significant losses, and standby consumption are discussed in this paper. An active loss-free balancing circuit, which utilizes an auxiliary switch-mode power supply (SMPS) to equalize the capacitor voltages, is proposed. The capacitors midpoint (MP) is connected to the SMPS via two devices; namely a current injection device and a compensation device. The current injection device injects current into the capacitors MP, while the compensation device sinks the difference between the capacitor leakage currents and the injected current. As a result, the capacitor voltages are controlled and maintained in the desired ratio. The proposed balancing technique is theoretically analyzed and experimentally verified on a laboratory setup. The results are presented and discussed.      

VCO电路测试新型BST电容器的可变电容特性

基于新型BST电容器的变容机理,采用集成芯片MC12148设计VCO(压控震荡器)测试电路,通过测量不同控制电压对应的频率,计算出材料的电容与介电常数,研究了新型BST的压控特性,推导出该BST材料的电压与电容关系式。结果显示:新型BST材料加正反偏压电容都发生变化;最大耐压值为40 V;其电容调谐率与压控灵敏度都很小,分别为10.691%和5.717 kHz/V;材料应用在频率合成器的微调上,可提高合成频率的灵敏度与精度。     

复合开关投切电容器无功补偿装置的研究

针对电磁开关和电力电子开关投切电容器无功补偿装置应用中存在的问题，开发、研制了一种基于复合开关投切电容器的无功补偿装置。采用三相共补△接线与单相分补Y接线相结合的接线方式，实现了对三相负栽分相、分级、快速的无功补偿。试验和现场运行情况表明，这种无功补偿装置运行可靠性高、性能稳定，能满足绝大多数场合的应用需要。对复合开关的组成原理、电路结构和装置的整体性能等进行了详细描述。     

A new negative resistance circuit and an application for loss compensation in a distributed amplifier

This paper presents a new negative resistance (NR) circuit which is designed especially to compensate the losses inherent in conventional distributed amplifiers (CDA). The consequence of the new NR circuit in the CDA is significant improvement of bandwidth (~15%) with no degradation in gain. In addition, the simplicity of the NR circuit makes it amenable to MMIC technology and moreover for broadband applications.     

Design and Application for PV Generation System Using a Soft-Switching Boost Converter With SARC

In order to improve the efficiency of energy conversion for a photovoltaic (PV) system, a soft-switching boost converter using a simple auxiliary resonant circuit, which is composed of an auxiliary switch, a diode, a resonant inductor, and a resonant capacitor, is adopted in this paper. The conventional boost converter decreases the efficiency because of hard switching, which generates losses when the switches are turned on/off. During this interval, all switches in the adopted circuit perform zero-current switching by the resonant inductor at turn-on, and zero-voltage switching by the resonant capacitor at turn-off. This switching pattern can reduce the switching losses, voltage and current stress of the switching device. Moreover, it is very easy to control. In this paper, we have analyzed the operational principles of the adopted soft-switching boost converter, and it is designed for PV generation system. Simulation and experimental results are presented to confirm the theoretical analysis.      

A high-gain complementary metal-oxide semiconductor op amp using composite cascode stages

In this work, a complementary metal-oxide semiconductor (CMOS) op amp design using composite cascode stages is reported. The design follows the classic Widlar architecture and is fabricated on a 0.25 μm CMOS process. The measured gain of 117 dB is comparable to that achieved in bipolar designs in this architecture. This design is suited for precision instrumentation applications where high gain, low input offset voltage and small cell size are important. It provides a common-mode input range of ?1 to 0.7 V using±1 V power supplies with a quiescent current of 55 μA. The use of the composite cascode also allows for dominant pole compensation with a single capacitor. A phase margin of 43° is achieved with a 3.5 pF compensation capacitor. The resulting cell size for the core op-amp circuit is approximately 24 × 16 mils, including large common centroid input devices that achieve an input offset voltage in the 1 mV range.     

BST材料在DRAM电容中的应用研究

钛酸锶钡(BST)高介电常数材料被普遍认为是最有前途的DRAM电容介质材料。BST作为DRAM电容介质材料的研究已有多年，到目前为止取得了不少突破性的进展。介绍了BST的材料特性和堆积型电容结构电极、埋层材料的设计考虑，探讨了BST膜的制备、掺杂及刻蚀工艺技术。     

Metodology for Capacitor Placement in Distribution Systems using Linear Sensitivity Factors

This paper proposes a capacitor placement methodology based on sensitivity linear factors of distribution losses with respect to derivation-connected capacitor compensators. The methodology identifies the best size and location for every capacitor bank to be placed in the distribution network considering technical and economical issues. A compensation action is technically accepted when it reduces losses and improves voltage profiles. In order to reduce the search space of feasible solutions and to use real banks capacities, only commercial bank sizes are considered. To evaluate the different alternatives from the economical viewpoint, the net present value is applied. Two examples with different distribution systems reported in the literature are presented in order to illustrate the proposed methodology application.     

An analysis of a circuit for the generation of high-order harmonics using an ideal nonlinear capacitor

A particular harmonic generator circuit using an ideal nonlinear capacitor is analyzed and theoretical expressions are obtained for the loss involved in generating a high-order harmonic. The harmonic energy is developed in a load resistor either as an exponentially decaying sine wave or as a pulse. The analysis is valid for harmonics of about the tenth or greater. The results are presented in a graphical form that allows the losses involved to be found easily and it is thus shown that the minimum loss in generating a high-order harmonic by this circuit is about 8.5 db independent of the order of the harmonic. The degree to which a charge storage diode approximates to an ideal nonlinear capacitor is then discussed and some experimental results using such a diode are presented.     

电流型PWM DC-DC升压转换器的稳定性分析与实现

文章先对影响电流型DC-DC升压转换器电路的系统稳定性的因素进行分析，然后在电路设计实现上提出了具体的改进办法：在误差放大器模块增加频率补偿电路来消除放大器反馈环路可能存在的振荡现象：采用斜坡补偿电路来增强反馈电流环路的稳定；为了提高电压反馈环路的稳定性，创新提出在芯片外部增加COMP管脚。内部增加环路补偿电路；输入管脚增加旁路电容以减少噪声；输出管脚增加旁路电容以增强芯片反馈系统的稳定性;通过采取这些措施，保证了芯片电路的的稳定性能，并极大的提高了输出电压的精度，设计取得了很大成功。     

Evaluation of electrolytic capacitors for high peak current pulseduty

A new type of electrolytic capacitor has been developed specifically for high-peak-current applications. Preliminary results of an ongoing research effort to determine the operational characteristics of this new type of electrolytic capacitor are reported. The new electrolytic capacitors, designed for pulse discharge application, were tested in a low-inductance discharge circuit to evaluate the maximum current extractable, internal inductance of the capacitors (equivalent series inductance), internal losses of the capacitor (equivalent series resistance), and the potential lifetimes of the capacitors. The peak currents extracted ranged from 17 kA for the 2000-μF unit to 27 kA for the 6800-μF unit, with pulsewidths ranging from approximately 100 to 280 μs for the 2000- and 6800-μF units, respectively     

Optimized design of a fully soft-switched boost-converter suitable for power factor correction

A fully soft-switched boost-converter using a one auxiliary switch is presented here. It uses the minimum number of components in the auxiliary circuit with minimum current stress of the main switch. Since the resonant capacitor charges only through an inductor and a diode, the circuit conduction losses are minimized. The main and auxiliary insulated gate bipolar transistor (IGBT) switches share a common emitter connection, facilitating direct drive to them. Various operating modes of the converter are presented in detail and analysed. The choice of the resonating capacitor and inductor has been done through an optimization process based on the guiding equations working under different modes. In this optimization process, emphasis has been given on minimum voltage stress on the auxiliary switch for a wide duty cycle range of operation. Based on the design, the principle of operation has been verified with computer simulation. Experimental results from a laboratory prototype with active power factor correction confirms the operation of this converter.     

Design of an LDO with capacitor multiplier

This paper presents a low quiescent current,highly stable low-drop out(LDO) regulator.In order to reduce capacitor value and control frequency response peak,capacitor multipliers are adopted in the compensation circuit with mathematic calculations.The phase margin is adequate when the load current is 0.1 or 150 mA.Fabricated in an XFAB 0.6μm CMOS process,the LDO produces 12.2 mV(0.7%) overshoot voltage while the current changes at 770 mA/100μs with a capacitor load of 10μF.     

Relationship between settling time and pole–zero placements for three-stage CMOS opamp

In this article, the effect of pole–zero placements on settling time has been analysed for a three-stage CMOS operational amplifier (opamp) with nested Miller compensation (NMC) and reversed nested Miller compensation (RNMC) schemes. In this study, optimised balancing of speed and power is done for a three-stage CMOS opamp for a given load condition (on-chip opamp). Optimum values of circuit parameters have been derived for power efficient shifting of poles and zeros. The effect of placement of poles and zeros on dynamic settling error (DSE) is analysed by means of numerical simulation using MATLAB. This analysis will be useful to ascertain the relationship between pole–zero placements and settling time. The study of the effects of compensation elements on pole–zero placements has been done to assist the circuit designers to achieve better performance. Analysis of the effect of capacitive load on pole–zero placements and DSE has been done in this study. A technique has been developed to find out the upper and lower limits of compensation capacitor that allows fast settling with low power. The validity of the analytical work has been checked by simulation using Tanner tool in 0.35-µm CMOS technology. In the case of RNMC scheme, a power dissipation of 60.17?µw and a settling time of 340?ns are achieved; the results obtained are better than the earlier reported design technique. In the case of NMC, the simulation has been done to validate the analytical analysis.     

A stacked capacitor technology with ECR plasma MOCVD(Ba,Sr)TiO3 and RuO2/Ru/TiN/TiSixstorage nodes for Gb-scale DRAMs

A Gb-scale DRAM stacked capacitor technology with (Ba,Sr)TiO₃ thin films is described, The four-layer RuO₂/Ru/TiN/TiSi_x, storage node configuration allows 500°C processing and fine-patterning down to the 0.20 μm size by electron beam lithography and reactive ion etching. Good insulating (Ba_0.4Sr_0.6)TiO₃ (BST) films with an SiO₂ equivalent thickness of 0.65 nm on the electrode sidewalls and leakage current of 1×10^{-/6 A}cm² at 1 V are obtained by ECR plasma MOCVD without any post-deposition annealing, A lateral step coverage of 50% for BST is observed on the 0.2 μm size storage node pattern, and the BST thickness on the sidewalls is very uniform, thanks to the ECR downflow plasma. Using this stacked capacitor technology, a sufficient cell capacitance of 25 fF for 1 Gb DRAMs can be achieved in a capacitor area of 0.125 μm² with only the 0.3 μm high-storage electrodes     

Estimation and compensation of process-induced variations in capacitors for improved reliability in integrated circuits

This paper describes a method for the estimation of capacitor process variations in integrated circuits and for the subsequent compensation of such variations through a calibration scheme that exploits a variable capacitor bank. An architecture for the calibration circuit is proposed, and various problems that arise during implementation are discussed. The design consists of an oscillator whose output frequency is inversely proportional to the capacitor value and simple state machine for measurement of capacitor process variations. The design of optimum capacitor bank is described together with the adequate tuning plan. The circuit is fabricated and verified in 130 nm RF CMOS process and can be easily scaled to sub-100-nm technologies.     

X‐Band Phased Array Antenna Using Ferroelectric (Ba,Sr)TiO3 Coplanar Waveguide Phase Shifter

A phased array antenna was fabricated using four‐element ferroelectric phase shifters with a coplanar waveguide (CPW) transmission line structure based on a Ba0.6Sr0.4TiO3(BST)/MgO structure. Epitaxial BST films were deposited on MgO (001) substrates by pulsed laser deposition. To attain the large differential phase shift and small losses for a ferroelectric CPW phase shifter, an impedance‐matching‐part adding technique between the effective transmission line and connecting cable was used. The return loss and insertion loss for this technique‐adapted BST CPW device were improved with respect to those for a normal BST CPW device. For an X‐band phased array antenna system consisting of ferroelectric BST CPW phase shifters, power divider, dc block, patch antenna, and programmed dc power, the steering beam could be tilted by 15° in either direction.     

A New Automatic Compensation Network for System‐on‐Chip Transceivers

This paper proposes a new automatic compensation network (ACN) for a system‐on‐chip (SoC) transceiver. We built a 5 GHz low noise amplifier (LNA) with an on‐chip ACN using 0.18 µm SiGe technology. This network is extremely useful for today's radio frequency (RF) integrated circuit devices in a complete RF transceiver environment. The network comprises an RF design‐for‐testability (DFT) circuit, capacitor mirror banks, and a digital signal processor. The RF DFT circuit consists of a test amplifier and RF peak detectors. The RF DFT circuit helps the network to provide DC output voltages, which makes the compensation network automatic. The proposed technique utilizes output DC voltage measurements and these measured values are translated into the LNA specifications such as input impedance, gain, and noise figure using the developed mathematical equations. The ACN automatically adjusts the performance of the 5 GHz LNA with the processor in the SoC transceiver when the LNA goes out of the normal range of operation. The ACN compensates abnormal operation due to unusual thermal variation or unusual process variation. The ACN is simple, inexpensive and suitable for a complete RF transceiver environment.