Design of a Sub-1.5 V, 20 MHz, 0.1% MOS Current-Mode Sample-and-Hold Circuit

This paper describes an MOS current-mode sample-and-hold (S/H) circuit that potentially operates with a sub-1.5 V supply voltage, 20 MHz clock frequency, and less than 0.1% linearity. A newly developed voltage-to-current converter suppresses the voltage change at an input terminal and achieves low-voltage operation with superior linearity. Sample switches are differentially placed at the inputs of a differential amplifier so that the feed through errors from switches cancel out. The MOS current mode S/H circuit is designed and simulated using CMOS 0.6 m device parameters. Simulation results indicate that an operation with 20 MHz clock frequency, linearity error of less than 0.1%, and 1 MHz input from a 1.5 V power supply is achievable.     

A reconfigurable two-stage cyclic ADC for low-power applications in 3.3 V 0.35 µm CMOS

This article presents a reconfigurable pipeline analog-to-digital converter (ADC) using a two-stage cyclic configuration. The ADC consists of two stages with 1.5 effective bit resolution, two reference circuits for voltage and current biasing, and a clock generator and timing circuit. Throughout the development of this ADC, several techniques were combined for reducing the power consumption as well as for preserving the converter linearity. To reduce the power consumption, the circuit has a single operational trans-conductance amplifier shared by both pipeline stages. To keep conversion linearity, circuits such as the bootstrapped complementary metal-oxide semiconductor (CMOS) transmission gates and a robust comparator topology were implemented. The circuit can be configured to perform conversion between 7 and 15 bit resolutions, and it works with the master clock frequency in the range of 1 kHz to 40 MHz. The circuit has been prototyped in a 3.3 V 0.35 µm CMOS process and consumes 14.1 mW at 40 MHz and 8 MSample/s sampling rate. With this resolution and sampling rate, it achieves 60.1 dB SNR, 56.57 dB SINAD and 9.1 bit ENOB at 0.666 MHz input frequency and 53.6 dB SNR, 52.4 dB SINAD and 8.6 bit ENOB at 3.85 MHz input frequency. The technological FOM obtained was 13.2 A s/m².     

一种0.18μm数字工艺的12bit 100MS/s流水线型ADC设计

描述一个基于TSMC 0.18μm数字工艺的12 bit 100 Ms/s流水线模数转换器的设计实例。该模数转换器采用1.5bit每级结构,电源电压为1.8V。包括十级1.5 bit/stage和最后一级2bit Flash模数转换器,共产生22bit数字码,数字码经过数字校正电路产生12 bit的输出。该模数转换器省去了采样保持电路,电路模块包括:各个子流水级、共模电压生成模块、带隙基准电压生成模块、开关电容动态偏置模块、系统时钟生成模块、时间延迟对齐模块和数字校正电路模块。为了实现低功耗设计,在电路设计中综合采用了输入采样保持放大器消去、按比例缩小和动态偏置电路等技术。ADC实测结果,当以100 MHz的采样率对10MHz的正弦输入信号进行采样转换时,在其输出得到了73.23dB的SFDR,62.75dB的SNR,整体功耗仅为113mW。     

8位CMOS双通道流水线ADC仿真设计

设计了一种8位1.2V,1GS/s双通道流水线A/D转换器(ADC)。所设计ADC对1.5位增益D/A转换电路(MDAC)中的流水线双通道结构进行改进,其中设置有双通道流水线时分复用运算放大器和双/单通道快闪式ADC,以简化结构并提高速度;在系统前置采样/保持器中加设由单一时间信号驱动的开关线性化控制(SLC)电路,以解决两条通道之间的采样歪扭和时序失调问题。用90nm标准CMOS工艺对所设计的流水线ADC进行仿真试验,结果表明,室温下所设计ADC的信噪比SNR为32.7dB,无杂散动态范围SFDR为42.3dB,它的分辨率、功耗PD和采样速率SR分别为8位、23mW和1GS/s,从而满足了高速、高精度和低功耗的应用需要。     

一种带二进制校正的10位100 MS/s SAR ADC

基于SMIC 65 nm CMOS工艺,设计了一种带二进制校正的10位100 MS/s逐次逼近型模数转换器(SAR ADC),主要由自举开关、低噪声动态比较器、电容型数模转换器(C-DAC)、异步SAR逻辑以及数字纠错电路组成。电容型数模转换器采用带2位补偿电容的拆分单调电容转换方案,通过增加2位补偿电容,克服了电容型数模转换器在短时间内建立不稳定和动态比较器失调电压大的问题,使SAR ADC的性能更加稳定。数字纠错电路将每次转换输出的12位冗余码转换成10位的二进制码。使用Spectre进行前仿真验证,使用Virtuoso进行版图设计,后仿真结果表明,当电源电压为1.2 V、采样率为100 MS/s、输入信号为49.903 MHz时,该ADC的SNDR达到58.1 dB,而功耗仅为1.3 mW。     

A 16-bit cascaded sigma-delta pipeline A/D converter

A low-noise cascaded multi-bit sigma-delta pipeline analog-to-digital converter (ADC) with a low oversampling rate is presented. The architecture is composed of a 2-order 5-bit sigma-delta modulator and a cascaded 4-stage 12-bit pipelined ADC, and operates at a low 8X oversampling rate, The static and dynamic performances of the whole ADC can be improved by using dynamic element matching technique. The ADC operates at a 4 MHz clock rate and dissipates 300 mW at a 5 V/3 V analog/digital power supply. It is developed in a 0.35 μm CMOS process and achieves an SNR of 82 dB.     

Oversampled pipeline A/D converters with mismatch shaping

This paper presents a pipeline analog-to-digital converter (ADC) with improved linearity. The linearity improvement is achieved through a combination of oversampling and mismatch shaping, which modulates the distortion energy out of band. Mismatch shaping can be realized in a traditional 1-bit/stage pipeline ADC, but the ADCs transfer characteristic properties limit its effectiveness at pushing the distortion out of band. These limitations can be alleviated by using a 1-bit/stage commutative feedback capacitor switching pipeline design. A test chip was fabricated in a 0.35-μm CMOS process to demonstrate mismatch shaping. Experimental results obtained indicate that the spurious-free dynamic range improves by 8.5 dB to 76 dB when mismatch shaping is used at an oversampling ratio of 4 and a sampling rate of 61 MHz. The signal-to-noise and distortion ratio improves by 3 dB and the maximum integral nonlinearity decreases from 1.8 to 0.6 LSB at the 12-bit level     

A 16-bit cascaded sigma-delta pipeline A/D converter

A low-noise cascaded multi-bit sigma-delta pipeline analog-to-digital converter （ADC） with a low over-sampling rate is presented. The architecture is composed of a 2-order 5-bit sigma-delta modulator and a cascaded 4-stage 12-bit pipelined ADC, and operates at a low 8X oversampling rate. The static and dynamic performances of the whole ADC can be improved by using dynamic element matching technique. The ADC operates at a 4 MHz clock rate and dissipates 300 mW at a 5 V/3 V analog/digital power supply. It is developed in a 0.35μm CMOS process and achieves an SNR of 82 dB.     

A CMOS switch-capacitor 14-bit 100 Msps pipeline ADC with over 90 dB SFDR

This article presents a design of 14-bit 100?Msamples/s pipelined analog-to-digital converter (ADC) implemented in 0.18?µm CMOS. A charge-sharing correction (CSC) is proposed to remove the input-dependent charge-injection, along with a floating-well bulk-driven technique, a fast-settling reference generator and a low-jitter clock circuit, guaranteeing the high dynamic performance of the ADC. A scheme of background calibration minimises the error due to the capacitor mismatch and opamp non-ideality, ensuring the overall linearity. The measured results show that the prototype ADC achieves spurious-free dynamic range (SFDR) of 91?dB, signal-to-noise-and-distortion ratio (SNDR) of 73.1?dB, differential nonlinearity (DNL) of +0.61/?0.57?LSB and integrated nonlinearity (INL) of +1.1/?1.0?LSB at 30?MHz input and maintains over 78?dB SFDR and 65?dB SNDR up to 425?MHz, consuming 223?mW totally.     

一种12位80 MS/s CMOS流水线ADC设计

介绍了一种12 bit 80 MS/s流水线ADC的设计,用于基带信号处理,其中第一级采用了2.5 bit级电路,采样保持级采用了自举开关提高线性,后级电路采用了缩减技术,节省了芯片面积.采用了折叠增益自举运放,优化了运放的建立速度,节省了功耗.芯片采用HJTC0.18μm标准CMOS工艺,1.8 V电压供电,版图面积2.3 mm × 1.4 mm.版图后仿真表明,ADC在8 MHz正弦信号1 V峰值输入下,可以达到11.10 bit有效精度,SFDR达到80.16 dB,整个芯片的功耗为155 mW.     

用于百万像素级CMOS图像传感器的10位50MS/s流水线ADC设计

噪声和不匹配是流水线ADC中的重要误差源,采用Matlab软件对它们进行了计算和系统仿真.为了在没有降低表现的情况下控制功耗,采用了相同结构放大器共用相同的偏置电路技术,并且采用了共源共栅补偿技术来降低功耗.还设计并且测试了一个可用于大像素规模CMOS图像传感器系统的10位50MS/s流水线ADC原型.根据测试结果,当采样频率为50MHz时功耗仅为42mW,SINAD为45.69dB.设计在表现和功耗上取得了很好的平衡.     

0.13 μm CMOS 60 dB SFDR的8 bit 250 MS/s模数转换器

论述了一种高速度低功耗的8位250 MHz采样速度的流水线型模数转换器(ADC).在高速度采样下为了实现大的有效输入带宽,该模数转换器的前端采用了一个采样保持放大器(THA).为了实现低功耗,每一级的运放功耗在设计过程中具体优化,并在流水线上逐级递减.在250 MHz采样速度下,测试结果表明,在1.2 V供电电压下,所有模块总功耗为60 mw.在19 MHz的输入频率下,SFDR达到60.1 dB,SNDR为46.6 dB,有效比特数7.45.有效输入带宽大于70 MHz.该ADC采用TSMC 0.13μm CMOS 1P6M工艺实现,芯片面积为800 μm×700μm.     

一种用于高速流水线ADC的时钟管理器

文章设计了一种用于高速流水线ADC的时钟管理器,该电路以延迟锁相环(DLL)电路为核心,由偏置电路、时钟输入电路、50%占空比稳定电路和无交叠时钟电路构成。该电路用0.35μmBiCMOS工艺条件下cadence spectre仿真。由测量结果可知,时钟管理器可以实现70MHz~300MHz有效输出。在250MHz典型频率下测得峰值抖动为16ps,占空比为50%,功耗为47mW。仿真结果表明该时钟管理器具有高速度、高精度、低功耗的特点,适用于高速流水线ADC。     

一种10位50MHz流水线模数转换器的设计

采用每级1.5 bit和每级2.5 bit相结合的方法设计了一种10位50 MHz流水线模数转换器。通过采用自举开关和增益自举技术的折叠式共源共栅运算放大器,保证了采样保持电路和级电路的性能。该电路采用华润上华(CSMC)0.5μm 5 V CMOS工艺进行版图设计和流片验证,芯片面积为5.5 mm2。测试结果表明:该模数转换器在采样频率为50 MHz,输入信号频率为30 kHz时,信号加谐波失真比(SNDR)为56.5 dB,无杂散动态范围(SFDR)为73.9 dB。输入频率为20 MHz时,信号加谐波失真比为52.1 dB,无杂散动态范围为65.7 dB。     

High performance 14-bit pipelined redundant signed digit ADC

A novel architecture of a pipelined redundant-signed-digit analog to digital converter(RSD-ADC) is presented featuring a high signal to noise ratio(SNR), spurious free dynamic range(SFDR) and signal to noise plus distortion(SNDR) with efficient background correction logic. The proposed ADC architecture shows high accuracy with a high speed circuit and efficient utilization of the hardware. This paper demonstrates the functionality of the digital correction logic of 14-bit pipelined ADC at each 1.5 bit/stage. This prototype of ADC architecture accounts for capacitor mismatch, comparator offset and finite Op-Amp gain error in the MDAC(residue amplification circuit) stages. With the proposed architecture of ADC, SNDR obtained is 85.89 dB, SNR is 85.9 dB and SFDR obtained is 102.8 dB at the sample rate of 100 MHz. This novel architecture of digital correction logic is transparent to the overall system, which is demonstrated by using 14-bit pipelined ADC. After a latency of 14 clocks, digital output will be available at every clock pulse. To describe the circuit behavior of the ADC, VHDL and MATLAB programs are used. The proposed architecture is also capable of reducing the digital hardware. Silicon area is also the complexity of the design.     

用于巨磁阻生物传感器检测的模拟前端电路

提出一种用于巨磁阻(GMR)生物传感器检测的模拟前端电路。电路采用电压检测的方法,包括基准电压源,单位增益缓冲器,电荷转移型开关电容采样保持电路,流水线模数转换器四部分;基准电压源用于产生传感器阵列的片内激励电压;传感器阵列的检测输出电压经单位增益缓冲器后,由开关电容采样保持电路进行采样,保持,放大;最后经过流水线模数转换器输出数字码流;芯片采用SMIC 0.18μm 1P6M CMOS厚栅氧工艺实现。测试结果表明,在电源电压3.3 V,20 MHz时钟下测试,整体电路输出信号有效精度达到7.2 bit,功耗33 mW,满足GMR生物传感器的检测要求。     

A 4 Gbps current-mode transmitter for 12-bit 250 MSPS ADC

A 4 Gbps transmitter for a 12-bit 250 MSPS pipelined ADCs is presented. A low power current mode (CM) output driver with reverse scaling technique is proposed. A high speed, low power combined serializer is implemented to convert 12 bit parallel data into a seria1 data stream. The whole transmitter is used in a 12-bit 250 MSPS pipelined ADC for the digital output buffer and fabricated in 180 nm 1. 8 V 1P5M CMOS technology. Test results show that the transmitter provides an eye height greater than 800 mV for data rates of both 2 Gbps and 4 Gbps, the 12-bit 250 MSPS ADC achieves the SNR of 69.92 dBFS and SFDR of 81.17 dB with 20.1 MHz input at full sampling speed. The ADC with the 4 Gbps transmitter consumes the power consumption of 395 mW, where the power consumption of transmitter is 75 mW. The ADC occupies an area of 2.5×3.2 mm², where the active area of the transmitter block is 0.5×1.2 mm².     

用于百万像素级CMOS图像传感器的10位50MS/s流水线ADC设计

高速高精度ADC是CMOS图像传感器中的重要部分。随着工艺的进步,低功耗设计已经吸引了很多人的注意。为了在没有降低表现的情况下控制功耗,在本设计采用相同结构放大器共用相同的偏置电路技术,并且采用了共源共栅补偿技术来降低功耗。噪声和不匹配也是流水线ADC中重要的误差源,因此采用了Matlab对这两者进行了仔细的计算和系统仿真。在本文中,提出了一个10位50MS/s的 流水线ADC核心。这个设计可以用于大像素规模的CMOS图像传感器。本设计在表现和功耗上取得了很好的平衡。     

一种应用于流水线ADC采样保持电路的设计

介绍了一种应用于12位、10MS/s流水线模数转换器前端的高性能采样保持（SH）电路的设计。该电路采用全差分电容翻转型结构及下极板采样技术,有效地减少噪声、功耗及电荷注入误差。采用一种改进的栅源电压恒定的自举开关,极大地减小电路的非线性失真。运算放大器为增益增强型折叠式共源共栅结构,能得到较高的带宽和直流增益。该采样保...     

一种低功耗11位100MS/s采样率SAR ADC IP

本文介绍了一种双通道11位100MS/s采样率的混合结构SAR ADC IP。每个通道均采用flash-SAR结构以达到高速低功耗的目的。为了进一步降低功耗,flash和SAR中的比较器均采用全动态比较器。SAR中逐次逼近逻辑所需要的高速异步触发时钟采用门控环形振荡器产生。为了提高电容的匹配性,在版图设计中,采用底板包围顶板的MOM电容结构,有效减小电容寄生。本设计制造工艺为SMIC55nm的低漏电CMOS工艺,双通道的总面积为0.35mm2且核心面积仅为0.046 mm2。双通道模数转换器在1.2V供电电压下消耗的总电流为2.92mA。在2.4MHz输入和50MHz输入下的有效转换位数（ENOB）分别为9.9位和9.34位。计算得出本设计的FOM值为18.3fJ/conversion-step。