一种全新的高性能n－JFET和n－p－n兼容工艺

本文提出了一种全新的ｎ－ＪＦＥＴ和ｎ－ｐ－ｎ兼容工艺，采用二次外延实现了ＪＦＥＴ和ｎ－ｐ－ｎ的隔离。介绍了工艺流程，并对工艺上第一外延的厚度和浓度、二次硼埋浓度以及隔离的温度和时间对ｎ－ＪＦＥＴ的Ｖ＿ｐ和ｎ－ｐ－ｎ管的性能的影响进行了讨论。采用这种工艺研制出了Ｖ＿ｐ达３．５～４．５Ｖ，Ｉ＿（ＤＳＳ）＝１５ｍＡ的ＪＦＥＴ和ｆ＿Ｔ＝８００ＭＨｚ，β＝１００，ＢＶ＿（ｃｅｏ）≥２５Ｖ的ｎ－ｐ－ｎ管，并成功运用于调制解调开关侧音放大器中。     

一种新型结构的LB膜化学场效应晶体管的气敏特性研究

合成了新型的有机半导体ＬＢ膜气敏材料（ＣＯＴＤＭＡＰＰ），其ＬＢ多层膜拉制在场效应晶体管上，形成了具有ＬＢ－ＯＳＦＥＴ结构的化学场效应晶体管（ＣｈｅｒｎＦＥＴ），该器件置于ＮＯ２，ＮＨ３，ＣＯ和Ｈ２Ｓ等有害气体中，结果表明在ＮＯ２气氛中元件漏电流ＩＤＳ发生变化，并可检测到２ｐｐｍ的ＮＯ２．这种器件的气敏特性在于ＦＥＴ的电流放大作用及ＬＢ膜的有序性的影响．     

有问有答

有问有答问１：我单位需要一种型号为ＩＣＬ８００７ＣＴＶ的金属封装（８脚）器件，请问有无代用品或仿制品，性能如何？沈阳李顺德问）答ＩＣＬＳ００７ＣＴＶ是７０年代早期生产的高阻输人运算放大器，输入级为ＭＯＳ－ＦＥＴ，输人电流约１ｐＡ，３ｄＢ带宽约１ＭＨｚ...     

元器件快讯

表封式压控振荡器Ｍｉｎｉ -Ｃｉｒｃｕｉｔｓ生产的ＪＴＯＳ -１５５０型宽带表封式压控振荡器的工作频率范围为１１５０～１５５０ＭＨｚ,具有２２～３２ＭＨｚ（典型）的线性调谐特性。此振荡器的典型功率输出为７ｄＢｍ,在１００ｋＨｚ的间隔下具有 -１２１ｄＢｃ／Ｈｚ的低ＳＳＢ相位噪声、 -２０ｄＢｃ的谐波压缩率和０．５～２０．０Ｖ（最小到最大）的调谐电压。这款压控振荡器尤其适用于ＧＰＳ应用系统。咨询编号 :０１１１４０更小的集成式开关国际整流器公司推出了高效、低成本强化ＩＲＩＳ集成开关 ,它将ＨＥＸＦＥＴ功率ＭＯ…     

0．1μm NMOSFET沟道δ－掺杂与结构特性

沟道δ－形掺杂对于改善极小尺寸ＭＯＳＦＥＴ性能、提高可靠性极其重要。利用能量输运模型（ＥＴＭ），报道了沟道δ－形掺杂分布对０．１μｍ沟长ＮＭＯＳＦＥＴ结构特性的影响，根据漏源电流ＩＤＳ、截止态电流Ｉｏｆｆ、阈值电压ＶＴＨ和Ｓ因子的要求，提出了使性能和可靠性得到优化的δ－形掺杂分布。     

CHINESE JOURNALOFL ASERS B Vol. B4, No.1(Series No.19),February 20,1995

ＣＨＩＮＥＳＥＪＯＵＲＮＡＬＯＦＬＡＳＥＲＳＢＶｏｌ．Ｂ４，Ｎｏ．ｌ（ＳｅｒｉｅｓＮｏ．１９），Ｆｅｂｒｕａｒｙ２０，１９９５（Ｊａｎｕａｒｙ／Ｆｅｂｒｕａｒｙ）CHINESE JOURNALOFL ASERS B Vol. B4, No.1(Series No.19),February 20,199...     

硅微波功率DMOSFET发展现状

简要地评述了硅微波功率ＤＭＯＳＦＥＴ（ＬＤＭＯＳ,ＶＤＭＯＳ）的发展概况,叙述了硅微波功率ＤＭＯＳ的基本结构和一些重要的制造技术。对微波功率ＤＭＯＳ的性能,特点与ＢＪＴ进行了比较,并对其应用,发展方向及前景进行了探讨。     

硅微波功率DMOSFET发展现状

简要地评述了硅微波功率ＤＭＯＳＦＥＴ （ＬＤＭＯＳ, ＶＤＭＯＳ） 的发展概况, 叙述了硅微波功率ＤＭＯＳ的基本结构和一些重要的制造技术。对微波功率ＤＭＯＳ的性能、特点与ＢＪＴ进行了比较, 并对其应用、发展方向及前景进行了探讨。     

GaAs MESFET中肖特基势垒接触退化机理的研究

本文对Ｔｉ／Ｍｏ／Ｔｉ／Ａｕ作为栅金属的ＧａＡｓＭＥＳＦＥＴ进行了四种不同的应力试验：１．高温反偏（ＨＴＲＢ）；２．高压反偏（ＨＲＢ）；３．高温正向大电流（ＨＦＧＣ）；４．高温存贮（ＨＴＳ）．通过ＨＲＢ，ΦＢ从０．６４ｅＶ减少到０．６２ｅＶ，理想因子ｎ略有增大．ＨＴＳ试验中ΦＢ从０．６７ｅＶ增加到０．６９ｅＶ．分析表明，这归因于界面氧化层的消失，以及Ｔｉ与ＧａＡｓ的反应；ＨＦＧＣ试验结果表明其主要的失效模式为烧毁，ＳＥＭ观察中有电徙动及断栅现象发生．ＡＥＳ分析表明。应力试验后的样品，肖特基势垒接触界面模糊     

双极型压控晶体管直流特性的数值模拟

本文采用数值计算和解析分析相结合的方法,建立了新型功率半导体器件－－有型压控晶体管（ＢＪＭＯＳＦＥＴ）电流－电压特性的数值分析模型;运用Ｍａｔｈｅｍａｔｉｃｓ数学分析软件,模拟得出ＢＪＭＯＳＦＥＴ电压转移特性曲线和电压输出特性曲线;得出的结果说明在相同的器件结构尺寸和工作情况下,与功率ＭＯＳ晶体管相比,导通电压略有增加,但电流容量增加较大。     

SOI结构P型SiGe沟道混合模式晶体管器件模型研究

在带有应变SiGe沟道的SOIMOSFET结构中 ,把栅和衬底相连构成了新型的混合模式晶体管 (SiGeSOIBMHMT) .在SIVACO软件的器件数值模拟基础上 ,对这种结构的P型沟道管工作过程作了分析 ,并建立了数学模型 .提出在低电压 (小于 0 7V)下 ,衬底电极的作用可近似等效成栅 ,然后依据电荷增量 (非平衡过剩载流子 )的方法 ,推导出该结构的I V特性方程 .该方程的计算结果与器件模拟结果相一致.     

一种考虑复合电流的SiC LBJT行为模型改进

介绍了一种考虑基区SiC/SiO₂界面处复合电流的SiC LBJT改进模型。分析了横向碳化硅双极结型晶体管与其垂直结构之间的区别,将横向BJT的外延层和半绝缘机构等效为衬底电容。再引入一个平行于SiC BJT基极结的附加二极管来描述复合电流,以垂直SiC BJT的SGP模型为基础建立SiC LBJT行为模型。校准了LBJT模型的基区渡越时间,模型与实际器件的开关特性接近吻合。相较于未考虑复合电流的LBJT模型,改进后的模型输出特性曲线与实测数据精度误差较小。该模型可以较精确地描述受复合电流影响的LBJT器件行为。     

一种积累型槽栅超势垒二极管

提出了一种积累型槽栅超势垒二极管,该二极管采用N型积累型MOSFET,通过MOSFET的体效应作用降低二极管势垒。当外加很小的正向电压时,在N+区下方以及栅氧化层和N-区界面处形成电子积累的薄层,形成电子电流,进一步降低二极管正向压降;随着外加电压增大,P+区、N-外延区和N+衬底构成的PIN二极管开启,提供大电流。反向阻断时,MOSFET截止,PN结快速耗尽,利用反偏PN结来承担反向耐压。N型积累型MOSFET沟道长度由N+区和N外延区间的N-区长度决定。仿真结果表明,在相同外延层厚度和浓度下,该结构器件的开启电压约为0.23 V,远低于普通PIN二极管的开启电压,较肖特基二极管的开启电压降低约30%,泄漏电流比肖特基二极管小近50倍。     

国产中高压抗辐照功率MOSFET单粒子效应

功率金属-氧化物半导体场效应晶体管(MOSFET)空间使用时易遭受重离子轰击产生单粒子效应(单粒子烧毁和单粒子栅穿)。本文对国产新型中、高压(额定电压250 V,500 V)抗辐照功率MOSFET的单粒子辐射效应进行了研究,并采取了有针对性的加固措施,使器件的抗单粒子能力显著提升。结果表明：对250 V KW2型功率MOSFET器件进行Bi粒子辐照,在栅压等于0 V时,安全工作的漏极电压达到250 V;对500 V KW5型功率MOSFET器件进行Xe粒子辐照,在栅压等于0 V时,安全工作的漏极电压达到400 V,并且当栅压为-15 V时,安全工作的漏极电压也达到400 V,说明国产中、高压功率MOSFET器件有较好的抗单粒子能力。     

Dynamic threshold-voltage MOSFET (DTMOS) for ultra-low voltage VLSI

In this paper, we propose a novel operation of a MOSFET that is suitable for ultra-low voltage (0.6 V and below) VLSI circuits. Experimental demonstration was carried out in a Silicon-On-Insulator (SOI) technology. In this device, the threshold voltage of the device is a function of its gate voltage, i.e., as the gate voltage increases the threshold voltage (V_t) drops resulting in a much higher current drive than standard MOSFET for low-power supply voltages. On the other hand, V_t is high at V_gs=0, therefore the leakage current is low. We provide extensive experimental results and two-dimensional (2-D) device and mixed-mode simulations to analyze this device and compare its performance with a standard MOSFET. These results verify excellent inverter dc characteristics down to V_dd=0.2 V, and good ring oscillator performance down to 0.3 V for Dynamic Threshold-Voltage MOSFET (DTMOS)     

槽栅型SiC MOSFET器件单粒子响应特性研究

利用TCAD Sentaurus模拟仿真软件,研究分析了三种不同结构的槽栅型1 200 V SiC MOSFET单粒子响应特性,器件包括传统单沟槽MOSFET、双沟槽MOSFET和非对称沟槽MOSFET结构。仿真结果表明,双沟槽MOSFET的抗单粒子特性优于其它两种结构器件。通过分析可知,双沟槽MOSFET结构的优越性在于有较深的源极深槽结构,有助于快速收集单粒子碰撞过程产生的载流子,从而缓解大量载流子聚集带来的内部电热集中,相比其它两种结构能有效抑制引起单粒子烧毁的反馈机制。     

功率MOSFET参数测试仪的设计

功率MOSFET参数测试仪是用来测试功率MOSFET电特性参数的仪器设备（如阈值电压、跨导等）。以单片机为核心,介绍功率MOSFET参数测试仪的原理、设计及实现,设计了电特性参数测试的具体电路,编写了测试控制程序,通过对设计出的测试仪系统进行实验和调试,可以准确测量功率MOSFET的阈值电压、跨导、栅源漏电流、零栅压漏极电流及耐压。     

A reverse-voltage protection circuit for MOSFET power switches

When MOSFET is used as a power switch, it is essential to prevent reverse current flow through the parasitic body diodes under reverse voltage condition. A new built-in reverse voltage protection circuit for MOSFETs has been developed. In this design, an area-efficient circuit is used to automatically select the proper well bias voltage to prevent reverse current under the reverse-voltage condition. This built-in reverse protection circuit has been successfully implemented in a high-side power switch application using a 0.6-μm CMOS process. The die area of the protection circuit is only 2.63% of that of a MOSFET. The latch-up immunity is greater than +12 V and -10 V in voltage triggering mode, and greater than ±500 mA in current triggering mode. The protection circuit is not in series with the MOSFET switch, so that the full output swing and high power efficiency are achieved     

An analytical drain current model for dual material engineered cylindrical/surrounded gate MOSFET

In this paper, a drain current model incorporating drain-induced barrier lowering (DIBL) has been developed for Dual Material gate Cylindrical/Surrounding gate MOSFET (DMG CGT/SGT MOSFET) and the expressions for transconductance and drain conductance have been obtained. It is shown that DMG design leads to drain current enhancement and reduced output conductance. The effectiveness of DMG design was scrutinized by comparing with single metal gate (SMG) CGT/SGT MOSFET. Moreover, the effect of technology parameters variations workfunction difference has also been presented in terms of gate bias, drain bias, transconductance and drain conductance. Results reveal that the DMG SGT/CGT devices offer superior characteristics as compared to single material gate CGT/SGT devices. A good agreement between modeled and simulated results has also been obtained thus providing the validity of proposed model.     

Design and performance analysis of cylindrical surrounding double-gate MOSFET for RF switch

In this paper, we have analyzed the design parameters of Cylindrical Surrounding Double-Gate (CSDG) MOSFETs as an RF switch for the advanced wireless telecommunication systems. The proposed CSDG RF MOSFET is operated at the microwave regime of the spectrum. We emphasize on the basics of the circuit elements such as drain current, threshold voltage, resonant frequency, resistances at switch ON condition, capacitances, energy stored, cross talk and switching speed required for the integrated circuit of the radio frequency sub-system of the CSDG RF CMOS device and the physical significance of these basic circuit elements is also discussed. We observed that the total capacitance between the source to drain for the proposed CSDG MOSFET is more compared to the Cylindrical Surrounding Single-Gate (CSSG) MOSFET due to the greater drain current passing area of the CSDG MOSFET, which reveals that the isolation is better in the CSDG MOSFET compared to that of the simple double-gate MOSFET and single-gate MOSFET. We analyzed that the CSDG MOSFET stores more energy (1.4 times) as compared to the CSSG MOSFET. Therefore, the CSDG MOSFET has more stored energy. The ON-resistance of CSDG MOSFET is half than that of the double-gate MOSFET and single-gate MOSFET, which reveals that the current flow from source to drain in CSDG MOSFET is better than the double-gate MOSFET and single-gate MOSFET.