Computer-aided design of a BPSK spread-spectrum chip set

The design of a binary-phase shift-keyed (BPSK) spread-spectrum chip set with an integrated CAD environment called VANDA is described. VANDA uses the functional compiler concept to integrate system and physical designs, thus allowing complex high-performance integrated circuit chips to be implemented easily. Three functional compilers have been designed and implemented for the design of a spread-spectrum transceiver: a pseudonoise (PN) generator compiler, a direct digital frequency synthesizer (DDFS) compiler, and a Costas loop compiler. Three test chips for a BPSK digital intermediate frequency (IF) spread-spectrum system generated by these compilers have been fabricated and tested. Details of each of the functional compilers and the test chips are described. In addition, the measurement results for digital IF transceiver test boards constructed using these chips are presented     

Retargetable Code Generation Based on Structural Processor Description

Design automation for embedded systems comprising both hardware and software components demands for code generators integrated into electronic CAD systems. These code generators provide the necessary link between software synthesis tools in HW/SW codesign systems and embedded processors. General-purpose compilers for standard processors are often insufficient, because they do not provide flexibility with respect to different target processors and also suffer from inferior code quality. While recent research on code generation for embedded processors has primarily focussed on code quality issues, in this contribution we emphasize the importance of retargetability, and we describe an approach to achieve retargetability. We propose usage of uniform, external target processor models in code generation, which describe embedded processors by means of RT-level netlists. Such structural models incorporate more hardware details than purely behavioral models, thereby permitting a close link to hardware design tools and fast adaptation to different target processors. The MSSQ compiler, which is part of the MIMOLA hardware design system, operates on structural models. We describe input formats, central data structures, and code generation techniques in MSSQ. The compiler has been successfully retargeted to a number of real-life processors, which proves feasibility of our approach with respect to retargetability. We discuss capabilities and limitations of MSSQ, and identify possible areas of improvement.     

Performance Monitoring and Assessment of Embedded HW/SW Systems

Performance assessment of embedded HW/SW systems built with various types of VLSI components, i.e. heterogeneous multi-processor architectures, is important to help the development of complex real-time applications. To design such a tool, two issues must be solved: the gathering of relevant information simultaneously on several components without disturbing the application behavior, display of the performance results in a way that can be easily interpreted by designers. This paper presents a significant solution for the two above issues. We first describe what the goal for designers is and what kind of applications are concerned. Then we describe the principle of collecting an event trace and the technique to evaluate the selected performance indexes. The monitoring technique, based on a specific ASIC, is non-intrusive and allows our tool to capture real-time event occurrences from software tasks, and even from hardware functions implemented in ASICs. Each event is automatically time-stamped, collected and processed in real-time to evaluate the performance indexes selected by the designer. We also describe the display tool which clearly shows the results to the designer according to different representations. This technique and the associate real-time performance analyzer are integrated in a complete development process based on the MCSE methodology.     

A Formal Approach to On-Line Monitoring of Digital VLSI Circuits: Theory,Design and Implementation

This work is concerned with the development of algorithms and CAD tools for the design of digital circuits with on line monitoring capability. The Theory of Fault Detection and Diagnosis available in the literature on Discrete Event Systems has been adopted for on-line detection of stuck-at faults in Digital Circuits. Efficient computational techniques to deal with very large state spaces based on Ordered Binary Decision Diagrams and Abstraction have been proposed. Based on these a CAD tool has been developed that can provide a fully automated flow for design of circuits with on-line test capability without the requirement of any modification to the core. The tool can handle generic digital circuits with cell count as high as 15,000 and having the order of 2⁵⁰⁰ states. This is believed to be an improvement of an order of magnitude over results presented in the literature. This methodology enables the designer to tradeoff fault coverage and detection latency against area and power overhead. The design flow using the CAD tool developed is described and results for design of on-line detectors for various ISCAS89 benchmark circuits are provided. The methodology is further validated by design, fabrication, and testing of an ASIC in 0.18 μ technology.     

Technology transfer between VLSI design and software engineering: CAD tools and design methodologies

Recent research on the explicit transfer of technology used in computer-aided design (CAD) tools and design methodologies is reported. First, several examples are given of applications of these technologies to software engineering. Then, three research projects are described which focused on applying software engineering principles to the VLSI design process. They are: a methodology, language, and assessment tool for multilevel mixed-mode VLSI designs; a research project that explored the potential for transfer of software design methodologies for managing VLSI design complexity; and a specification technique for "modules" in a VLSI design that localizes the impact of changes to the design. Next, a CAD tool and design methodology are described which consider the design of software and hardware together, and apply common techniques to both. Finally, some observations are made on the appropriateness of technology transfer between VLSI design and software engineering.     

Synthesis for real time systems: Solutions and challenges

A real time system typically combines a variety of implementation technologies and hardware architectures. Deciding how to partition the system and selecting an architectural technology for the sub-systems is by no means a trivial task. These architectural decisions, which can have a major impact on the quality and performance of the final implementation, have to be made at the early stages in the design process, when the impact of the decisions is unclear and can only be quantified using some primitive measures. p ]In this paper, we present our vision on how a next generation of design environment can aid the designer in this decision process. We first identify the problems of designing a heterogeneous real time system by walking through the design process of a complex speech recognition system. Based on this analysis, we propose a system design methodology build on top of current synthesis tools. Today, DSP synthesis tools are application and/or architecture specific, covering subparts of the application once the partitioning is made. To make them useful in the proposed methodology, a unified view on the underlying architecture assumptions is needed. Secondly, good decision making requires an “as-good-as-possible” estimation of the implications of the decision. Therefore, it is important that current manual estimation be enlarged by high level estimation and performance analysis tools. p ]The HYPERSPACE environment, which is currently under development, therefore, consists of three complementary components: a set of architecture specific compilers, a set of estimation and performance analysis tools and an architecture selection and partitioning framework, steered by the designer.     

FPGA Implementation of Embedded Fuzzy Controllers for Robotic Applications

Fuzzy-logic-based inference techniques provide efficient solutions for control problems in classical and emerging applications. However, the lack of specific design tools and systematic approaches for hardware implementation of complex fuzzy controllers limits the applicability of these techniques in modern microelectronics products. This paper discusses a design strategy that eases the implementation of embedded fuzzy controllers as systems on programmable chips. The development of the controllers is carried out by means of a reconfigurable platform based on field-programmable gate arrays. This platform combines specific hardware to implement fuzzy inference modules with a general-purpose processor, thus allowing the realization of hybrid hardware/software solutions. As happens to the components of the processing system, the specific fuzzy elements are conceived as configurable intellectual property modules in order to accelerate the controller design cycle. The design methodology and tool chain presented in this paper have been applied to the realization of a control system for solving the navigation tasks of an autonomous vehicle.     

基于硬件性能计数器的编译器性能测试与分析

Itanium 2处理器提供的性能监控单元实现了在程序运行过程中捕捉微结构事件的功能.利用GNU Gcc、Intel Icc和HP-Opencc编译器的不同优化选项编译并运行SPEC2006基准程序.通过CPU硬件计数器(HPCs)采集的性能数据,了解特定程序特征,分析比较编译器性能差异,对HP-Opencc编译器的性能优化给出相关参考数据.实验表明HP-Opencc编译器的的分支预测优化技术可再改进.     

Approaching a machine-application bound in delivered performance onscientific code

A performance bounding methodology that explains the performance of loop-dominated scientific applications on particular systems is presented. The throughput of key hardware units that are common bottlenecks in concurrent machines is modeled. A workload characterization is proposed, and upper bounds on the performance of specific machine-workload pairs are derived. Comparing delivered performance with bounds focuses attention on areas for improvement and indicates how much improvement might be attainable. A detailed analysis and performance improvement effort for the IBM RS/6000 produced an average lower bound of 1.27 clocks per floating-point operation (CPF), whereas machine peak performance is 0.5 CPF and the V2.01 Fortran compiler attains only 2.43 CPF. Code improvements in this study have achieved 1.36 CPF, increasing the harmonic mean steady-state inner loop performance to 97.6% of the MFLOPS bound. Subsequently, the V2.02 compiler achieved 1.75 CPF, and 1.60 with carefully chosen preprocessing     

Compiling for EPIC architectures

Designing compilers for Explicitly Parallel Instruction Computing (EPIC.) architectures presents challenges substantially different from those encountered in designing compilers for traditional sequential architectures. These challenges are addressed not only by employing new optimizations that are specific to EPIC, but also by employing new ways to architect compilers. EPIC architectures provide features that allow compilers to take a proactive role in exploiting instruction level parallelism. Compiler technology is intimately intertwined with the target processor architecture, and compiler architects must solve new analysis and optimization problems to achieve the highest levels of performance. When complex optimizations are uniformly applied to large applications, the resulting slow compile speeds are unacceptable. Demanding requirements to produce high-quality code at high compile speed shapes the fundamental structure of EPIC compilers     

Development of design flow for multiported register files,which includes a cell library and a compiler for SOI 0.25-μm process

A typical design flow for a high-performance System-on-Chip usually includes memory compilers, which are implemented by different CAD producers for a given technology. These compilers allow to create automatically all file views for a memory unit using its configuration given by a user. However, there was no memory compiler for a 0.25-micron CMOS SOI process used in some our projects. At the same time, chips we were developing in this process had a wide variety of memories including register files. We developed new design approach and patented a multiported modular bitcell. Additionally, a schematic and layout library of basic cells was created to implement register files with different number of read and write ports. This gave rise to development of design flow and a program, which generates typical file views automatically.     

Challenges and Opportunities in Many-Core Computing

In this paper, we present some of the challenges and opportunities in software development based on the current hardware trends and the impact of massive parallelism on both the software and hardware industry. We indicate some of the approaches that can enable software development to effectively exploit the many-core architectures. Some of these include encapsulating domain-specific knowledge in reusable components, such as libraries, integrating concurrency with languages, and supporting explicit declarations to help compilers and operating system schedulers. Tighter interaction between software and underlying hardware is required to build scalable and portable applications with predictable performance and higher power-efficiency. Overall, many-core computing provides us opportunities to enable new application scenarios that support enhanced functionality and a richer experience for the user on commodity hardware.     

Broadway: A Compiler for Exploiting the Domain-Specific Semantics of Software Libraries

This paper describes the Broadway compiler and our experiences in using it to support domain-specific compiler optimizations. Our goal is to provide compiler support for a wide range of domains and to do so in the context of existing programming languages. Therefore, we focus on a technique that we call library-level optimization, which recognizes and exploits the domain-specific semantics of software libraries. The key to our system is a separation of concerns: compiler expertise is built into the Broadway compiler machinery, while domain expertise resides in separate annotation files that are provided by domain experts. We describe how this system can optimize parallel linear algebra codes written using the PLAPACK library. We find that our annotations effectively capture PLAPACK expertise at several levels of abstraction and that our compiler can automatically apply this expertise to produce considerable performance improvements. Our approach shows that the abstraction and modularity found in modern software can be as much an asset to the compiler as it is to the programmer.     

A Compiler-Friendly RISC-Based Digital Signal Processor Synthesis and Performance Evaluation

As DSP (Digital Signal Processing) applications become more complex, there is also a growing need for new architectures supporting efficient high-level language compilers. We try to synthesize a new DSP processor architecture by adding several DSP processor specific features to a RISC core that has a compiler friendly structure, such as many general-purpose registers and orthogonal instructions. The synthesized digital signal processor supports single-cycle MAC (Multiply-and-ACcumulate), direct memory access, automatic address generation, and hardware looping capabilities in addition to ordinary RISC instructions. The compiler for the new architecture is quickly implemented by developing a code-converter that modifies the assembly codes that are generated by the RISC compiler. The performance effects of adding each of these as well as all the combined features are evaluated using seven DSP-kernel benchmarks, a QCELP vocoder, and an MPEG video decoder. The effects of CPU clock frequency change due to the addition of these features are also considered. Finally, we also compare the performances with several existing DSP processors, such as TMS320C3x, TMS320C54x, and TMS320C5x.     

面向对象的智能化FBM CAD系统

以UML为建模语言,Rational ROSE为工具,建立了基于面向对象技术的智能化耐火砖模具CAD系统。该系统利用面向对象的机制将常见的耐火砖原型按其拓扑结构关系建立基类,在用户仅输入成品耐火砖各项参数的情况下,自动生成边、堵、底、盖等6个模板的三维实体,进而生成其零件图。同时,由于充分利用类的继承与派生,使系统具有良好的可扩充性。     

Electronic CAD frameworks

The CAD framework, i.e. the underlying facilities provided to the CAD tool developer, the CAD system integrator, and the end-user (IC or system designer) to facilitate their tasks, is discussed. The development of the CAD framework concept in the domain of electronic circuit design is reviewed. The most important work in the area is briefly described. The major components of a CAD framework are identified, and the requirements and desirable features of these components are described in some detail. Many of the key engineering tradeoffs required to build CAD frameworks are examined, using examples from existing CAD systems. Framework standardization efforts are also reviewed